JP2005032107A - Av system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an AV system which can suppress the wasteful use of a system bus by completing data transfer at one stroke. <P>SOLUTION: The AV system, having a CPU D9, a memory D12, an I/O device, device control parts D5-D8, a system bus, and a bus arbitration control part in which the system bus supports burst transfer as a high-speed data transfer mode and right of use for the bus corresponding to bus requests from a plurality of bus masters is arbitrated, is configured with a data transfer control part D10 for executing one to many broadcast which transfers one block data with a certain size to a plurality of devices in one bus cycle utilizing a burst transfer function on the system bus. In this AV system, the device control parts D5-D8 of transfer destinations have a means for holding a transfer destination address in order to transfer the data received on the device or the memory. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an AV system, and more particularly to a processing apparatus that handles digital AV (Audio Video) data.

  BS broadcast receivers and CS broadcast receivers compatible with digital broadcasting in recent years, DVD recorders that record and play back video and audio data converted to digital data on disks such as DVD-RW, DVD-RAM, and DVD-R, A video recording / reproducing apparatus equipped with a hard disk (hereinafter abbreviated as “HDD”) generally has a system configuration as shown in FIG.

  For example, when a digital broadcast is received and viewed on a TV, the digital tuner unit A-1 demodulates the antenna signal to be input and outputs a TS (transport stream) signal. This TS signal is subjected to DEMUX processing by the TS data control unit A-4 on the system information and the like multiplexed on the TS, and the next-stage MPEG2 decoding processing unit A-5 outputs AV-out. A TS signal used in digital broadcasting is transmitted from a broadcasting station by compressing source video and audio signals in the MPEG2 format, multiplexing each information in a TS format stream. Therefore, in order to receive and view a digital broadcast, the MPEG2 decoding processing unit A-5 that decompresses the video and audio data compressed in this way is required. After being expanded by the MPEG2 decoding processing unit A-5, D / A conversion is performed, and analog video and audio signals are output as AV-out. By connecting this signal to the AV input terminal of the TV, video and audio can be viewed. It is possible to do.

  Next, a case where video and audio are recorded / reproduced in a recorder with a built-in HDD will be described. First, for recording to the HDD, when the signal to be recorded is an analog external input signal AV-in, the MPEG2 encoding processing unit A-2 compresses and converts the signal to the above-described TS signal. The TS signal is reconfigured in the TS data control unit A-4 by the same DEMUX processing and TS packet data as unit data managed by the system, and the block data is transferred to the HDD control unit A via the system bus. Data is transferred to -11. The HDD controller A-11 sequentially writes this data to the HDD (A-12), so that the video and audio signals finally input from the AV-in are recorded on the HDD (A-12).

  With respect to the operation via the system bus, several control methods can be adopted. The TS data control unit A-4 transfers the memory to the memory unit A-9 through the memory control unit A-8 once. Among these processes, buffering is performed, and then data is transferred from the memory unit A-9 to the HDD control unit A-11 via the memory control unit A-8 using a DMA (direct memory access) control unit A-10. It is one of.

  For playback from the HDD, the HDD controller A-11 reads the data recorded in the HDD (A-12) by recording, and the read data is block data of a management unit via the system bus and the TS data controller. Data is transferred to A-4. This block data is subjected to TS packetization processing again in the TS data control unit A-4, and then video and audio signals are output as AV-out by the same processing as when viewing digital broadcasts. Video and audio can be viewed by connecting to the input terminal.

  At this time, depending on the performance of the system, it is possible to simultaneously process the recording to the HDD and the reproduction from the HDD, and it is also possible to realize so-called “chase reproduction” in which the recording and reproduction times are shifted.

  The viewing of the digital broadcast receiver as described above and the recording and reproduction of the HDD recorder are all controlled by the CPU (A-7) via the system bus.

  Digital video receivers and DVD recorders have fixed video and audio compression methods, and the streams handled are limited to TS or PS (program stream: stream format used in DVD). As general-purpose LSIs used, dedicated LSIs specialized for these methods are developed. As for the digital tuner unit A-1, MPEG2 encoding processing unit A-2, IEEE 1394 control unit A-3, and MPEG2 decoding processing unit A-5, TS signals conforming to the MPEG2 system are directly input / output as shown in FIG. Designed to be able to. By using such an LSI, there is an advantage that a system for processing TS signals compliant with the MPEG2 system can be greatly simplified.

  FIG. 1 shows a system that is generally used when developing a device corresponding to a standardized system. On the other hand, in the system configuration shown in FIG. 2, the TS signal path shown in FIG. 1 does not exist. . This indicates that all the TS signal input / output processing performed in FIG. 1 is performed via the system bus. Such a configuration is a system configuration that is very useful for adapting to various usage scenes and systems.

  As an operation example, a case where video and audio are recorded / reproduced in a recorder with a built-in HDD will be described with reference to FIG. First, in recording to the HDD, when the recording signal is an analog external input signal AV-in, the compression processing unit B-2 digitizes the analog input signal and converts it into compressed data. The compressed data is transferred from the compression processing unit via the system bus to the memory unit B-9 via the memory control unit B-8. The block data transferred to the memory unit B-9 is subjected to necessary processing by the CPU (B-7), and then the DMA (direct memory access) control unit B-10 is a unit (block data size) managed by the system. Data is transferred from the memory unit B-9 via the system bus to the HDD control unit B-11 via the memory control unit B-8.

  The HDD controller B-11 sequentially writes this data to the HDD (B-12), so that video and audio signals finally input from the AV-in are recorded on the HDD.

  For playback from the HDD, the HDD control unit B-11 reads the data recorded in the HDD (B-12) by recording, and the read data is block data of a management unit via the system bus and the decompression processing unit B. Data is transferred to -5. This block data is decompressed in the decompression processing unit B-5, then D / C converted, and analog video and audio signals are output as AV-out. By connecting this signal to the AV input terminal of the TV, the video data It is also possible to view audio.

  In the system of FIG. 2 as well, it is possible to simultaneously process the recording to the HDD and the reproduction from the HDD depending on the performance of the system, and it is possible to realize the so-called “chase reproduction” in which the recording and reproduction times are shifted. .

  In the case of the system configuration of FIG. 1, since the TS signal control is performed by each signal processing unit (dedicated LSI) having TS signal input / output, the burden on the CPU is reduced. However, since it is specialized in a standardized system, it is not suitable for using a stream of a different system depending on the application. In the case of the system shown in FIG. 2, the data transfer can be performed regardless of the stream format, so the system configuration can be applied. However, since all data transfer is performed via the system bus, a bandwidth is secured for the system bus data transfer. Is required.

  Although it is a special condition, depending on the system, a system that processes applications such as receiving, compressing, and storing multiple images in real time while simultaneously delivering a single stored content via different media in real time If you think about it, the bandwidth of the system bus will be inadequate. In addition, since the CPU intervenes in all the controls, the overhead for control and the system bus are used for data transfer. Therefore, the response when the CPU performs the control via the system bus, that is, further securing of the bandwidth is required.

  The methods for increasing the bandwidth include expanding the bus bit width, increasing the operating frequency, and separating the bus for each function, but the effects of this increase costs such as increased power consumption, noise suppression, and increased component costs. It becomes a factor of up.

  An object of the present invention is to solve the conventional problem and to provide an AV system capable of suppressing use of a useless system bus by being completed by one data transfer.

  In order to solve the above problems, the present invention relates to the means shown in the items 1 to 17 as means for indicating that the bus operation mode executed by the DMA in the system bus specification is a one-to-many data transfer mode. Means for arbitrating data transfer timing so as to replace a DMA transfer request from a plurality of media (DMA transfer request sources) with one data transfer, and address information on the system bus in response to a data transfer request from a plurality of media And a data buffer means for improving the data transfer rate on the data output side, and a data buffer means on the data receiving side.

  According to the present invention, the means for realizing the one-to-many data transfer transfers one block data to a plurality of media (input / output processing units) having different data request sources in one burst data transfer cycle. Allows the transfer to be completed. For this reason, useless use of the system bus can be suppressed, and the throughput of the system bus can be improved.

  According to the present invention, it is possible to obtain an AV system capable of suppressing useless use of a system bus by completing the data transfer once.

  An embodiment of the present invention will be described.

  The following is a detailed description of the AV system of the present invention. In the following embodiments, description will be made by a method using a system configured to transfer all data via the system bus shown in FIG. First, the superiority of the present invention will be briefly described with reference to FIGS. 3, 4, 5 and 6. FIG. FIG. 3 shows an image of conventional AV data transfer, and FIG. 4 shows an image of AV data transfer of the present invention.

  The functional modules constituting the system in FIGS. 3 and 4 are the same, and are briefly described below. HDDs (hard disks) C-1 and D-1 record and store digital AV data. Digital tuner units C-2, C-3, D-2, and D-3 demodulate antenna input signals and receive AV data compressed in MPEG2 in a TS format stream. The HDD control units C-4 and D-4 control access related to recording and reproduction with respect to the HDD. The IEEE1394 control units C-5 and D-5 control input / output of data via iLINK. The LAN1 controllers C-6 and D-6 control data input / output via the LAN (local area network) 1. The LAN2 controllers C-7 and D-7 control data input / output via the LAN (local area network) 2. The MPEG2 decompression units C-8 and D-8 decompress the digital AV data compressed in the MPEG2 format, convert it into an analog signal, and output it as an AV signal. CPUs (C-9, D-9) are processor processing units that control the entire system. The memory control units C-10 and D-10 control access to the memories C-12 and D-12. The DMA control units C-11 and D-11 control data transfer via the system bus. However, each functional module in FIG. 4 has the characteristics shown in Items 1 to 17 which are the characteristics of the present invention.

  3 and 4 both show a state in which the following series of operations are simultaneously processed in real time.

  1) While receiving two programs at the same time with the digital tuner units 1 and 2, the two programs are simultaneously recorded on the HDD.

  2) A program (content) recorded in the HDD is read, and the read data is reproduced by the MPEG2 decompression unit and simultaneously distributed to iLINK, LAN1, and LAN2.

  The flow of data by the above series of operations is indicated by arrows 1) to 9) in FIG. 3 and arrows 1) to 6) in FIG.

  If the data flow is divided into the following three, 1) to 9) in FIG. 3 and 1) to 6) in FIG. 4 are classified as follows. The following 1) to 9) are data block units that must be processed within the unit time required for real-time processing.

FIG. 3 shows a conventional operation, which will be described below.
・ Data input system: 1), 2)
-HDD input / output: 3) to 5)
・ Data output system: 6) to 9)
1): Data transfer from digital tuner 1 to memory
2): Data transfer from digital tuner 2 to memory
3): Data transfer from memory to HDD (1) is saved)
4): Data transfer from memory to HDD (2) is saved)
5): Data transfer from HDD to memory (playback)
6): Data transfer (distribution) from memory to other devices via iLINK
7): Data transfer from memory to other devices via LAN1 (distribution)
8): Data transfer (distribution) from memory to other devices via LAN2
9): Data transfer from memory to MPEG2 decompression unit (reproduction output)
FIG. 4 shows the operation of the present invention, which will be described below.
・ Data input system: 1), 2)
-HDD input / output: 3) to 5)
・ Data output system: 6)
1) to 5): Same as conventional.
6): Data transfer (distribution) from memory to other devices via iLINK, data transfer (distribution) from memory to other devices via LAN1, data transfer (distribution) from memory to other devices via LAN2, from memory Data transfer to MPEG2 expansion unit (reproduction output)
As a result, it is clear that the data flow by data transfer in the data output system is different in processing between the conventional method and the method of the present invention.

  That is, in the conventional method, the data processing in the data output system is executed 4 times individually as one block transfer, but in the present invention, one block data transfer cycle according to 6) is executed. It is characterized by the fact that it is completed by executing.

  FIGS. 5 and 6 are timing charts showing the data transfer images of FIGS. 3 and 4, respectively. As can be seen from the above, in the case of performing real-time distribution of contents recorded on the HDD to four different media while recording two broadcasts, the conventional (FIGS. 3 and 5) and the present invention (FIG. 4 and FIG. 6) are the same as data input (twice) and HDD input / output (three times), but conventionally four times in a data transfer cycle (data output) from the memory to each device (I / O). The need for a block data transfer cycle indicates that the present invention (FIG. 6) completes in one block data transfer cycle.

  The effective values of the data transfer rate required for the real-time AV processing in the prior art and the present invention when assuming a 24-Mbps (= 3 MBps) high-definition AV stream as the real-time processing stream are shown below.

Conventional operation (FIG. 3): Data transfer rate processed on system bus: 3 MBps / time × 9 times = 27 MBps
Operation of the present invention (FIG. 4): Data transfer rate processed on the system bus: 3 MBps / time × 6 times = 18 MBps
By using the present invention, the data transfer processing capability required for the system bus can be reduced by 9 MBps.

  Further, the bus idle time when the system bus specification is set to the contents shown in FIG. 5 and FIG.

Conventional operation (FIG. 5): Bus idle time per 1 second cycle: 325 msec
Operation of the present invention (FIG. 6): Bus idle time per 1 second cycle: 550 msec
By using the present invention, it is shown that the above specification can be used for processing other than data transfer by 225 msec per 1 second cycle.

  From the above, the advantage of using the present invention was briefly shown.

Details of the present invention will be described below. Prior to the description of the present invention, a conventional DMA controller, memory controller, I / O device controller, system bus request arbitration controller, DMA transfer request arbitration controller, and data transfer image will be described. FIG. 15 is a block diagram showing the internal configuration of a conventional DMA controller (controller). The DMA control unit is composed of the following control blocks.
DMA control register J1-1: FIG. 16 shows register details, which will be described later.
Memory address & transfer size control unit J1-2: Controls the memory address & data transfer size during the DMA data transfer cycle.
DMA transfer cycle control unit & system bus I / F control unit J1-3: Controls the start, execution, and end of the DMA cycle.
Data buffer J1-4: Temporarily saves data read by the DMA cycle. In the DMA write cycle, the data in this buffer is output to the system bus.
I / O address & data transfer size controller J1-5: Controls the I / O (memory) address & data transfer size during the DMA data transfer cycle.
DMA transfer request arbitration control unit J1-6: Controls the DMA transfer order and execution timing in response to a DMA transfer request from an external device.

The DMA control register J1-1 will be described. FIG. 16 shows a register configuration implemented in the DMA channel. These registers are implemented as many as the number of DMA channels implemented.
SAR (transfer source address register): sets the memory address of the data transfer source to be read in the DMA cycle.
DAR (transfer destination address register): Sets the I / O (memory) address of the data transfer destination to be written in the DMA cycle.
TMR (transfer mode register): Sets various data transfer modes of DMA (port size, burst, etc.).
TSR (transfer size register): Sets the block data size for one DMA transfer.
DCR (DMA channel control register): Controls the operation of the DMA channel (DMA start, forced termination, reset, etc.).
DSR (DMA channel status register): Indicates the status of the DMA channel (operation completed, error, operating, etc.).

FIG. 17 is a block diagram of a conventional memory control unit. The memory control unit is composed of the following control blocks.
-Memory unit J2-1
Memory control unit J2-2: Controls access to the memory in accordance with an access request from the system bus. When DRAM is used for the memory, refresh control is also executed.
System bus interface unit J2-3: Recognizes a memory access request on the system bus and issues an access request to the memory access control unit. Performs system bus response control during memory access.
Data buffer J2-4: A high-speed response to the write cycle is realized by functioning as a write buffer during the memory write cycle.

FIG. 18 is a block diagram of a conventional I / O device controller. The I / O device control unit is composed of the following control blocks.
I / O device module J3a-1: Various input / output control devices (IEEE 1394 controller, LAN controller, etc.)
I / O device control unit J3a-2: Controls access to the I / O device in accordance with an access request from the system bus.
System bus interface unit J3a-3: Recognizes an I / O device access request on the system bus and issues an access request to the I / O device access control unit. Performs system bus response control during I / O device access. A DMA transfer request signal is output to the system bus in response to a request from the I / O device control unit. The activation of the DMA cycle is recognized by the DMA transfer approval signal.
Data buffer J3a-4: A high-speed response to the write cycle is realized by functioning as a write buffer during the I / O device write cycle.

FIG. 19 is a block diagram of the I / O device controller when the memory is mounted in FIG. The I / O device control unit is composed of the following control blocks.
I / O device module J3b-1: Various input / output control devices (IEEE 1394 controller, LAN controller, etc.)
I / O device control unit J3b-2: Controls access to I / O devices and memory in accordance with an access request from the system bus. When DRAM is used for the memory, refresh control is also executed.
System bus interface unit J3b-3: Recognizes an I / O device access request on the system bus and issues an access request to the I / O device access control unit. Performs system bus response control during I / O device access. A DMA transfer request signal is output to the system bus in response to a request from the I / O device control unit. The activation of the DMA cycle is recognized by the DMA transfer approval signal.
Data buffer J3b-4: A high-speed response to the write cycle is realized by functioning as a write buffer during the I / O device write cycle.
・ Memory part J3b-5
FIG. 7 is a block diagram of a conventional system bus arbitration control unit. The system bus arbitration control unit includes the following control blocks.
・ Bus arbitration control unit G1-1
DMA transfer request arbitration control unit G1-2: receives a DMA transfer request signal DMAREQ from each I / O device, and asserts a bus request signal BUSREQ0 to the system bus request arbitration control unit. At the same time, the channel for starting the DMA operation is determined by the prescribed priority order determination control method, and the corresponding DMA channel waits for the assertion of DMAG. In response to BUSACK0 from the system bus request arbitration control unit, the corresponding DMAG is asserted to activate the corresponding DMA channel. The DMA controller asserts DMAACK of the corresponding DMA channel when executing the DMA cycle. Here, for simplicity, it is assumed that there are four DMA transfer request signals.
System bus request arbitration control unit G1-3: detects a bus request signal BUSREQ from each bus master. The bus master to which the right to use the bus is given is determined by a prescribed priority order determination control method. Assert BUSACK of the corresponding bus master. Here, for simplicity, it is assumed that there are four system bus request signals.

  The DMA transfer request arbitration control unit is originally implemented in the DMA control unit and operates in cooperation with the DMA control unit. Here, however, the part related to the arbitration control for the bus request is extracted and together with the system bus request arbitration circuit. Indicated.

  8 and 9 are timing charts showing the operation of the arbitration control unit for the conventional system bus and DMA transfer requests. Here, it is assumed that the priority of the arbitration control for a request is higher as the value of “n” added to the BUSREQ (0: n) and BUSACK (0: n) signals is smaller. In this case, since BUSREQ (0) has the highest priority, the priority order of the DMA transfer request is the highest. Further, the arbitration control method is the same among the plurality of DMAREQ (0: n), and DMAREQ (0) is the highest.

First, a control method related to the conventional system bus request arbitration shown in FIG. 8 will be described using a timing chart. Each signal on the timing chart is shown below.
BUSCLK: A synchronous clock for bus control and shown as a bus clock cycle in the figure.
T (1:23): Indicates the bus clock control timing.
BBUSUSY: Signal indicating the system bus drive status BUSREQ [0: 3]: Bus request signal from each bus master [0: 3] BUSACK [0: 3]: Bus usage to each bus master [0: 3] Approval signal A timing chart will be described below.
T1: BUSREQ1 and BUSREQ3 are asserted simultaneously.
T2: Locks the arbitration control circuit after synchronization (in the future, even if there is a higher priority bus request, it will not be affected). BUSACK1 is asserted by a prescribed priority order determination method (here, the lower priority order is higher), and the bus master 1 is permitted to use the bus. BUSREQ0 is asserted (BUSREQ0 is the highest priority bus request but does not change state).
T3: The bus master 1 checks the state of the BUSBUSY signal and confirms that no other bus master is using the bus. The bus master 1 asserts the BUSBUSY signal and negates BUSREQ1 simultaneously with the start of the bus cycle. The arbitration control circuit is unlocked by negating BUSREQ1. BUSREQ2 is asserted.
T4: BUSACK0 is asserted in the second arbitration (at this time, BUSACK1 is negated).
T5: Bus master 0 waits for BUSBUSY to be negated and the bus to be released.
T6: The bus master 1 negates BUSBUSY and releases the bus.
T7: The bus master 0 checks the state of the BUSBUSY signal and confirms that no other bus master is using the bus. The bus master 0 asserts the BUSBUSY signal and negates BUSREQ0 simultaneously with the start of the bus cycle. The arbitration control circuit is unlocked by negating BUSREQ0.
<T23 is reached by the same control below>
The priority determination method and control method are only examples, and various control methods can be selected according to the system specifications.

Next, a control method related to the conventional DMA transfer request arbitration shown in FIG. 9 will be described using a timing chart. Each signal on the timing chart is shown below.
BUSCLK: A synchronous clock for bus control and shown as a bus clock cycle in the figure.
T (1:23): Indicates the bus clock control timing.
BUSBUSY: Signal indicating the system bus drive status DMAREQ [0: 3]: DMA transfer request signal from I / O device [0: 3] DMAG [0: 3]: I / O device [0: 3 DMA transfer approval signal to BUSREQ [0]: Bus request signal from each bus master [0] BUSACK [0]: Bus use approval signal to each bus master [0] A timing chart will be described below.
T1: Assert BUSREQ0 after detecting assertion of DMAREQ1 and DMAREQ3.
T2: Locks the arbitration control circuit after synchronization (in the future, even if there is a higher priority bus request, it will not be affected). BUSACK0 assertion is detected (system bus use right has been approved by the system bus arbitration control unit). DMAG1 is asserted by a prescribed priority order determination method (here, the smaller number is the higher priority), and DMA channel 1 is authorized to start the DMA cycle. DMA channel 1 waits for BUSBUSY to be negated.
T4: DMAREQ0 is asserted (DMAREQ0 is the highest priority DMA request, but the state does not change). BUSBUSY negates (the bus master using the system bus releases the bus).
T5: Bus master 0 (DMA channel 1) checks the state of the BUSBUSY signal and confirms that no other bus master is using the bus. The bus master 0 (DMA channel 1) asserts the BUSBUSY and DMAACK signals and negates DMAREQ1 simultaneously with the start of the bus cycle. The arbitration control circuit is unlocked by negating DMAREQ1. DMAREQ2 is asserted.
T6: DMAG0 is asserted by re-arbitration (DMAG1 is negated at this time).
T7: Bus master 0 (DMA channel 0) waits for BUSBUSY to be negated and the bus to be released.
T8: Bus master 0 (DMA channel 1) negates BUSBUSY and releases the bus.
T9: Bus master 0 (DMA channel 0) checks the state of the BUSBUSY signal and confirms that no other bus master is using the bus. The bus master 0 (DMA channel 0) asserts the BUSBUSY signal and negates DMAREQ0 simultaneously with the start of the bus cycle. The arbitration control circuit is unlocked by the negation of DMAREQ0.
<T23 is reached by the same control below>
By continuously asserting BUSREQ0 while a plurality of DMA transfer requests are asserted to the system bus request arbitration control unit, the system bus arbitration control circuit is locked, and the right to use the bus by the DMA control unit is secured.

  The priority determination method and control method for the DMA transfer request is an example, and various control methods can be selected according to the system specifications. Therefore, the determination method does not matter in the present invention.

The operation of DMA data transfer according to the conventional method using each control unit will be described below with reference to FIGS. First, FIG. 20 and FIG. 21 show data transfer images when a DMA control unit is arranged on the system bus. This data transfer is a DMA transfer from the memory K1-1 to the I / O device K1-4.
(1) In order to execute such an operation, necessary information is set in advance in the register of the DMA control unit K1-3.
-Channel initialization: Channel is initialized by setting to DCR.
SAR setting: Sets the start address of the transfer source memory.
DAR setting: Sets the start address of the transfer destination I / O.
TSR setting: Sets the data transfer size (number of words).
• TMR setting: Sets the data transfer mode.
DMA transfer cycle (transfer source) = burst transfer DMA transfer size (transfer source) = 4 burst port size (transfer source) = 4 byte DMA transfer cycle (transfer destination) = burst transfer DMA transfer size (transfer destination) = 4 Burst port size (transfer destination) = 4-byte memory address increase / decrease = Increment I / O address increase / decrease = Fixed DMA channel activation method = DMAREQ
Interrupt = enable channel start: Channel operation is started by setting to DCR. The TMR setting causes this channel to execute a DMA cycle when it detects DMAREQ assertion. At this timing, since the operation of the I / O device related to the channel operation has not started, the DMA cycle is not started immediately.
(2) Initial setting of the DMA transfer request source I / O device and control unit, initialization of the I / O device, and necessary operations are set.
DMA request enable (3) When various settings are completed, the operation of the I / O device is started at the timing of starting the operation.

The above settings are set by the host CPU via the system bus.
(4) DMAREQ assert: The I / O device requests data transfer.
(5) By the bus arbitration operation described in FIGS. 7 to 9, the corresponding DMA channel acquires the right to use the bus and starts the bus cycle.
(6) A bus cycle is executed at the timing shown in FIG.
T1: The DMA control unit K1-3 asserts BUSBUSY, AS, transfer source memory address & transfer mode information on Add & Com, indicating the start of a burst read cycle to the memory.
T2: The DMA control unit K1-3 negates the AS, and each bus I / F control unit K1-2 decodes the address and recognizes the access request while the AS is asserted. The bus I / F control unit K1-2 detects an access request and requests the memory control unit to read 4 burst data.
T3: The bus I / F control unit K1-2 outputs the first one-word data read from the memory to the data bus of the system bus. The bus I / F control unit K1-2 asserts RDY and outputs a response signal (first time) to the read request.
T4: The DMA control unit K1-3 fetches data into the buffer K1-3a. The bus I / F control unit K1-2 outputs the second one-word data read from the memory to the data bus of the system bus. The bus I / F control unit K1-2 asserts RDY and outputs a response signal (second time) to the read request.
T5: The DMA control unit K1-3 fetches data into the buffer K1-3a.
The bus I / F control unit K1-2 outputs the third 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit K1-2 asserts RDY and outputs a response signal (third time) to the read request.
T6: The DMA control unit K1-3 fetches data into the buffer K1-3a.
The bus I / F control unit K1-2 outputs the fourth 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit K1-2 asserts RDY and outputs a response signal (fourth time) to the read request.
T7: The DMA control unit K1-3 fetches data into the buffer K1-3a.
The bus I / F control unit K1-2 negates RDY. The DMA control unit K1-3 asserts AS, DMAACK, transfer destination I / O address & transfer mode information on Add & Com, and indicates the start of a burst write cycle to the I / O device. The read first word data on the buffer K1-3a is output to the data bus of the system bus.
T8: The DMA control unit K1-3 negates the AS, and each bus I / F control unit K1-2 decodes the address and recognizes the access request while the AS is asserted. The I / O control unit K1-5 detects an access request. The I / O control unit K1-5 asserts RDY and outputs a response signal (first time) to the write request.
T9: The I / O control unit K1-5 takes data into the buffer K1-5a. The read second word data on the buffer K1-3a is output to the data bus of the system bus. The I / O control unit K1-5 asserts RDY and outputs a response signal (second time) to the write request.
T10: The I / O control unit K1-5 takes data into the buffer K1-5a.
The read third word data on the buffer K1-3a is output to the data bus of the system bus. The I / O control unit K1-5 asserts RDY and outputs a response signal (third time) to the write request.
T11: The I / O control unit K1-5 takes data into the buffer K1-5a.
The read fourth word data on the buffer K1-3a is output to the data bus of the system bus. The I / O control unit K1-5 asserts RDY and outputs a response signal (fourth time) to the write request.
T12: The I / O control unit K1-5 takes data into the buffer K1-5a.
The I / O control unit K1-5 negates RDY. The buffer K1-3 negates BUSBUSY, DMAACK, Add & Com, and write data, and releases the bus.
(7) When the data transfer of the size set in the TSR is completed by repeating the operations (4) to (6), the DMA control unit asserts an interrupt to the host CPU to notify the completion of the DMA data transfer.

Next, FIG. 22 and FIG. 23 are data transfer images when the DMA control unit is arranged on the memory control unit. This data transfer is a DMA transfer from the memory K2-1 to the I / O device K2-3.
(1) In order to execute such an operation, necessary information is set in advance in the register of the DMA control unit K2-2a. This is the same as setting (1) in FIGS.
(2) Initial setting of the I / O device and control unit of the DMA transfer request source. This is the same as setting (2) in FIGS.
(3) When various settings are completed, the operation of the I / O device is started at the timing of starting the operation.

The above settings are set by the host CPU via the system bus.
(4) Assert DMAREQ, and the I / O device requests data transfer.
(5) The corresponding DMA channel acquires the right to use the bus by the bus arbitration operation described in FIGS. 7 to 9, and starts the bus cycle.
(6) A bus cycle is executed at the timing shown in FIG.

Here, the timing when the processing of the I / O device-side control unit is low speed and RDY cannot be responded with 0 wait in write access to the I / O device is shown as 1 wait processing. The processing procedure is shown below.
T1: The memory control unit K2-2 asserts BUSBUSY, DMAACK, AS, transfer destination I / O address & transfer mode information on Add & Com, and indicates the start of a burst write cycle to the I / O device. The first word data read from the memory on the buffer K2-2b is output to the data bus of the system bus.
T2: The memory control unit K2-2 negates AS, and each bus I / F control unit decodes an address and recognizes an access request while AS is asserted.
The bus I / F control unit K2-4 detects an access request.
T3: The bus I / F control unit K2-4 asserts RDY and outputs a response signal (first time) to the write request.
T4: The bus I / F control unit K2-4 takes in data. The bus I / F control unit K2-4 negates RDY. The second one-word data read from the memory on the buffer K2-2b is output to the data bus of the system bus.
T5: The bus I / F control unit K2-4 asserts RDY and outputs a response signal (second time) to the write request.
T6: The bus I / F control unit K2-4 takes in data.
The bus I / F control unit K2-4 negates RDY.
The third 1-word data read from the memory on the buffer K2-2b is output to the data bus of the system bus.
T7: The bus I / F control unit K2-4 asserts RDY and outputs a response signal (third time) to the write request.
T8: The bus I / F control unit K2-4 takes in data. The bus I / F control unit K2-4 negates RDY. The fourth 1-word data read from the memory on the buffer K2-2b is output to the data bus of the system bus.
T9: The bus I / F control unit K2-4 asserts RDY and outputs a response signal (fourth time) to the write request.
T10: The bus I / F control unit K2-4 takes in data.
The bus I / F control unit K2-4 negates RDY. The memory control unit K2-2 negates BUSBUSY, DMAACK, Add & Com, and write data and releases the bus.
(7) When the data transfer of the size set in the TSR is completed by repeating the operations (4) to (6), the DMA control unit asserts an interrupt to the host CPU to notify the completion of the DMA data transfer.

  Here, since the DMA control unit is arranged on the memory control unit, the DMA burst operation is performed in the same manner as in FIG. 20 and FIG. 21 as the DMA operation, but the read cycle for this memory is not on the system bus. It does not appear.

  By arranging the DMA in this way, it is possible to reduce the use of the system bus and suppress the operation rate of the system bus.

Next, FIGS. 24 and 25 show data transfer images when the response to access is set to 0 wait by providing the write buffer K3-4a for the I / O burst write transfer in FIGS. This data transfer is a DMA transfer from the memory K2-1 to the I / O device K2-3.
(1) to (5) and (7) are the same as FIG. 22 and FIG.
(6) A bus cycle is executed at the timing shown in FIG.
T1: The memory control unit K3-2 asserts BUSBUSY, DMAACK, AS, transfer destination I / O address & transfer mode information on Add & Com, indicating the start of a burst write cycle to the I / O device. The first word data read from the memory on the buffer K3-2b is output to the data bus of the system bus.
T2: The memory control unit K3-2 negates AS, and each bus I / F control unit decodes an address and recognizes an access request while AS is asserted. The bus I / F control unit K3-4 detects an access request. The bus I / F control unit K3-4 asserts RDY and outputs a response signal (first time) to the write request.
T3: The buffer K3-4a takes in data. The second one-word data read from the memory on the buffer K3-2b is output to the data bus of the system bus. The bus I / F control unit K3-4 asserts RDY and outputs a response signal (second time) to the write request.
T4: The buffer K3-4a takes in data. The third 1-word data read from the memory on the buffer K3-2b is output to the data bus of the system bus. The bus I / F control unit K3-4 asserts RDY and outputs a response signal (third time) to the write request.
T5: The buffer K3-4a takes in data. The fourth 1-word data read from the memory on the buffer K3-2b is output to the data bus of the system bus. The bus I / F control unit K3-4 asserts RDY and outputs a response signal (fourth time) to the write request.
T6: The buffer K3-4a takes in data. The bus I / F control unit K3-4 negates RDY. The memory control unit K3-2 negates BUSBUSY, DMAACK, Add & Com, and write data and releases the bus.

  Thus, by improving the responsiveness by the write buffer, it is possible to reduce the usage time of the system bus and suppress the operation rate of the system bus.

Finally, FIGS. 26 and 27 show data transfer images when the DMA control unit is arranged in the I / O device control unit. This data transfer is a DMA transfer from the memory K4-1 to the I / O device K4-3.
(1) In order to execute such an operation, necessary information is set in advance in the register of the DMA control unit K4-4a. This is the same as setting (1) in FIGS.
(2) Initial setting of the I / O device and control unit of the DMA transfer request source. This is the same as setting (2) in FIGS.
(3) When various settings are completed, the operation of the I / O device is started at the timing of starting the operation.

The above settings are set by the host CPU via the system bus.
(4) DMAREQ assert: The I / O device requests data transfer.
(5) The corresponding DMA channel acquires the right to use the bus by the bus arbitration operation described in FIGS. 7 to 9, and starts the bus cycle.
(6) A bus cycle is executed at the timing shown in FIG.

Here, in the case of a low-speed memory in the read access to the memory, the response is slow and RDY cannot be responded with 0 wait, so the timing in the case of 1 wait processing is shown. The processing procedure is shown below.
T1: The bus I / F control unit K4-4 asserts BUSBUSY, AS, transfer source memory address & transfer mode information on Add & Com, and indicates the start of a burst read cycle to the memory.
T2: The bus I / F control unit K4-4 negates AS, and each bus I / F control unit decodes an address and recognizes an access request while AS is asserted. The bus I / F control unit K4-2 detects an access request and requests the memory control unit to read 4 burst data.
T4: The bus I / F control unit K4-2 outputs the first one-word data read from the memory to the data bus of the system bus. The bus I / F control unit K4-2 asserts RDY and outputs a response signal (first time) to the read request.
T5: The bus I / F control unit K4-4 takes data into the buffer K4-4b.
The bus I / F control unit K4-2 negates RDY.
T6: The bus I / F control unit K4-2 outputs the second 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit K4-2 asserts RDY and outputs a response signal (second time) to the read request.
T7: The bus I / F control unit K4-4 takes data into the buffer K4-4b.
The bus I / F control unit K4-2 negates RDY.
T8: The bus I / F control unit K4-2 outputs the third 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit K4-2 asserts RDY and outputs a response signal (third time) to the read request.
T9: The bus I / F control unit K4-4 takes data into the buffer K4-4b.
The bus I / F control unit K4-2 negates RDY.
T10: The bus I / F control unit K4-2 outputs the fourth 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit K4-2 asserts RDY and outputs a response signal (fourth time) to the read request.
T11: The bus I / F control unit K4-4 fetches data into the buffer K4-4b.
The bus I / F control unit K4-2 negates RDY and releases the data bus.
The bus I / F control unit K4-4 negates BUSBUSY, Add & Com, and releases the bus.
(7) When the data transfer of the size set in the TSR is completed by repeating the operations (4) to (6), the DMA control unit asserts an interrupt to the host CPU to notify the completion of the DMA data transfer.

  Here, since the DMA control unit is arranged on the I / O device control unit, as the DMA operation, an I / O burst write cycle operation is performed in the same manner as in FIGS. The write cycle does not appear on the system bus. By arranging the DMA in this way, it is possible to reduce the use of the system bus and suppress the operation rate of the system bus.

  In the above conventional K1-1x to -4x, the DMA transfer operation using the DMAREQ signal has been described. However, the host CPU recognizes the state of the I / O device and activates the data block of the required size to activate the DMA channel. It is also possible to start DMA transfer directly regardless of the DMAREQ method.

Next, examples of the present invention will be described. First, a DMA controller, a memory controller, an I / O device controller, an arbitration controller corresponding to broadcast transfer, and a data transfer image according to the present invention will be described. FIG. 28 is a block diagram showing the internal configuration of a DMA control unit for broadcast transfer (hereinafter abbreviated as “broad transfer”) of the present invention. The broadcast-compatible DMA control unit (hereinafter abbreviated as “broad control unit”) is composed of the following control blocks.
Broadcast transfer control register L1-1: FIG. 32 shows register details.
Memory address & data transfer size control unit L1-2: Controls the memory address & data transfer size during the broadcast data transfer cycle.
Broad transfer cycle & system bus I / F control unit L1-3: Controls the start, execution and end of the broad transfer cycle.
Data buffer L1-4: temporarily stores data read by the broad transfer cycle. In the broad transfer write cycle, the data in this buffer is output to the system bus.
I / O address & data transfer size control unit L1-5: Controls the I / O (memory) address & data transfer size during the broad transfer cycle.
Broad transfer request arbitration control unit L1-6: Controls the order and execution timing of broad transfer in response to a broad transfer request from an external device.
Broadcast arbitration control register L1-7: FIG. 33 shows a register configuration.

FIG. 32 shows a register configuration implemented in the broad transfer channel. These registers are implemented for the number of implemented channels.
Transfer source address register SAR: Sets the memory address of the data transfer source in the broad transfer cycle.
Transfer destination address register DAR [0: n]: Sets the I / O (memory) address of the data transfer destination in the first broad transfer cycle after the channel operation starts.

  In items 15 and 16, the value of DAR [0: n] is output onto the system bus in the step before starting the data transfer of the broad transfer cycle to a plurality of transfer destinations. In the second and subsequent broad transfer cycles, the transfer destination address is updated depending on the transfer mode (sequential increase or the like).

  Item 15: Transfer destination address information is output to the data bus in the first broad transfer cycle (see FIG. 47 for details).

  Item 16: Transfer destination address information is output to the address bus in the first broad transfer cycle (see FIG. 46 for details).

When the same DAR is mounted at the transfer destination and is set in advance by the host CPU or the like, it is not necessary to mount DAR [0: n].
Transfer mode register TMR: Sets various data transfer modes of broad transfer (port size, burst, burst size, etc.).

  In items 13 and 14, the TMR burst size value is output on the system bus in the step before starting the data transfer in the broad transfer cycle to a plurality of transfer destinations.

  Item 13: A broad transfer size per one time is output to the data bus in a broad transfer cycle (refer to FIG. 46 for details).

  Item 14: The broad transfer size per time is output to the command bus in a broad transfer cycle (see FIG. 47 for details).

A register for setting a similar burst size value is mounted at the transfer destination, and if it is set in advance by the host CPU or the like, the functions of items 13 and 14 need not be mounted.
Transfer size register TSR: Sets the data transfer size.
Channel control register CCR: Controls the operation of the broad transfer channel (channel start, forced end, reset, etc.).
Channel status register CSR: Indicates the status of the broad transfer channel (operation complete, error, operating, etc.).

FIG. 33 shows a register configuration for broadcast arbitration control. These registers are implemented for the number of implemented channels.
Broadcast arbitration control register RER: Controls the broadcast arbitration control unit.

FIG. 35 shows register details. FIG. 35 shows the detailed bit structure of FIG.
EN: Controls the broadcast arbitration control unit (achieving item 11).

EN = 0: Disable EN = 1: Enable • RR [0: 7] BROARDREQ (n) Controls a request by input (achieving item 10).

BR (n) = 0: Disable request BR (n) = 1: Enable request Arbitration is performed only by the BLOADREQ signal in which the BR (n) bit is set to “1”.

  When the BR (n) bit is “0”, the BOARDREQ (n) signal input is always the same as when the Low level is input.

  See BROARDREQ (2) in the timing chart of FIG.

FIG. 29 shows a control circuit example of the broadcast transfer request signal BLOADREQ (n) by setting the bit in the broadcast arbitration control register. (Explanation of items 10 and 11)
When EN = 0, B-REQ (n) is “1” regardless of the state of BLOADREQ (n) and BR (n), and the transfer request is negated.
When EN = 1, if BR (n) = 0, B-REQ (n) is “0” regardless of the state of BLOADREQ (n), and the transfer request is always asserted.
When EN = 1 & BR (n) = 1, the state of BLOADREQ (n) is reflected in B-REQ (n).

Arbitration control will be described. FIG. 10 shows a block diagram of the system bus arbitration control unit of the present invention. It consists of the following control blocks.
・ Bus arbitration control unit H1-1
DMA transfer request arbitration control unit H1-2: As in the conventional case of FIG. 8, in response to a DMA transfer request signal DMAREQ from each I / O device, the bus request signal BUSREQ1 is asserted to the system bus request arbitration control unit To do. At the same time, the channel for starting the DMA operation is determined by the prescribed priority order determining control method, and the corresponding DMA channel is prepared for starting. In response to BUSACK1 from the system bus request arbitration control unit, the corresponding DMA channel is activated. When a DMA cycle is executed, DMAACK of the corresponding DMA channel is asserted. Here, for simplicity, it is assumed that there are four DMA transfer request signals.
System bus request arbitration control unit H1-3: As in the conventional case of FIG. 9, the bus request signal BUSREQ from each bus master is detected. The bus master to which the right to use the bus is given is determined by a prescribed priority order determination control method. Assert BUSACK of the corresponding bus master. Here, for simplicity, it is assumed that there are four system bus request signals.
Broadcast transfer request arbitration control unit H1-4 (Sections 7, 8, 9): Upon receiving a broad transfer request signal BROADREQ from each I / O device, the system bus request arbitration control unit The bus request signal BUSREQ0 is asserted (see FIG. 11, FIG. 12: Item 7; FIG. 13: Item 8; FIG. 14: Item 9). At the same time, the channel for starting the broad transfer operation is determined by a prescribed priority order determination control method, and the corresponding channel waits for the assertion of BROADG. In response to BUSACK0 from the system bus request arbitration control unit, the corresponding channel is asserted in order to activate the corresponding channel. The DMA controller asserts BROADACK of the corresponding channel when executing the broad transfer cycle. Here, for simplicity, it is assumed that there are four broad transfer request signals.

  The broadcast transfer request arbitration control unit is originally installed in the broad transfer control unit and operates in cooperation with the broad transfer control unit. Here, a part related to arbitration control for bus requests is extracted and a system bus request arbitration circuit is extracted. With Since the control units H1-2 and H1-3 in FIG. 10 are the same as the operation of the arbitration control unit for the conventional system bus and DMA transfer request, description thereof will be omitted here (conventional operation, FIG. 7 to FIG. 9). reference).

Next, a control method related to the broad transfer request arbitration of the present invention in FIG. 10 will be described using the timing charts in FIGS. 11 to 14 (Items 7, 8, and 9). Each signal on the timing chart is shown below.
BUSCLK: A synchronous clock for bus control and shown as a bus clock cycle in the figure.
T (1:23): Indicates the bus clock control timing.
BUSBUSY: Signal indicating the system bus drive status DMAREQ [0: 3]: DMA transfer request signal from I / O device [0: 3] DMAG [0: 3]: I / O device [0: 3 DMA transfer approval signal to BUSREQ [0: 3]: Bus request signal from each bus master [0: 3] BUSACK [0: 3]: Bus use approval signal to each bus master [0: 3] [0: 3]: Broad transfer request signal from I / O device [0: 3] • BROADG [0: 3]: Broad transfer approval signal to I / O device [0: 3] • BROADACK [0: 3 ]: Signal indicating a broad transfer cycle to the I / O device [0: 3] EN and BR (0: 3) of the broadcast arbitration control register shown in FIGS. 33 and 35 are all enabled. It is assumed that it is set. In FIG. 35, bit 0 to bit 7 are shown with respect to BR setting. However, as shown in the description of FIGS. 10 to 13, the number of broad transfer request signals is four (BROADREQ). [0: n]), the setting of BR (0: 3) is effective.

First, the timing chart of FIG. 11 will be described (Section 7).
T1: BROADREQ3 is asserted
T2: BROADREQ0 is asserted.
T3: BROADREQ2 is asserted.
T8: When BLOADREQ1 is asserted, the broad transfer request arbitration control unit detects that all four broad transfer requests are asserted. Assert BUSREQ0.
T9: The system bus request arbitration control unit asserts BUSACK0. The BUSACK assertion timing is not necessarily this timing. In response to this, the broad transfer request arbitration control unit asserts BROADG [0: 3].
T10: After confirming that the system bus is open, the broad transfer control unit & bus I / F control unit asserts BUSBUSY and starts a memory burst read cycle.
T14: After completing the memory burst read cycle, assert BROADACK [0: 3] to start the broadcast write cycle for multiple I / O devices.
T15: BROADREQ [0: 3] is negated and BUSREQ0 is negated.
T16: The system bus request arbitration control unit negates BUSACK0, and in response, negates BROADG [0: 3].
T18: After the completion of the broadcast write cycle, BUSBUSY and BLOADACK [0: 3] are negated to release the bus.

  Next, the timing chart of FIG. 12 will be described (Section 7). The difference between FIG. 12 and FIG. 11 shows the arbitration control procedure in a state where BROADREQ2 is always fixed at the Low level. This indicates that there is no device connected to BROADREQ2 or an unused state, and the BLOADACK2 signal is asserted, but the device is not implemented and does not respond. By setting BR (2) = 0 in RER, the same state can be obtained in the control unit. However, since BROADACK2 is asserted, care must be taken not to respond when there is a device to be connected. In FIG. 11, all operations are performed at the same timing except that BROADREQ2 is asserted at T2 and BROADREQ2 is negated at T15.

Next, the timing chart of FIG. 13 will be described (Section 8).
-When T1: BROADREQ3 is asserted, the broad transfer request arbitration control unit detects that the broad transfer request is asserted. Assert BUSREQ0.
T2: BROADREQ0 is asserted. The system bus request arbitration control unit asserts BUSACK0. The BUSACK assertion timing is not necessarily this timing.
T3: BROADREQ2 is asserted. After confirming that the system bus is open, the broad transfer control unit & bus I / F control unit asserts BUSBUSY and starts a memory burst read cycle.
T7: After completing the memory burst read cycle, negate BUSBUSY and release the bus.
T12: BROADREQ1 is asserted.
T13: The broad transfer request arbitration control unit detects that all four broad transfer requests are asserted. Assert BROADG [0: 3].
T14: The broad transfer control unit & bus I / F control unit confirms that the system bus is open, then asserts BUSBUSY and BLOADACK [0: 3], and sends the broadcast write cycle to multiple I / O devices. Start against.
T15: BROADREQ [0: 3] is negated and BUSREQ0 is negated.
T16: The system bus request arbitration control unit negates BUSACK0, and in response, negates BROADG [0: 3].
T18: After the completion of the broadcast write cycle, BUSBUSY and BLOADACK [0: 3] are negated to release the bus.

  Here, by detecting the first broad request, the burst read cycle from the memory is started, which has the effect of shortening the response time to the broad transfer request.

Finally, the timing chart of FIG. 14 will be described (Section 9).
-When T1: BROADREQ3 is asserted, the broad transfer request arbitration control unit detects that the broad transfer request is asserted. Assert BUSREQ0.
T2: BROADREQ0 is asserted. The system bus request arbitration control unit asserts BUSACK0. The BUSACK assertion timing is not necessarily this timing.
T3: BROADREQ2 is asserted. After confirming that the system bus is open, the broad transfer control unit & bus I / F control unit asserts BUSBUSY and starts a memory burst read cycle. Once BUSREQ0 is negated.
T4: The system bus request arbitration control unit negates BUSACK0.
T7: After completing the memory burst read cycle, negate BUSBUSY and release the bus.
T12: When BLOADREQ1 is asserted, the broad transfer request arbitration control unit detects that all four broad transfer requests are asserted. Assert BUSREQ0 again.
T13: The system bus request arbitration control unit asserts BUSACK0. The BUSACK assertion timing is not necessarily this timing. In response to this, the broad transfer request arbitration control unit asserts BROADG [0: 3].
T14: The broad transfer control unit & bus I / F control unit confirms that the system bus is open, then asserts BUSBUSY and BLOADACK [0: 3], and sends the broadcast write cycle to multiple I / O devices. Start against.
T15: BROADREQ [0: 3] is negated and BUSREQ0 is negated.
T16: The system bus request arbitration control unit negates BUSACK0, and in response, negates BROADG [0: 3].
T18: After the completion of the broadcast write cycle, BUSBUSY and BLOADACK [0: 3] are negated to release the bus. In FIG. 13, the burst read cycle from the memory is started by detecting the first broad request, which has the effect of shortening the response time to the broad transfer request. However, since BUSREQ0 was continuously asserted, another buster could not use the bus until all four broad requests were met.

  The priority determination method and control method for the broad transfer request according to the present invention is only an example, and various control methods can be selected according to the system specifications. Therefore, the determination method does not matter in the present invention. .

The I / O control unit of the present invention will be described. FIG. 30 shows a block diagram of the I / O device controller of the present invention. The I / O device control unit is composed of the following control blocks.
I / O device module L2-1: Various input / output control devices (IEEE 1394 controller, LAN controller, etc.)
I / O device control unit & memory control unit L2-2: Controls access to I / O devices and memory in accordance with an access request from the system bus.
System bus interface unit L2-3: Recognizes an I / O device access request on the system bus and issues an access request to the I / O device access control unit. Performs system bus response control during I / O device access. A broad transfer request signal is output to the system bus in response to a request from the I / O device control unit. The start of the broad transfer cycle is recognized by the broad transfer approval signal.
Data buffer L2-4 (item 5): A high-speed response to the write cycle is realized by functioning as a write buffer during the I / O device write cycle.
Memory unit L2-5: Data storage memory Transfer destination address & transfer size control unit L2-6: Controls the transfer destination memory address and data transfer size in the broadcast transfer cycle. Recognizes the end of the data transfer cycle.
Broadcast transfer control register L2-7 (terms 1, 13, 14, 15, 16)
BMR: Broadcast mode register: Increases or decreases the transfer destination address.
DAR: Transfer destination address register: Holds the memory address of the data transfer destination during broad write transfer (reception).
TSR: Transfer size register: Holds the data transfer size during broad write transfer (reception). Two registers are set by the host CPU or a similar controller. In particular, TSR need not be implemented when the data transfer size is fixed as a system specification.
(Items 15 and 16): Control is performed so that the corresponding address information output at the timing shown in FIGS. 46 and 47 is taken into the DAR. In this case, the host CPU does not need to make settings for the register.
(Items 13 and 14): Control is performed so that the corresponding size information output at the timing shown in FIGS. 46 and 47 is taken into the TSR. In this case, the host CPU does not need to make settings for the register.

The memory control unit of the present invention will be described. FIG. 31 shows a block diagram of the memory control unit of the present invention. The memory control unit is composed of the following control blocks.
-Memory unit L3-1
Memory control unit L3-2: performs access control to the memory in accordance with an access request from the system bus. When DRAM is used for the memory, refresh control is also performed.
System bus interface unit L3-3 (Section 3): Recognizes a memory access request on the system bus and issues an access request to the memory access control unit. Performs system bus response control during memory access.
(Section 3): In the case of a burst data transfer request, there is a high possibility of receiving an access request again for the subsequent continuous data. Therefore, instead of executing the memory read access after the request, the first burst read access After completion, read access to the memory is continued, and the read data is stored in a dedicated data buffer to speed up access to burst transfer requests.
Data buffer L3-4 (terms 2, 3, 4): A high-speed response to the write cycle is realized by functioning as a write buffer during the memory write cycle.

  Terms 2, 3, and 4 will be described. Arbitrates the timing of read access to the memory and the timing of data output to the system bus (section 2). Stores prefetched data of item 3. By providing two buffers shown in item 4, a high-speed response to a burst read request becomes possible.

The broadcast transfer of the present invention will be described. The operation of broadcast data transfer using each control unit of the present invention will be described below with reference to FIGS. Data transfer access by the broadcast transfer control unit will be described. First, FIG. 36 and FIG. 37 show data transfer images when a broadcast transfer control unit is arranged on the system bus. This data transfer is a broad transfer from the memory M-1 to the I / O devices M-3 and M-5.
(1) In order to execute such an operation, necessary information is previously set in the registers of the control units M-8 and M-9 by the host CPU.
<Broadcast request control register: L1-1>
-Setting of RER: EN = 1: The broadcast control unit is enabled.
BR [0: 3] = “1111”: BROADREQ [0: 3] is enabled.
<Broadcast transfer control register: L1-3>
-Channel initialization: Channel is initialized by setting to DCR.
SAR setting: Sets the start address of the transfer source memory.
-Setting of DAR [0: 3]: Not set: Items 15 and 16 are set only at the time of mounting.
TSR setting: Sets the data transfer size (number of words).
• TMR setting: Sets the data transfer mode.
Transfer mode = broadcast (section 1)
Transfer cycle (transfer source) = burst transfer transfer size (transfer source) = 4 burst port size (transfer source) = 4 byte transfer cycle (transfer destination) = burst transfer transfer size (transfer destination) = 4 bursts (Section 13) 14)
Port size (transfer destination) = 4-byte memory address increase / decrease = Increment I / O address increase / decrease = Fixed channel activation method = BROADREQ
Interrupt = enable channel start: Channel operation is started by setting to DCR. When the TMR setting detects that BROADREQ is asserted, this channel executes a broad transfer cycle. At this timing, since the operation of the I / O device related to the channel operation has not started, the broad transfer cycle is not started immediately.
(2) Initial setting of data transfer request source I / O device and control unit <broad transfer related I / O device control register: L2-9>
-BMR setting: Address fixed-DAR setting: Set the port address of the transfer destination I / O.
Setting of TSR: The same value as the TMR transfer size (transfer destination) of the broad transfer control unit L1-3 is set.
<I / O device settings>
-Initialization of I / O devices-Set necessary operations.
DMA transfer request enable: Requests DMA data transfer as an I / O device.
(3) When various settings are completed, the operation of the I / O device is started at the timing of starting the operation.

The above settings are set by the host CPU via the system bus.
(4) BROADREQ asserted: I / O device requests data transfer.
(5) The corresponding broad transfer control unit acquires the right to use the bus by the bus arbitration operation described with reference to FIGS. 7 to 11, and starts the bus cycle.
(6) A bus cycle is executed at the timing shown in FIG.
T1: DMA controller M-8 asserts BUSBUSY, AS, transfer source memory address & transfer mode information on Add & Com: indicates burst read cycle start to memory T2: DMA controller M-8 negates AS : While the AS is asserted, each bus I / F control unit decodes the address and recognizes the access request. The bus I / F control unit M-2 detects an access request and requests the memory control unit to read 4 burst data.
T3: The bus I / F control unit M-2 outputs the first one-word data read from the memory to the data bus of the system bus. The bus I / F control unit M-2 asserts RDY and outputs a response signal (first time) to the read request.
T4: The DMA control unit M-8 takes data into the buffer M-8a. The bus I / F control unit M-2 outputs the second one-word data read from the memory to the data bus of the system bus. The bus I / F control unit M-2 asserts RDY and outputs a response signal (second time) to the read request.
T5: The DMA control unit M-8 takes data into the buffer M-8a. The bus I / F control unit M-2 outputs the third 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit M-2 asserts RDY and outputs a response signal (third time) to the read request.
T6: The DMA control unit M-8 takes data into the buffer M-8a. The bus I / F control unit M-2 outputs the fourth 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit M-2 asserts RDY and outputs a response signal (fourth time) to the read request.
T7: The DMA control unit M-8 takes data into the buffer M-8a. The bus I / F control unit M-2 negates RDY, the DMA control unit M-8 asserts AS, BLOADACK [0: 3], transfer destination I / O address & transfer mode information on Add & Com, Indicates the start of a broadcast burst write cycle to the I / O device. The read first word data on the buffer M-8a is output to the data bus of the system bus.
T8: The DMA control unit M-8 negates the AS, and each bus I / F control unit decodes the address and recognizes the access request while the AS is asserted. The bus I / F control units M-4 and M-6 detect the access request. The bus I / F controllers M-4 and M-6 assert RDY and output a response signal (first time) to the write request. (Note: described later)
T9: The bus I / F control units M-4 and M-6 fetch data into the buffers M-4a and M-6a. The read second word data on the buffer M-8a is output to the data bus of the system bus. The bus I / F controllers M-4 and M-6 assert RDY and output a response signal (second time) to the write request. (Note: described later)
T10: The bus I / F control units M-4 and M-6 fetch data into the buffers M-4a and M-6a. The read third word data on the buffer M-8a is output to the data bus of the system bus. The bus I / F controllers M-4 and M-6 assert RDY and output a response signal (third time) to the write request. (Note: described later)
T11: The bus I / F control units M-4 and M-6 fetch data into the buffers M-4a and M-6a. The read fourth word data on the buffer M-8a is output to the data bus of the system bus. The bus I / F controllers M-4 and M-6 assert RDY and output a response signal (fourth time) in response to the write request. (Note: described later)
T12: The bus I / F control units M-4 and M-6 fetch data into the buffers M-4a and M-6a. The bus I / F control units M-4 and M-6 negate RDY. The DMA control unit M-8 negates BUSBUSY, BLOADACK [0: 3], Add & Com, and write data and releases the bus.
(7) When the data transfer of the size set in the TSR of the broad transfer control unit is completed by repeating the above operations (4) to (6), the broad transfer control unit asserts an interrupt to the host CPU and performs DMA data transfer. Signal completion.
(Note) Since the bus I / Fs of a plurality of I / O control units simultaneously assert RDY, collision of RDY signals is avoided by wired OR connection. The RDY signal becomes Low only when all RDY becomes Low by the wired OR connection. This can be adjusted to the response of the slowest device when there is a slow response device. (Claim 6)
Next, data transfer access 2 by the broadcast transfer control unit will be described. 38 and 39 show data transfer images when a broadcast transfer control unit is arranged on the control unit of the I / O device 1. This data transfer is a broad transfer from the memory P1-1 to the I / O devices P1-3 and P1-5. (1) to (5) and (7) are the same as FIG. 36 and FIG.
(6) A bus cycle is executed at the timing shown in FIG.
T1: BROAD-C (P1-4d) asserts BUSBUSY, AS, transfer source memory address & transfer mode information on Add & Com, indicating the start of a burst read cycle to the memory.
T2: BROAD-C (P1-4d) negates AS, and each bus I / F control unit decodes the address and recognizes the access request while AS is asserted. The bus I / F control unit P1-2 detects an access request and requests the memory control unit to read 4 burst data.
T3: The bus I / F control unit P1-2 outputs the first one-word data read from the memory to the data bus of the system bus. The bus I / F control unit P1-2 asserts RDY and outputs a response signal (first time) to the read request.
T4: BROAD-C (P1-4d) fetches data into the buffer P1-4b. The bus I / F control unit P1-2 outputs the second 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit P1-2 asserts RDY and outputs a response signal (second time) to the read request.
T5: BROAD-C (P1-4d) takes data into the buffer P1-4b. The bus I / F control unit P1-2 outputs the third 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit P1-2 asserts RDY and outputs a response signal (third time) to the read request.
T6: BROAD-C (P1-4d) takes data into the buffer P1-4b. The bus I / F control unit P1-2 outputs the fourth 1-word data read from the memory to the data bus of the system bus. The bus I / F control unit P1-2 asserts RDY and outputs a response signal (fourth time) to the read request.
T7: BROAD-C (P1-4d) takes data into the buffer P1-4b. The bus I / F control unit P1-2 negates RDY, BROAD-C (P1-4d) asserts AS, BROADACK [0: 3], transfer destination I / O address & transfer mode information on Add & Com, Fig. 4 illustrates the start of a broadcast burst write cycle to multiple I / O devices. The read first word data on the buffer P1-4b is output to the data bus of the system bus.
T8: BROAD-C (P1-4d) negates AS, and each bus I / F control unit decodes an address and recognizes an access request while AS is asserted. The bus I / F controllers P1-4 and P1-6 detect access requests. The bus I / F controllers P1-4 and P1-6 assert RDY and output a response signal (first time) to the write request. (Note: described later)
T9: The bus I / F controllers P1-4 and P1-6 fetch data into the buffers P1-4a and P1-6a. The read second word data on the buffer P1-4b is output to the data bus of the system bus. The bus I / F controllers P1-4 and P1-6 assert RDY and output a response signal (second time) to the write request. (Note: described later)
T10: The bus I / F control units P1-4 and P1-6 fetch data into the buffers P1-4a and P1-6a. The read third word data on the buffer P1-4b is output to the data bus of the system bus. The bus I / F controllers P1-4 and P1-6 assert RDY and output a response signal (third time) to the write request. (Note: described later)
T11: The bus I / F control units P1-4 and P1-6 fetch data into the buffers P1-4a and P1-6a. The read fourth word data on the buffer P1-4b is output to the data bus of the system bus. The bus I / F controllers P1-4 and P1-6 assert RDY and output a response signal (fourth time) to the write request. (Note: described later)
T12: The bus I / F control units P1-4 and P1-6 fetch data into the buffers P1-4a and P1-6a. The bus I / F controllers P1-4 and P1-6 negate RDY. BROAD-C (P1-4d) negates BUSBUSY, BLOADACK [0: 3], Add & Com, and write data and releases the bus.
(Note) Since the bus I / Fs of a plurality of I / O control units simultaneously assert RDY, collision of RDY signals is avoided by wired OR connection. The RDY signal becomes Low only when all RDY becomes Low by the wired OR connection. This can be matched to the response of the slowest device when there is a slow response device. (Claim 6)
Next, data transfer access 3 by the broadcast transfer control unit will be described. 40 and 41 show data transfer images when the broadcast transfer control unit is arranged on the memory control unit (item 17). This data transfer is a broad transfer from the memory N1-1 to the I / O devices N1-3 and N1-5. (1) to (5) and (7) are the same as FIG. 36 and FIG.
(6) A bus cycle is executed at the timing shown in FIG.
T1: The bus I / F control unit N1-2 asserts BUSBUSY, BROADACK, AS, transfer destination I / O address & transfer mode information on Add & Com, and indicates the start of a broadcast burst write cycle to the I / O device.
The first word data read from the memory on the buffer N1-2b is output to the data bus of the system bus.
T2: The bus I / F control unit N1-2 negates AS, and each bus I / F control unit decodes an address and recognizes an access request while AS is asserted. The bus I / F controllers N1-4 and N1-6 detect access requests. The bus I / F controllers N1-4 and N1-6 assert RDY and output a response signal (first time) to the write request. (Note: described later)
T3: The buffers N1-4a and N1-6a take in data. The second one-word data read from the memory on the buffer N1-2b is output to the data bus of the system bus. The bus I / F controllers N1-4 and N1-6 assert RDY and output a response signal (second time) to the write request. (Note: described later)
T4: The buffers N1-4a and N1-6a take in data. The third 1-word data read from the memory on the buffer N1-2b is output to the data bus of the system bus. The bus I / F controllers N1-4 and N1-6 assert RDY and output a response signal (third time) in response to the write request. (Note: described later)
T5: The buffers N1-4a and N1-6a take in data. The fourth 1-word data read from the memory on the buffer N1-2b is output to the data bus of the system bus. The bus I / F controllers N1-4 and N1-6 assert RDY and output a response signal (fourth time) in response to the write request. (Note: described later)
T6: The buffers N1-4a and N1-6a take in data. The bus I / F controllers N1-4 and N1-6 negate RDY. The bus I / F control unit N1-2 negates BUSBUSY, BLOADACK, Add & Com, and write data, and releases the bus.

(Note) Since the bus I / Fs of a plurality of I / O control units simultaneously assert RDY, collision of RDY signals is avoided by wired OR connection. The RDY signal becomes Low only when all RDY becomes Low by the wired OR connection. This can be matched to the response of the slowest device when there is a slow response device. (Claim 6)
Here, since the broad transfer control unit is arranged on the memory control unit, the operation of the broad transfer control unit performs the memory burst read cycle operation as in FIGS. 36 and 37. Does not appear on the bus.

  By disposing the broad transfer control unit in this way, it is possible to reduce the use of the system bus and suppress the operation rate of the system bus.

Next, data transfer access 4 by the broadcast transfer control unit will be described. 40 and 42 show data transfer images when the broadcast transfer control unit is arranged on the memory control unit (items 6 and 17). This data transfer is a broad transfer from the memory N1-1 to the I / O devices N1-3 and N1-5. Here, the timing when the processing of the I / O device side control unit in the write access to the I / O device 4 is low speed and RDY cannot be responded with 0 wait is shown as 1 wait processing. The processing procedure is shown below (I / O device N1-3 can perform 0 wait operation).
(1) to (5) and (7) are the same as FIG. 36 and FIG.
(6) A bus cycle is executed at the timing shown in FIG.
T1: The bus I / F control unit N1-2 asserts BUSBUSY, BROADACK, AS, transfer destination I / O address & transfer mode information on Add & Com, and indicates the start of a broadcast burst write cycle to the I / O device. The first word data read from the memory on the buffer N1-2b is output to the data bus of the system bus.
T2: The bus I / F control unit N1-2 negates AS, and each bus I / F control unit decodes an address and recognizes an access request while AS is asserted. The bus I / F control units of the bus I / F control units N1-4 and N1-6 detect access requests. The bus I / F control unit N1-4 asserts RDY and outputs a response signal (first time) to the write request. (Note: described later)
T3: The buffer N1-4a takes in data. The bus I / F control unit N1-6 asserts RDY and outputs a response signal (first time) to the write request. (Note: described later)
T4: The buffer N1-6a takes in data. The bus I / F control unit N1-6 negates RDY. The second one-word data read from the memory on the buffer N1-2b is output to the data bus of the system bus. The bus I / F control unit N1-4 asserts RDY and outputs a response signal (second time) to the write request. (Note: described later)
T5: The buffer N1-4a takes in data. The bus I / F control unit N1-6 asserts RDY and outputs a response signal (second time) to the write request. (Note: described later)
T6: The buffer N1-6a takes in data. The bus I / F control unit N1-6 negates RDY. The third 1-word data read from the memory on the buffer N1-2b is output to the data bus of the system bus. The bus I / F control unit N1-4 asserts RDY and outputs a response signal (third time) to the write request. (Note: described later)
T7: The buffer N1-4a takes in data. The bus I / F control unit N1-6 asserts RDY and outputs a response signal (third time) to the write request. (Note: described later)
T8: The buffer N1-6a takes in data. The bus I / F control unit N1-6 negates RDY. The fourth 1-word data read from the memory on the buffer N1-2b is output to the data bus of the system bus. The bus I / F control unit N1-4 asserts RDY and outputs a response signal (fourth time) to the write request. (Note: described later)
T9: The buffer N1-4a takes in data. The bus I / F control unit N1-6 asserts RDY and outputs a response signal (fourth time) to the write request. (Note: described later)
T10: The buffer N1-6a takes in data. The bus I / F controllers N1-4 and N1-6 negate RDY. The bus I / F control unit N1-2 negates BUSBUSY, BLOADACK, Add & Com, and write data, and releases the bus.

  (Note) Since the bus I / Fs of a plurality of I / O control units simultaneously assert RDY, collision of RDY signals is avoided by wired OR connection. The RDY signal becomes Low only when all RDY becomes Low by the wired OR connection. This means that if there is a slow response device, the response of the slowest device can be matched (Section 6).

Next, the broadcast transfer / address setting method 1 will be described. 43 and 44 show data access when the host CPU makes settings for the DAR and TSR installed in the I / O device controller for broadcast transfer control. When there are four devices performing broad transfer, a total of eight single write cycles by the host CPU are required. The processing procedure of the timing chart of the single write cycle shown in FIG. 44 is shown below.
(1) The bus use right is acquired by the bus arbitration operation described with reference to FIGS. 7 and 8, and a bus cycle is started.
(2) A bus cycle is executed at the timing shown in FIG.
T1: The CPU (N2-8) asserts BUSBUSY, AS, transfer destination I / O address & transfer mode information on Add & Com, indicating the start of a single write cycle to the I / O device.
T2: The CPU (N2-8) negates AS, and each bus I / F control unit decodes the address and recognizes the access request while AS is asserted. The bus I / F control unit N2-4 detects an access request. The bus I / F control unit N2-4 asserts RDY and outputs a response signal to the write request (0 wait response).
T3: The data on the data bus of the system bus is taken into DAR (N2-4c) on the I / O device control unit (1).
T4: The bus I / F control unit N2-4 negates RDY. The CPU (N2-8) negates BUSBUSY, BLOADACK, Add & Com, and write data, and releases the bus.

Next, FIG. 45 and FIG. 46 show the information related to the DAR and TSR output in the broadcast data transfer cycle executed for the DAR and TSR implemented in the I / O device controller for broadcast transfer control. Then, an image and timing chart for controlling the I / O device control unit to take in the corresponding information are shown. Even if there are a plurality of devices performing the broad transfer, the setting is completed in one broadcast cycle by outputting the information on the bus. The DAR / TSR information setting method in the broadcast control according to the present invention will be described below with reference to FIGS.
(1) In order to execute such an operation, necessary information is previously set in the registers of the control units M-8 and M-9 by the host CPU.
<Broadcast request control register: L1-1>
・ Same as (1) in FIGS.
<Broadcast transfer control register: L1-3>
-Setting of DAR [0: 3]: Setting of DAR information on the I / O device control unit (Section 16)
DAR0: DAR information for I / O device 1 DAR1: DAR information for I / O device 2 DAR2: DAR information for I / O device 3 DAR3: DAR information for I / O device 4 • TMR setting: Data transfer mode is set To do.
Transfer size (transfer destination) = 4 bursts (Clause 13)
-Settings other than the above are the same as (1) in FIGS.
(2) Initial setting of the data transfer request source I / O device and control unit.
<Broad transfer related I / O device control register: L2-9>
-BMR setting: Address fixed-DAR setting: Setting is unnecessary because it is automatically written in the bus cycle-TSR setting: Setting is not required because it is automatically written in the bus cycle <I / O device setting>
・ Same as (1) in FIGS.
(3) When various settings are completed, the operation of the I / O device is started at the timing of starting the operation.

The above settings are set by the host CPU via the system bus.
(4) Assert BROADREQ, and the I / O device requests data transfer.
(5) The corresponding broad transfer control unit acquires the right to use the bus by the bus arbitration operation described with reference to FIGS. 7 to 11, and starts the bus cycle.
(6) A bus cycle is executed at the timing shown in FIG.

Explanation of the signal will be described.
AS: Indicates that the address and size information is valid.
Com: Indicates a broadcast burst write cycle (transfer mode).
Add: DAR information of I / O devices 1 to 4 is output in a time-sharing manner (section 16)
BROACKACK: When AS is Low, it indicates that Com and Add information of each I / O device is valid. When AS is High, it indicates a data transfer cycle.
Data: Indicates the data transfer size of the cycle when AS is Low (Item 13)
When AS is High, burst write data is sequentially output.
RDY: Data transfer completion response (response in 1-word units)
The processing procedure will be described with reference to FIG.
T1: Bus I / F control unit N3-2 asserts BUSBUSY, AS, BROACKACK [0: 3], DAR1 on Add, transfer mode information, T-Size on Data, and broadcasts to I / O device Indicates the start of a burst write cycle.
T2: The bus I / F control unit N3-2 negates BROADACK [1: 3], and each bus I / F control unit decodes the transfer mode between T1 and T2. The bus I / F controllers N3-4 and N3-6 recognize the broad transfer access request.
T3: The I / O device 1 takes in DAR1 on Add and T-Size on Data, and writes them in its own DAR and TSR, respectively. The bus I / F control unit N3-2 outputs DAR2 on Add, negates BROADACK0, and asserts BLOADACK1.
T4: The I / O device 2 takes in DAR2 on Add and T-Size on Data, and writes them in its own DAR and TSR, respectively. The bus I / F control unit N3-2 outputs DAR3 on Add, negates BROADACK1, and asserts BLOADACK2.
T5: The I / O device 3 takes in the DAR3 on Add and the T-Size on Data, and writes them in its own DAR and TSR. The bus I / F control unit N3-2 outputs DAR4 on Add, negates BROADACK2, and asserts BLOADACK3.
T6: The I / O device 4 takes in DAR4 on Add and T-Size on Data, and writes them in its own DAR and TSR, respectively. The bus I / F control unit N3-2 negates AS, asserts 2 from BROADACK0, performs a burst on Data, and outputs trie data. The bus I / F controllers N3-4 and N3-6 assert RDY (0 wait response).
T7 to T9: The bus I / F control units N3-4 and N3-6 sequentially fetch data into the buffers N3-4a and N3-6a and assert RDY (0 wait response).
T10: The bus I / F controllers N3-4 and N3-6 fetch data into the buffers N3-4a and N3-6a, and negate RDY. The bus I / F control unit N3-2 negates BUSBUSY, BROADACK [0: 3], Add & Com, and write data, and releases the bus.
(7) Same as (7) in FIGS.

  When the TSR setting is larger than the cycle transfer size (transfer destination) in the TMR of the broadcast transfer control register, the broadcast transfer cycle is executed in a plurality of times, but in the second and subsequent broadcast burst write cycles, FIG. The bus cycle indicated by is executed. Because it is possible to control the second and subsequent addresses in the transfer destination address & transfer size control unit L2-8 in FIG. 30 on the I / O device side, it is not necessary to transfer the address information after the second time. Although the address information may be transferred every time, it does not make much sense because the specification efficiency of the system bus is reduced.

Next, FIGS. 45 and 47 show a method for setting DAR and TSR information in broadcast control when the signals output from the address information and transfer size information described in FIG. 46 are changed to the signals shown below. (1) to (5) and (7) are the same as in FIG.
(6) A bus cycle is executed at the timing shown in FIG.

The signal will be described.
AS: Indicates that the address and size information is valid.
Com: Indicates a broadcast burst write cycle (transfer mode).
Add: Indicates the data transfer size of the cycle (item 14).
BROADACK: When AS is Low, it indicates that Com and Add information of each I / O device is valid. When AS is High, it indicates a data transfer cycle.
Data: When AS is Low, DAR information of I / O devices 1 to 4 is output in a time division manner (Section 15). When AS is High, burst write data is sequentially output.
RDY: Data transfer completion response (response in 1-word units)
A processing procedure will be described.
T1: Bus I / F control unit N3-2 asserts BUSBUSY, AS, BROADACK [0: 3], T-Size on Add, transfer mode information, DAR1 on Data, and broadcasts to I / O device Indicates the start of a burst write cycle.
T2: The bus I / F control unit N3-2 negates BROADACK [1: 3], and each bus I / F control unit decodes the transfer mode between T1 and T2. The bus I / F controllers N3-4 and N3-6 recognize the broad transfer access request.
T3: The I / O device 1 takes in DAR1 on Data and T-Size on Add, and writes it in its own DAR and TSR, respectively. The bus I / F control unit N3-2 outputs DAR2 on Data, negates BROADACK0, and asserts BLOADACK1.
T4: The I / O device 2 takes in DAR2 on Data and T-Size on Add, and writes them in its own DAR and TSR, respectively. The bus I / F control unit N3-2 outputs DAR3 on Data, negates BROADACK1, and asserts BLOADACK2.
T5: The I / O device 3 takes in the DAR3 on Data and the T-Size on Add, and writes them in its own DAR and TSR, respectively. The bus I / F control unit N3-2 outputs DAR4 on Data, negates BROADACK2, and asserts BLOADACK3.
T6: The I / O device 4 takes in DAR4 on Data and T-Size on Add, and writes them in its own DAR and TSR, respectively. The bus I / F control unit N3-2 negates AS, asserts 2 from BROADACK0, and outputs burst write data on Data. The bus I / F controllers N3-4 and N3-6 assert RDY (0 wait response).
T7 to T9: The bus I / F control units N3-4 and N3-6 sequentially fetch data into the buffers N3-4a and N3-6a and assert RDY (0 wait response).
T10: The bus I / F controllers N3-4 and N3-6 fetch data into the buffers N3-4a and N3-6a, and negate RDY. The bus I / F control unit N3-2 negates BUSBUSY, BROADACK [0: 3], Add & Com, and write data, and releases the bus.

  The information distribution and method on the bus relating to the information setting to the DAR and TSR is an example and can be applied to other bus specifications, and therefore the bus specifications are not limited here.

  Finally, the system configuration shown in FIGS. 3 and 4 is an example, and the present invention can be applied to other system configurations.

  According to the present invention, when transferring the same content to different media (input / output processing units) at the same time, the data transfer has been conventionally performed for each medium. However, in the present invention, it is possible to suppress useless use of the system bus by completing the data transfer once.

  For example, data transfer in the case of an application specification in which 24 Mbps HD (High Definition) video is recorded on two HDDs, while another 24 Mbps HD content video recorded on the HDD is simultaneously distributed to different media. The effective value of the data transfer rate required for the system is 27 MB / s in the conventional system bus (FIG. 3), but 18 MB / s in the system bus (FIG. 4) of the present invention, which is 9 MB / s. However, it is not necessary to wastefully use the bandwidth.

FIG. 2 is an explanatory diagram of a general digital AV system block outline. An explanatory view of an outline of an AV system block connected by a system bus. Explanatory drawing of the conventional AV data transfer image (real-time reproduction | regeneration & real-time delivery). Explanatory drawing of the AV data transfer image (real-time reproduction | regeneration & real-time delivery) of this invention. Explanatory drawing of the conventional real-time data transfer timing chart. Explanatory drawing of the real-time data transfer timing chart of this invention. Explanatory drawing of the conventional system bus arbitration control and block. Explanatory drawing of the conventional system bus request | requirement arbitration control and timing chart. Explanatory drawing of the conventional DMA transfer request arbitration control and timing chart. Explanatory drawing of the system bus arbitration control / block of this invention. Explanatory drawing of the DMA transfer request arbitration control and timing chart 1 of this invention. Explanatory drawing of the DMA transfer request arbitration control and timing chart 2 of this invention. Explanatory drawing of the DMA transfer request arbitration control and timing chart 3 of this invention. Explanatory drawing of the DMA transfer request | requirement arbitration control and timing chart 4 of this invention. Explanatory drawing of a DMA internal structure block. FIG. 3 is an explanatory diagram of a DMA channel register configuration. Explanatory drawing of the block of a memory controller. Explanatory drawing of the block of an I / O controller. Explanatory drawing of a memory mounting type block. Explanatory drawing of the data transfer image 1 in the data transfer access by a DMA controller. Explanatory drawing of a data transfer cycle timing chart (data transfer image 1). Explanatory drawing of the data transfer image 2 in the data transfer access by a DMA controller. Explanatory drawing of a data transfer cycle timing chart (data transfer image 2). Explanatory drawing of the data transfer image 3 in the data transfer access by a DMA controller. Data transfer cycle timing chart (data transfer image 3) explanatory diagram. Explanatory drawing of the data transfer image 4 in the data transfer access by a DMA controller. Explanatory drawing of a data transfer cycle timing chart (data transfer image 4). Explanatory drawing of the internal block of the broadcast transfer control part of this invention. Explanatory drawing of BR (n) signal control of the broadcast arbitration control register (RER) of this invention. The explanation part of the I / O control part block of the present invention. Explanatory drawing of the memory control part block of this invention. Explanatory drawing of the broadcast transfer control part register structure of this invention. Explanatory drawing of the broadcast arbitration control part register structure of this invention. Explanatory drawing of the I / O device side control register structure of this invention. Explanatory drawing of the broadcast arbitration control part register detail of this invention. Explanatory drawing of the data transfer image in the data transfer access 1 by the broadcast transfer control part of this invention. Explanatory drawing of a data transfer cycle timing chart (system bus). Explanatory drawing of the data transfer image in the data transfer access 2 by the broadcast transfer control part of this invention. Explanatory drawing of a data transfer cycle timing chart (system bus). Explanatory drawing of the data transfer image in the data transfer access 3 by the broadcast transfer control part of this invention. Explanatory drawing of the data transfer cycle timing chart 1 (system bus). Explanatory drawing of the data transfer cycle timing chart 2 (system bus) in the data transfer access 3 by the broadcast transfer control part of this invention. The block explanatory view of the broadcast control and address setting method 1 of the present invention. Explanatory drawing of the timing chart in the broadcast control and the address setting method 1 of this invention. The block explanatory view of the broadcast control / address setting method 2 of the present invention. Explanatory drawing of the timing chart 1 in the broadcast control and the address setting method 2 of this invention. Explanatory drawing of the timing chart 2 in the broadcast control and the address setting method 2 of this invention.

Claims (17)

Supports CPU, memory, multiple I / O devices, device controller that controls the device or memory, system bus connecting these multiple devices, and burst transfer where the system bus is in high-speed data transfer mode In an AV system having a bus arbitration control unit that arbitrates bus use rights in response to bus requests from a plurality of bus masters,
A data transfer control unit for performing one-to-many broadcast on the system bus, which enables simultaneous transfer of one block data of a certain size to a plurality of devices in one bus cycle by using a burst transfer function; The AV system is characterized in that the transfer destination device control unit has a register means for holding a transfer destination address for transferring received data to a device or memory controlled by the device control unit. The AV system according to claim 1,
An AV system characterized in that the device control unit on the data transmission side has a data buffer for broadcast transfer. The AV system according to claim 2, wherein
An AV system characterized in that the device control unit has means for pre-reading a request that has been read-accessed once before the next access comes and holding the data in the data buffer. In the AV system according to claim 2 or 3,
The AV system according to claim 1, wherein the device control unit has two data buffers that alternately respond to read access. The AV system according to claim 1,
An AV system characterized in that the device control unit on the data receiving side has a write buffer corresponding to the broadcast transfer size. The AV system according to claim 1,
An AV system comprising timing adjustment control means for reliably completing data transfer simultaneously to a plurality of devices in a bus cycle during broadcast data transfer. The AV system according to claim 1,
An AV system comprising a broadcast transfer request arbitration control unit that arbitrates the start timing of a data transfer cycle in response to broadcast data transfer requests from a plurality of devices. The AV system according to claim 7,
The broadcast transfer request arbitration control unit has a means for controlling to execute a memory read cycle at the same time as detecting one request and controlling to execute a broadcast write cycle when all the requests are completed. AV system. The AV system according to claim 8, wherein
The broadcast transfer request arbitration control unit performs control to release the bus once after the completion of the memory read cycle, and to assert the bus request again to execute the broadcast write cycle when all the requests are completed. An AV system characterized by comprising: The AV system according to claim 7,
An AV system characterized by comprising control means for preventing a request signal for performing no operation from being arbitrated because all of a plurality of broadcast transfer request signals do not always request a broadcast transfer operation. The AV system according to claim 7,
An AV system comprising means for controlling the arbitration control unit to be disabled regardless of the state of the broadcast transfer request signal. The AV system according to claim 1,
The AV system characterized in that the control unit on the data receiving side has means for holding the size of data transfer (number of data transfer bytes) at the time of broadcast data transfer. The AV system according to claim 12, wherein
In the step before starting the data transfer of the broadcast transfer cycle, information indicating the data transfer size in that cycle is added to the data bus, and this information is taken into the means for holding the data transfer size of the broadcast transfer at the data transfer destination. An AV system comprising means capable of The AV system according to claim 12, wherein
In the step before starting the data transfer in the broadcast transfer cycle, information indicating the data transfer size in that cycle is added to the address bus, and this information is stored in the register means for holding the data transfer size of the broadcast transfer at the data transfer destination. An AV system comprising means capable of capturing. The AV system according to claim 1,
Register means for adding information indicating the transfer destination address on the data transfer side to the data bus in the step before starting data transfer in the broadcast transfer cycle, and holding this information for data transfer destination address information of the broadcast transfer at the data transfer destination An AV system characterized by comprising means capable of importing into the system. The AV system according to claim 1,
Information indicating the transfer destination address on the data transfer side is added to the address bus in the step before starting the data transfer in the broadcast transfer cycle, and this information is used as means for holding the data transfer destination address information of the broadcast transfer at the data transfer destination. An AV system characterized by comprising means capable of being captured. An AV system comprising a broadcast data transfer control unit of the AV system according to claim 1 and a broadcast transfer request arbitration control unit according to claims 7 to 11 in a memory control unit as a data transfer source.

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