JP2005027392A - High speed comparator and dc/dc converter using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize stabilized operation while ensuring a maximum duty even in a DC/DC converter having a high switching frequency. <P>SOLUTION: The comparator comprises a differential circuit 12 provided with a diode connection load where the drain and the gate are connected, a self-bias differential amplifier 13 receiving the output from the differential circuit 12, and an output stage 14 wherein a circuit power supply is shared among the differential circuit 12, the self-bias differential amplifier 13 and the output stage 14 through an internal power supply circuit 11. In a DC/DC converter comprising a first comparator for comparing the output voltage from an error amplifier with a saw-tooth voltage, a second comparator for comparing a voltage level determining a soft start time with the saw-tooth voltage, and a circuit performing switching control of a switching transistor with the outputs from both comparators, the first and second comparators employ above-mentioned arrangement. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PWM type DC / DC converter that generates a pulse by performing pulse width modulation according to an error between an input voltage and a predetermined voltage, and more particularly, a DC / DC converter using a comparator circuit capable of high-speed operation. It is about.
[0002]
[Prior art]
A circuit of a conventional DC / DC converter will be described with reference to FIG.
The step-up operation portion of the conventional chopper type step-up switching regulator has a basic configuration as shown in FIG. When the NMOS transistor 124 is in the ON state, a switch current flows from the input voltage (VIN) 121 to the coil 122, energy is accumulated in the coil 122, and when the NMOS transistor 124 is in the OFF state, the energy accumulated in the coil 122 is input. After being superposed on the voltage and rectified by the diode 123, the output is smoothed by the capacitor 125, thereby performing a boosting operation.
In particular, in a step-up PWM switching regulator, a dead time control voltage (DTC voltage) is set to limit the duty ratio of an output pulse when determining the maximum pulse width.
[0003]
FIG. 11 is a block diagram of a typical step-up DC / DC converter.
The feedback voltage (VFB) via the output of COUT from the step-up DC / DC converter circuit shown in FIG. 10 and the reference voltage (Vref) are compared by the error amplifier 140, and the output and the output (triangular wave) of the triangular wave generation circuit 132 are compared. The first comparator 141 performs comparison. The second comparator 142 compares the dead time control voltage (DTC) including the soft start function set by the capacitor 136 and the resistors 137 and 138 with the triangular wave generated by the triangular wave generating circuit 132. Further, the NAND circuit 139 ANDs the output of the first comparator 141 and the output of the second comparator 142 to determine the duty width, and the NAND circuit 133 controls the duty width.
Further, by providing an external terminal for the reference voltage 131, the maximum duty and soft start time can be set.
[0004]
Conventionally, the two-stage amplification type comparators 141 and 142 are used as the first and second comparators for comparing the voltages as described above. However, in recent years, DC / DC converters using a high-frequency switching frequency have been used in portable devices and products targeted for space saving in order to reduce the size of components such as coils. Therefore, the delay due to the comparator has become a problem as an influence on the maximum duty width and stability as a DC / DC converter.
[0005]
FIG. 12 is a diagram showing experimental results of DTC voltage and duty using a conventional comparator.
In the left figure, when DTC is 0.2 V to 0.9 V, the duty is 0.2 to 0.3 and the duty is 0 to 10%. When DTC is 0.9, the duty is 90 to 100%. In the right figure, when DTC is set to 0.82 to 0.92, the duty ratio is 90% or more at 0.9 or more. As is apparent from this figure, it can be seen that the linearity is particularly lost where the duty is 90% or more. This means that the duty cannot be secured due to the delay of the comparator.
[0006]
FIG. 8 is a circuit diagram of a conventional two-stage amplification type comparator.
The gate inputs of the PMOS transistor 83 and the PMOS transistor 84 are compared, the difference output is applied as the gate voltage of the NMOS transistor 87, and the voltage between the source of the PMOS transistor 82 and the drain of the NMOS transistor 87 is divided into output voltages to the inverter 88. Apply.
Here, the NMOS transistor M1 is for enabling high-speed operation by limiting the output swing width.
[0007]
FIG. 9 is a diagram illustrating another example of a conventional comparator circuit.
This circuit configuration refers to CMOS ANALOG CIRCUIT DESIGN 2nd edition (author Phillip E. Allen et al.) (See Non-Patent Document 1). This circuit includes a preamplifier, a determination circuit, and an output buffer. The PMOS transistor 92 and the PMOS transistor 95 form a diode, and form a positive feedback circuit between the source and gate of the NMOS transistor 101 and NMOS transistor 103.
The preamplifier uses a diode-connected load to increase the speed by suppressing the gain, and the determination circuit in the next stage uses positive feedback to determine the output signal. The signal is output to an output buffer circuit including a self-bias type differential amplifier. With this circuit configuration, a high-speed comparator is realized.
However, the determination circuit requires a physical time for determining the signal, and this time is one cause of the delay of the comparator.
[0008]
[Non-Patent Document 1]
CMOS ANALOG CIRCUIT DESIGN 2nd edition (author Phillip E. Allen et al.)
[0009]
[Problems to be solved by the invention]
As described above, in the circuit configuration of the conventional DC / DC converter, the duty required for the comparator to be delayed cannot be ensured, and in other circuit configurations, the physical time for securing the output signal is not obtained. This was necessary, and that time caused the delay of the comparator.
[0010]
Therefore, an object of the present invention is to provide a comparator that operates at high speed in order to reduce the influence on the maximum duty width and stability due to the delay of the comparator.
Another object of the present invention is to provide a DC / DC converter capable of ensuring a maximum duty and performing a stable operation even in a DC / DC converter having a high switching frequency by using a high-speed comparator with a small delay time. It is in.
[0011]
[Means for Solving the Problems]
The comparator of the present invention includes a differential circuit having a diode-connected load having a drain and a gate connected, and a self-bias type differential amplifier that receives the output of the differential circuit as an input, and has a circuit power supply internally. The power supply circuit is common to the differential circuit and the self-bias type differential amplifier.
A DC / DC converter according to the present invention is a pulse width modulation control type DC / DC converter that outputs after adjusting a supplied voltage by changing a ratio of an on period and an off period of a switching transistor. An error amplifier that amplifies and outputs a difference from a reference voltage of a detection voltage obtained by dividing the voltage output after adjustment, a first comparator that compares the output voltage of the error amplifier with a sawtooth voltage, and soft start A second comparator for comparing a voltage value for determining a time and a sawtooth voltage; and a circuit for controlling the switching of the switching transistor by using outputs of both comparators, wherein the comparator described above is used for the first and second comparators. It is characterized by that.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram of a comparator circuit showing an embodiment of the present invention.
The comparator of this embodiment has a configuration including a differential circuit 12 that compares input signals, a self-bias type differential amplifier 13, and an output stage circuit 14, and each circuit voltage is shared by the internal power supply 11. ing.
The internal power supply 11 is a regulator circuit and is configured to keep the output voltage at a certain voltage.
[0013]
FIG. 2 is a detailed circuit diagram of the differential circuit in FIG.
Here, the diode connection, that is, the loads M2 and M3 in which the respective drains and gates of the NMOS transistors M2 and M3 are connected is used to increase the speed while suppressing the gain. At this time, the output width swings around the threshold value Vth of the NMOS transistors M2 and M3 due to diode connection.
[0014]
FIG. 3 is a detailed circuit diagram of the self-bias type differential amplifier and the output stage circuit in FIG.
The PMOS transistor 31 and the NMOS transistor 36 form a self-bias, and the inverter 37 forms an output stage. This self-bias type differential amplifier is configured to accelerate the output signal when the output of the differential circuit in the previous stage is input to the gates of the PMOS transistors 32 and 34 and the NMOS transistors 33 and 35.
[0015]
FIG. 4 is an operation explanatory diagram of the self-bias type differential amplifier in FIG.
Here, since the output level of the first-stage differential circuit is near the threshold value Vth of the NMOS transistors 43 and 45, there is a problem that the first-stage differential circuit is easily influenced by the change in the threshold of the next-stage differential amplifier. Therefore, in this embodiment, a configuration in which these circuits are placed under an internal power supply is adopted. By adopting this circuit configuration, the operating point between the first-stage differential circuit and the next-stage differential amplifier can be kept constant even when the input voltage changes, resulting in a high-speed comparator. be able to.
Further, by adopting the circuit configuration of the present embodiment, the delay time due to the determination circuit in the conventional comparator 2 can be omitted, and higher speed can be realized.
[0016]
FIG. 7 is a diagram showing the results of comparison experiments using the present invention and conventional comparator circuits.
The diagram on the left shows the relationship between DTC and duty when the conventional type and the present invention are 3.3V, and the diagram on the right shows the relationship between DTC and duty when the conventional type and the present invention are 5.0V. The broken line indicates the present invention, and the solid line indicates the conventional type.
Here, the circuit used in the experiment is different from the comparator circuit only and is measured under the condition that the frequency is constant. The input voltage is 3.3V, 5.0V, and the internal power supply is fixed at 3V. As a result of this experiment, the delay time of the comparator of this embodiment is smaller than that of the conventional type, the maximum duty can be taken to 90% or more, and there is no problem in the operation of the circuit of the present invention even when the input voltage changes. I understand that.
[0017]
5 and 6 are diagrams showing experimental results of the DTC voltage and duty in the comparator circuit of the present invention. FIG. 5 shows a low frequency (frequency 1.1 MEG), and FIG. 6 shows a high frequency (frequency 2.2 MEG). In this case, both cases are 3.3 V (solid line) and 5.0 V (broken line).
5 and 6, the curves for 3.3 V and 5.0 V overlap, indicating that the characteristics do not change even if the voltage changes. In other words, FIG. 5 shows the results indicating that the circuit of the present invention operates normally in the entire DTC voltage range, and as shown in FIG. It is ensured that the speed of the comparator can be increased.
[0018]
【The invention's effect】
As described above, according to the present invention, in the differential circuit having a diode-connected load and the comparator circuit having the self-bias type differential amplifier, by using the comparator circuit in which the circuit power supply is shared by the internal power supply circuit. Even in a DC / DC converter having a high switching frequency, the maximum duty can be ensured and a stable operation can be realized.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of a comparator circuit showing an embodiment of the present invention.
FIG. 2 is a detailed circuit diagram of a differential circuit in the comparator circuit in FIG.
3 is a circuit configuration diagram of a self-bias type differential amplifier and an output stage in the comparator circuit in FIG. 1. FIG.
4 is an operation explanatory diagram of the self-bias type differential amplifier in FIG. 3. FIG.
FIG. 5 is a diagram showing experimental results of DTC voltage and duty in the comparator circuit of the present invention.
FIG. 6 is a diagram showing experimental results of DTC voltage and duty at a high frequency in the comparator circuit of the present invention.
FIG. 7 is a diagram showing the results of a comparison experiment using a conventional type and a comparator circuit of the present invention.
FIG. 8 is a detailed circuit configuration diagram of a conventional comparator circuit.
FIG. 9 is another detailed circuit configuration diagram of a conventional comparator circuit.
FIG. 10 is a detailed circuit diagram of a main part of the step-up DC / DC converter circuit.
FIG. 11 is a detailed configuration diagram of a step-up DC / DC converter circuit.
FIG. 12 is a diagram showing experimental results of DTC voltage and duty using a conventional comparator circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Internal power supply, 12 ... Differential circuit, 13 ... Self-bias type differential amplifier,
14 ... Output stage, M2, M3 ... NMOS transistors forming diodes,
21 ... PMOS transistor forming a constant current load,
33, 35, 36, 43, 45 ... NMOS transistors,
22, 23, 32, 34, 42, 44 ... PMOS transistors,
31, 41 ... PMOS transistors for suppression,
36, 46 ... NMOS transistors for acceleration,
20 ... discharge overcurrent detector, 36 ... NMOS transistor forming load,
37, 47 ... inverters forming the output stage, 121 ... input voltage,
122: Coil, 124, 134: NMOS transistor,
125, 135 ... capacitor, 123 ... diode, 131 ... reference voltage,
132 ... Triangular wave generation circuit, 133 ... AND circuit, 139 ... NAND circuit,
141, 142: Comparators 1, 2, 3, 140: Error amplifiers.

Claims (2)

A differential circuit having a diode-connected load having a drain and a gate connected to each other and a self-bias type differential amplifier having an output of the differential circuit as an input; Comparator circuit that is shared by the circuit and the self-bias type differential amplifier. A pulse width modulation control type DC / DC converter that outputs after adjusting a supplied voltage by changing a ratio of an on period and an off period of a switching transistor,
An error amplifier that amplifies and outputs the difference from the reference voltage of the detection voltage obtained by dividing the voltage output after the adjustment, a first comparator that compares the output voltage of the error amplifier with a sawtooth voltage, and software 2. The first and second comparators according to claim 1, further comprising: a second comparator that compares a voltage value that determines a start time with a sawtooth voltage; and a circuit that controls the switching transistor by using the outputs of both comparators. A DC / DC converter characterized by using a comparator.

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