JP2005027181A - Mos integrated circuit and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS integrated circuit capable of obtaining a wide dynamic range and a high gain. <P>SOLUTION: MOS transistors 11, 12 constitute a cascode amplifier circuit. The gate oxide film of the MOS transistor 12 is formed by using a process other than a process of forming the gate oxide film of the MOS transistor 11, and the thickness of the gate oxide film of the MOS transistor 12 is formed thinner than the thickness of the gate oxide film of the MOS transistor 11. Thus, the cascode amplifier circuit having a wide dynamic range and a high gain is realized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS integrated circuit and a manufacturing method thereof.
[0002]
[Prior art]
It is considered to integrate an AM receiver circuit using bipolar transistors. It is also considered to integrate part or all of the AM receiving circuit using MOS transistors.
[0003]
As an amplifier circuit used in a semiconductor integrated circuit, for example, a cascode amplifier circuit as shown in Patent Document 1 is known.
When an amplifier circuit is formed using a bipolar transistor on a semiconductor integrated circuit substrate, it is necessary to increase the breakdown voltage of the bipolar transistor and supply a large power supply voltage to the collector in order to increase the dynamic range.
[0004]
[Patent Document 1]
JP 2002-164746 A (FIG. 6)
[0005]
[Problems to be solved by the invention]
Also in the MOS transistor, in order to increase the dynamic range, it is necessary to increase the power supply voltage to be applied, and it is necessary to increase the breakdown voltage of the MOS transistor accordingly. However, if the gate oxide film is thickened to increase the breakdown voltage of the MOS transistor, the mutual conductance becomes small and a large gain cannot be obtained.
[0006]
An object of the present invention is to obtain a wide dynamic range and a large gain in a MOS integrated circuit.
[0007]
[Means for Solving the Problems]
The MOS integrated circuit according to the present invention includes a first MOS transistor having a first gate oxide film, and a second MOS transistor cascode-connected to the first MOS transistor, and the second MOS transistor A second gate oxide film thinner than the first gate oxide film is formed in the second MOS transistor so that the gain of the second MOS transistor is larger than that of the first MOS transistor.
[0008]
According to the present invention, a wide dynamic range can be secured and a large gain can be obtained in a cascode-connected circuit.
In the above invention, the first gate oxide film and the second gate oxide film are formed by different processes.
[0009]
As described above, since the second gate oxide film of the second MOS transistor is formed by a process different from the process of forming the first gate oxide film of the first MOS transistor, the second gate oxide film is formed. The film can be made thinner than the first gate oxide film, and the gain of the second MOS transistor can be made larger than the gain of the first MOS transistor. As a result, the dynamic range of the cascode-connected circuit can be widened and the gain can be increased.
[0010]
According to another MOS integrated circuit of the present invention, a first signal and an inverted signal of the first signal are input to respective gates, and first and second MOS transistors whose sources are connected to each other; And the inverted signal of the first signal are input to the respective gates, the third and fourth MOS transistors whose sources are connected to each other, and the sources and drains of the first and second MOS transistors are connected to each other. The fifth MOS transistor to which the second signal is input to the gate and the sources and drains of the third and fourth MOS transistors are connected, and a signal obtained by inverting the second signal is input to the gate. The fifth and sixth MOS transistors, and the gains of the fifth and sixth MOS transistors are larger than those of the first to fourth MOS transistors. The oxide film of the MOS transistor thinner than oxide film of the first to fourth MOS transistors.
[0011]
According to the present invention, the gains of the fifth and sixth MOS transistors are increased by widening the dynamic range of the first to fourth MOS transistors and simultaneously reducing the thicknesses of the fifth and sixth oxide films. can do.
In the above invention, the difference voltage between the drain voltage of the first MOS transistor and the drain voltage of the third MOS transistor, and the difference between the drain voltage of the second MOS transistor and the drain voltage of the fourth MOS transistor. Output the voltage to the same external output terminal.
[0012]
With this configuration, a signal obtained by multiplying the first signal and the second signal can be output to the external terminal.
In the above invention, the seventh MOS transistor in which the source and the drain of the fifth and sixth MOS transistors are connected, the seventh MOS transistor and the gate are connected in common, and a constant current flows through the drain. And an eighth MOS transistor set to.
[0013]
With this configuration, a constant drain current can be passed through the fifth and sixth MOS transistors.
In the above invention, the first signal is a local oscillation signal, and the second signal is a broadcast signal reception signal.
[0014]
With this configuration, it is possible to increase the amplification degree of the intermediate frequency signal obtained from the reception signal and the local oscillation signal and to increase the dynamic range of the signal.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an amplifier circuit according to a first embodiment of the present invention.
In the embodiment described below, an AM / FM receiver circuit is formed on one integrated circuit substrate by a CMOS process.
[0016]
The drain of the n-channel MOS transistor 11 (corresponding to the first MOS transistor of claim 1) is connected to the power supply voltage VDD via the resistor R1. Alternatively, it is connected to the power supply voltage VDD via an inductance.
A voltage obtained by dividing the power supply voltage VDD by the resistors R2 and R3 is supplied to the gate of the n-channel MOS transistor 11 as a gate voltage. A capacitor C1 is connected to the gate of the n-channel MOS transistor 11, and the other end of the capacitor C1 is grounded.
[0017]
The drain of the n-channel MOS transistor 12 (corresponding to the second MOS transistor of claim 1) is connected to the source of the MOS transistor 11, and the source of the MOS transistor 12 is grounded. A capacitor C2 is connected to the gate of the MOS transistor 12, and an input signal Vs is input to the other end of the capacitor C2. MOS transistors 11 and 12 constitute a cascode amplifier circuit.
[0018]
The gate of the MOS transistor 12 is connected to the drain of the n-channel MOS transistor 13 via the resistor R4, and the constant current source 14 is connected to the gate of the MOS transistor 13. The MOS transistor 13 and the constant current source 14 supply a constant bias voltage to the MOS transistor 12.
[0019]
The MOS transistor 12 and the MOS transistor 11 are cascode-connected, and the input signal Vs is amplified by the MOS transistors 12 and 11 and output from the drain of the MOS transistor 11.
Assuming that the gate voltage V1, the gate-source voltage Vgs of the MOS transistor 11, the drain voltage V2 of the MOS transistor 12, and the power supply voltage VDD, V1 and V2 can be expressed by the following equations.
[0020]
V1 = {R3 / (R2 + R3)} VDD
V2 = V1-Vgs
Also, assuming that the mutual conductance gm of the MOS transistor and the capacitance of the gate oxide film per unit area are C0,
gm = ∂ID / ∂VG = μ · C0 (W / L)
It can be expressed.
[0021]
Since the drain voltage V2 of the MOS transistor 12 is a value obtained by subtracting the gate-source voltage Vgs from the gate voltage V1 of the MOS transistor 11, the withstand voltage between the drain and source of the MOS transistor 12 needs to be larger than V1-Vgs. is there. The breakdown voltage between the drain and the source depends on the thickness of the gate oxide film.
[0022]
On the other hand, in order to increase the gain of the MOS transistor, it is necessary to increase the value of the mutual conductance gm. From the above equation, if the channel width W and the channel length L are constant, the capacitance C0 of the gate oxide film may be increased in order to increase the mutual conductance value. In order to increase the capacitance C0, the oxide film may be thinned.
[0023]
Therefore, the gate oxide film of the MOS transistor 12 is formed by a process different from the process of forming the gate oxide film of the MOS transistor 11, and the gate oxide film of the MOS transistor 12 is made thinner than the gate oxide film of the MOS transistor 11. At this time, the thickness of the gate oxide film is designed so that a breakdown voltage larger than the voltage applied to the drain of the MOS transistor 12 can be obtained. When the gate oxide film of the MOS transistor 12 is made thinner than the gate oxide film of the MOS transistor 11, the value of the mutual conductance gm is larger than that of the MOS transistor 11, so that the gain is increased.
[0024]
By designing the thickness of the gate oxide film of the MOS transistor 12 as described above, the gain of the MOS transistor 12 is made larger than the gain of the MOS transistor 11 and the breakdown voltage required for the MOS transistor 12 is ensured. Can do. This can be realized if there is a process for forming gate oxide films having different thicknesses in the manufacturing process of the MOS integrated circuit.
[0025]
According to the first embodiment described above, the oxide film of the MOS transistor 12 is made thinner than the oxide film of the MOS transistor 11, and the gain is set larger than that of the MOS transistor 11, thereby increasing the amplification factor of the input signal Vs. Can do. In this case, since the gate oxide film of the MOS transistor 11 is thicker than the gate oxide film of the MOS transistor 12, the breakdown voltage of the drain of the MOS transistor 11 can be increased and the dynamic range can be widened. As a result, the dynamic range of the amplifier circuit composed of the cascode-connected MOS transistors 11 and 12 can be widened and the gain can be increased.
[0026]
Next, FIG. 2 is a circuit diagram of an intermediate frequency mixing circuit according to a second embodiment of the present invention.
A local oscillation signal V0 output from a local oscillation circuit (not shown) is input to the gate of an n-channel MOS transistor (hereinafter referred to as MOS transistor) 21, and the phase of the local oscillation signal V0 is input to the gate of the n-channel MOS transistor 22. -V0 (a signal having a phase difference of 180 degrees with respect to V0) is input.
[0027]
The sources of the MOS transistor 21 and the MOS transistor 22 are connected to each other, the drain of the MOS transistor 21 is connected to the upper side 29a (as viewed from the front of FIG. 2) of the tuning coil 29, and the drain of the MOS transistor 22 is below the tuning coil 29. Connected to side 29b.
[0028]
Similarly, a local oscillation signal V0 is input to the gate of the MOS transistor 24, and a signal −V0 obtained by inverting the phase of the local oscillation signal is input to the gate of the MOS transistor 23.
The sources of the MOS transistor 24 and the MOS transistor 23 are connected to each other, the drain of the MOS transistor 24 is connected to the lower side 29b of the tuning coil, and the drain of the MOS transistor 23 is connected to the upper side 29a of the tuning coil.
[0029]
The reception signal Vs is input to the gate of the n-channel MOS transistor 25, and the drain is connected to the sources of the MOS transistors 21 and 22.
A signal −Vs obtained by inverting the phase of the received signal is input to the gate of the n-channel MOS transistor 26, and the drain is connected to the sources of the MOS transistors 23 and 24.
[0030]
The MOS transistors 21 to 24 constitute a multiplication circuit. The multiplication circuit receives a signal obtained by amplifying the reception signals Vs and −Vs output from the drains of the n-channel MOS transistors 25 and 26, an intermediate frequency signal V0, and an inverted signal thereof. , A signal obtained by multiplying these signals, that is, a value obtained by multiplying the amplitude of the intermediate frequency signal V0 and the reception signal Vs as an amplitude, and the difference between the frequency of the sum of the frequency of the reception signal Vs and the frequency of the intermediate frequency signal V0. A signal having a frequency is output to the tuning coil 29.
[0031]
The sources of the MOS transistors 25 and 26 are connected to the drain of the MOS transistor 27, and their gates are connected to the gate and drain of the MOS transistor 28. Current is supplied from a constant current source to the drain and gate of the MOS transistor 28 and the gate of the MOS transistor 27.
[0032]
The MOS transistors 28 and 27 constitute a current mirror circuit, and a drain current substantially equal to the drain current of the MOS transistor 28 flows to the MOS transistor 27.
A capacitor 30 is connected to both ends of the tuning coil 29, and a power supply voltage VDD is supplied to the center of the winding of the tuning coil 29. A ceramic filter 31 having a band characteristic that passes a target intermediate frequency signal and blocks a signal of another frequency is connected in series to one terminal on the secondary side of the tuning coil 29. The other end of the next side is grounded. These tuning coil 29, capacitor 30 and ceramic filter 31 are connected as external components to the output terminal of the semiconductor integrated circuit board.
[0033]
The output side of the ceramic filter 31 is connected to an input terminal of the semiconductor integrated circuit board, and outputs an intermediate frequency signal to an intermediate frequency amplifier circuit inside the semiconductor integrated circuit board.
When the above intermediate frequency mixing circuit is formed on a semiconductor integrated circuit substrate, the gate oxide films of the MOS transistors 25 and 26 are formed by a process different from the process of forming the gate oxide films of the MOS transistors 21 to 24, The gate oxide films of the MOS transistors 25 and 26 are made thinner than the gate oxide film of the MOS transistor 11. At this time, the thickness of the gate oxide film is designed so that a breakdown voltage larger than the voltage applied to the drains of the MOS transistors 25 and 26 is obtained.
[0034]
By designing the thicknesses of the gate oxide films of the MOS transistors 25 and 26 as described above, the gains of the MOS transistors 25 and 26 are made larger than the gains of the MOS transistors 21 to 24 and necessary for the MOS transistors 25 and 26. It is possible to ensure a withstand voltage.
[0035]
According to the second embodiment described above, the gate oxide films of the MOS transistors 25 and 26 are made thinner than the gate oxide films of the MOS transistors 21 to 24, and the oxide film thickness is set so as to obtain a desired breakdown voltage. By designing, the gains of the MOS transistors 25 and 26 can be made larger than those of the MOS transistors 21 to 24. At this time, since the gate oxide films of the MOS transistors 21 to 24 are thicker than the gate oxide films of the MOS transistors 25 and 26, the dynamic range of the MOS transistors 21 to 24 can be increased. Thereby, the dynamic range of the intermediate frequency mixing circuit shown in FIG. 2 can be widened and the amplification degree can be increased.
[0036]
The present invention is not limited to the above embodiment, and may be configured as follows.
In the second embodiment, the case where the present invention is applied to the multiplier circuit of the intermediate frequency mixing circuit of the AM / FM receiver has been described. However, the present invention is not limited to this and can be applied to other circuits. The present invention is not limited to the case of multiplying the local oscillation signal and the received signal as in the second embodiment, but can be applied to a circuit that multiplies any two signals or an amplifier circuit other than the multiplier circuit.
[0037]
【The invention's effect】
According to the present invention, in the MOS integrated circuit, the gain of the amplifier circuit can be increased and a wide dynamic range can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an amplifier circuit according to a first embodiment.
FIG. 2 is a circuit of an intermediate frequency mixing circuit according to a second embodiment.
[Explanation of symbols]
11-13 n-channel MOS transistors 21-28 n-channel MOS transistor 29 tuning coil 31 ceramic filter

Claims (7)

A first MOS transistor having a first gate oxide film;
A second MOS transistor in cascode connection with the first MOS transistor;
A second gate oxide film thinner than the first gate oxide film is formed in the second MOS transistor so that the gain of the second MOS transistor is larger than that of the first MOS transistor. MOS integrated circuit. 2. The MOS integrated circuit according to claim 1, wherein the first gate oxide film and the second gate oxide film are formed by different processes. A first signal and an inverted signal of the first signal are input to the respective gates, and first and second MOS transistors whose sources are connected to each other;
A third MOS transistor and a fourth MOS transistor in which the first signal and the inverted signal of the first signal are input to the respective gates and the sources are connected to each other;
A fifth MOS transistor in which a source and a drain of the first and second MOS transistors are connected and a second signal is input to a gate;
A sixth MOS transistor having a source and a drain connected to each of the third and fourth MOS transistors and a signal obtained by inverting the second signal input to the gate;
The oxide films of the fifth and sixth MOS transistors are made the first to fourth MOS transistors so that the gains of the fifth and sixth MOS transistors are larger than those of the first to fourth MOS transistors. MOS integrated circuit thinner than the oxide film. The difference voltage between the drain voltage of the first MOS transistor and the drain voltage of the third MOS transistor, and the difference voltage of the drain voltage of the second MOS transistor and the drain voltage of the fourth MOS transistor are the same externally. 4. The MOS integrated circuit according to claim 3, wherein the MOS integrated circuit outputs to an output terminal. A seventh MOS transistor in which the source and drain of the fifth and sixth MOS transistors are connected; an eighth MOS transistor in which the gate is connected in common to the seventh MOS transistor and a constant current flows through the drain; 4. The MOS integrated circuit according to claim 3, comprising: 6. The MOS integrated circuit according to claim 3, 4 or 5, wherein the first signal is a local oscillation signal for generating an intermediate frequency signal, and the second signal is a broadcast signal reception signal. Forming a first gate oxide film on the first MOS transistor;
The second MOS transistor cascode-connected to the first MOS transistor has a second MOS transistor thinner than the first gate oxide film so that the gain of the second MOS transistor is larger than that of the first MOS transistor. And a process for forming a gate oxide film.

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