JP2005027029A - Variable length frame buffer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the processing time to retrieve the buffer amount not higher than a certain threshold in a frame unit at the time of buffering variable length frame data to notify a transmittable burst data amount in a frame unit. <P>SOLUTION: A buffer 3 for a frame number for storing the frame number is provided in the same address space as that of a frame buffer 1 for storing variable length frame data, and a frame division retrieving and controlling part 7 gives the value obtained by adding a threshold 31 existing in a read next first address 26 of the frame buffer 1 as a read address 32 to the buffer 3 for a frame number to acquire a frame number 33, retrieves a first address 23 to be a frame division from a memory 2 for buffer information with the frame number 33 as a read address 34, and outputs the buffer amount between the retrieved first address 23 and the next first address 26 as the buffer amount notification to a buffer amount notification request 30. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a variable-length frame buffer device that buffers variable-length frame data and notifies the amount of burst data that can be transmitted in units of frames.
[0002]
[Prior art]
In, for example, a PON (Passive Optical Network) system that employs a 1-to-N connection communication mode, a parent station that is one side performs communication by allowing a N-side child station to transmit to the parent station. At this time, the slave station notifies the master station of the amount of burst data that can be transmitted so that highly efficient communication can be performed. Further, for example, Non-Patent Document 1 discloses a method of performing communication with low delay and high efficiency by notification of an upper limit buffer amount.
[0003]
By the way, for example, in Ethernet (registered trademark) or the like, burst data is composed of a plurality of variable-length frames. Therefore, if the frame is not conscious, a blank time occurs. Therefore, in transmission of variable-length frames, if the amount of burst data that can be transmitted can be notified in units of frames, it is possible to eliminate the blank time and perform highly efficient communication.
[0004]
[Non-Patent Document 1]
"GE-PON Grant / Request Method Realizing High Efficiency and Low Delay" (2002, IEICE General Conference B-8-44, pages 414)
[0005]
[Problems to be solved by the invention]
However, when the amount of burst data that can be transmitted is notified in units of frames, a buffer amount that is equal to or less than a certain threshold is searched for in units of frames. In a system that employs a communication mode in which notification is made and the transmission time is determined, an increase in delay and a decrease in throughput are caused. Therefore, it is necessary that the search can be performed in a short time and the search time is always constant, but how to achieve this is a problem.
[0006]
The present invention has been made in view of the above. When buffering variable-length frame data and notifying the amount of burst data that can be transmitted in units of frames, a process for searching for the amount of buffers below a certain threshold in units of frames. It is an object of the present invention to obtain a variable-length frame buffer device capable of reducing time.
[0007]
[Means for Solving the Problems]
To achieve the above object, a variable-length frame buffer device according to the present invention stores a frame buffer that stores variable-length frame data in the order of input and a frame number that is incremented by one for each input frame as an address. In response to a buffer amount notification request from the outside, a buffer information memory for storing a head address and a frame length, a frame number buffer having the same address space as the frame buffer and storing the frame number, A frame number is obtained by giving a value obtained by adding a threshold value in the next read start address of the frame buffer to the frame number buffer as a read address, and a frame is separated from the buffer information memory using the read number as a read address. Search for the start address and The buffer amount between the retrieved head address and the next leading address, characterized in that it comprises a buffer volume retrieving means for outputting as a buffer amount notification to the buffer amount notification request.
[0008]
According to the present invention, since the frame number buffer for storing the frame number is provided in the same address space as the frame buffer for storing the variable-length frame data, the buffer amount search means is at the read next start address of the frame buffer. A value obtained by adding a threshold value to the frame number buffer as a read address is obtained to obtain a frame number, and the read address is used as a read address to search for a head address that is a frame delimiter from the buffer information memory. Only the addition and two memory accesses can retrieve the buffer amount in units of frames.
[0009]
When a gap is provided between the frames, write control means for controlling writing to the frame buffer, the buffer information memory, and the frame number buffer stores variable length frame data in the frame buffer. In this case, it is possible to control the writing including the data corresponding to the inter-frame gap and simultaneously control the writing of the frame number in the area corresponding to the inter-frame gap in the frame number buffer. It is also possible to cope with communication forms that require
[0010]
Also, when a gap is provided between frames, a deviation adjusting means is provided at the input stage of the write control means, and the operation clock of the variable length frame data to be input is set to an early clock considering the clock deviation existing between the devices. By converting and operating the write control means with the converted fast clock, if there is a clock deviation between the devices, the clock deviation can be adjusted.
[0011]
On the other hand, when the communication permission time is given, the buffer amount search means gives the frame number buffer as a read address a value obtained by adding the communication permission time to the next read start address of the frame buffer as a read address. About the remaining buffer amount obtained by retrieving the buffer amount in frame units that can be transmitted in the communication permission time from the buffer information memory using the obtained read address as a read address, and subtracting the retrieved buffer unit in frame units that can be transmitted Since the frame-by-frame search described above can be performed a plurality of times, it is possible to notify a buffer amount closer to the actual buffer amount. Therefore, since the side that gives the communication permission time can know the almost accurate buffer amount, some band control can be performed.
[0012]
In addition, a buffer amount search across the plurality of variable length frame buffer devices is realized by controlling the buffer amount search means provided in each of the plurality of variable length frame buffer devices in association with each other. can do.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a variable-length frame buffer device according to the present invention will be explained below in detail with reference to the accompanying drawings.
[0014]
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a variable-length frame buffer device according to Embodiment 1 of the present invention. The variable-length frame buffer apparatus shown in FIG. 1 holds a frame buffer 1 that holds frame data, and a “start address and frame length” of the frame data held in the frame buffer 1 using the frame number as a write / read address. A buffer information memory (2 port memory) 2, a frame number buffer (2 port memory) 3 having the same address space as the frame buffer 1 and storing a frame number to be counted up for each input frame, a write control unit 4, , A read control unit 5, an actual buffer amount management unit 6, a frame segmentation search control unit 7, and a selector 8.
[0015]
Each of the frame buffer 1, the buffer information memory 2, and the frame number buffer 3 is a 2-port memory, and can perform writing and reading with the same address value.
[0016]
The write control unit 4 controls writing to the frame buffer 1, the buffer information memory 2, and the frame number buffer 3. In addition to the input frame data 14, an input frame data valid signal 15 indicating that the input frame data 14 is valid is also input to the write control unit 4 from the outside.
[0017]
The read control unit 5 gives a frame number (address) 22 to the buffer information memory 2 via the selector 8 in response to the output permission signal 21 from the outside, and “start address + frame length” from the buffer information memory 2. 23 is read out. Then, the frame data given to and held in the frame buffer 1 as a read address 11 is read out, and an output frame enable signal 25 indicating that the output packet data (frame data) 24 and the output packet data 24 are valid outside. And control to output. At this time, the read control unit 5 outputs the next head address 26 to the frame segmentation search control unit 7.
[0018]
The actual buffer amount management unit 6 manages the actual buffer amount from the write address 10 and the read address 11 for the frame buffer 1, and outputs a write inhibit signal 12 to the write control unit 4. On the other hand, the frame data presence / absence information 13 is output.
[0019]
The frame delimiter search control unit 7 receives a buffer amount notification request 30 from the outside, and reads out a value including a value obtained by adding the next head address 26 from the read control unit 5 and a preset buffer amount notification amount threshold 31. The address 32 is given to the frame number buffer 3, and the read frame number 33 is further given as the frame number (address) 34 to the buffer information memory 2 via the selector 8. The “frame length” ”35 is read, a frame unit break that does not exceed a certain threshold is searched, and a buffer amount notification 36 is output to the outside as a response to the buffer amount notification request 30.
[0020]
At this time, the frame segmentation search control unit 7 also performs selection control of the selector 8 by giving a selection signal 20 to the selector 8. In other words, the frame delimiter search control unit 7 selects the search control unit 7 for the frame delimiter 8 only when the selection signal 20 given to the selector 8 is received for a short period when the buffer amount notification request 8 is received from the outside. In other normal periods, the read control unit 5 is selected.
[0021]
Next, the operation will be described. First, the buffering operation to the frame memory 1 will be described with reference to FIG. When the input frame data 14 is input together with the input frame data valid signal 15, the write control unit 4 first outputs the write address 10 to the frame buffer 1, and the write inhibit signal 12 from the actual buffer amount management unit 6. Determine the contents of The actual buffer amount management unit 6 determines whether or not there is a writable area from the write address 10 to the frame buffer 1. The write control unit 4 writes the input frame data 14 to the frame buffer 1 when the content of the write prohibition signal 12 from the actual buffer amount management unit 6 indicates that writing is possible.
[0022]
The write control unit 4 uses the frame number 16 as a write address, and writes the “head address” and “frame length” 17 of the frame data 14 that has been written to the frame buffer 1 to the buffer information memory 2. The frame number 16 is a counter value starting from 0, and is incremented by “+1” after the writing to the buffer information memory 2 is completed. The frame length 17 is a value obtained by counting the length of the input frame data valid signal 15.
[0023]
At this time, when writing to the buffer information memory 2 is completed, the write control unit 4 notifies the frame delimiter search control unit 7 of the value of “start address + frame length” as the end address 19 in parallel. I am doing so. The end address 19 may be a value holding the next write address 10.
[0024]
Further, when writing the input frame data 14 to the frame buffer 1, the write control unit 4 writes the frame number 16 as data 18 in the frame number buffer 3 using the same write address 10.
[0025]
On the other hand, the read control unit 5 uses the output permission signal 21 as a trigger, and gives the frame number 22 “+1” every time frame data is output to the buffer information memory 2 via the selector 8 as a read address. The information (“start address” and “frame length”) 23 of the start frame of the frame buffer 1 is read from the memory 2. Then, the information (start address + frame length) 23 is given to the frame buffer 1 as a read address 11, and the contents of the frame presence / absence information 13 from the actual buffer amount management unit 6 are determined. The actual buffer amount management unit 6 determines the presence / absence of frame data from the read address 11 to the frame buffer 1.
[0026]
When the content of the frame presence / absence information 13 from the actual buffer amount management unit 6 is “present”, the read control unit 5 reads the frame data 24 from the frame buffer 1 and outputs it to the outside together with the output frame enable signal 25. The read control unit 5 does not perform the above operation when the frame presence / absence information 13 from the actual buffer amount management unit 7 indicates that the frame buffer 1 is “empty”.
[0027]
At this time, the read control unit 5 calculates the next start address 26 (“start address” + “frame length”) from the ““ start address ”and“ frame length ”23 obtained at the time of output, and performs frame segment search control. Part 7 is notified. This next head address may be a value holding the next read address 11.
[0028]
Next, the buffer amount notification operation for each frame will be described. Here, in order to clarify the significance of the existence of the frame number buffer 3, a case where the frame number buffer 3 is not present (FIG. 3) will be described in addition to the case where the frame number buffer 3 is present (FIG. 2). . In the case where there is no frame number buffer 3 in FIG. 1, the read control unit 5 gives the frame delimiter search control unit 7 with the first frame number 27 indicated by a broken line. It is assumed that the buffer amount notification request 30 and the output permission signal 21 are not input simultaneously.
[0029]
FIG. 2 shows an example of the state of the frame buffer 1, the buffer information memory 2, and the frame number buffer 3 when the input frame data 14 is written and the output packet data (frame data) 24 is read a plurality of times. Has been. Similarly, FIG. 3 shows an example of the state of the frame buffer 1 and the buffer information memory 2 when the input frame data 14 is written and the output packet data (frame data) 24 is read a plurality of times. Yes.
[0030]
With reference to FIG. 1, the buffer amount notification operation for each frame when the frame number buffer 3 is present will be described with reference to FIG. In the frame delimiter search control unit 7, a buffer amount notification amount threshold 31 is set in advance. When the buffer amount notification request 30 is input, the frame delimiter search control unit 7 uses a value obtained by adding “buffer amount notification amount threshold 31” to “next head address 26” indicated by the read control unit 5 for the frame number. The frame number 33 is read from the frame number buffer 3 with the read address 32 given to the buffer 3. Thereafter, the selection signal 20 is used to cause the selector 8 to select the search control unit 7 by dividing the frame, and the read frame number 33 is set as the frame number 34 as the read address to be given to the buffer information memory 2 via the selector 8. “Start address AD3 + frame length LEN3” 35 is read from the information memory 2.
[0031]
As a result, the notification buffer amount 38 is determined as “start address AD3−next start address 26”, and is output as a buffer amount notification 36 for each frame. If (tail address 19) − (next head address 26) <(buffer amount notification amount threshold 31), the value of (tail address 19) − (next head address 26) is set in units of frames without searching. The notification buffer amount of the buffer amount notification 36 is used. As described above, when the frame number buffer 3 is provided, it is possible to retrieve the buffer amount in units of frames by only one addition and two memory accesses.
[0032]
Next, referring to FIG. 1, the buffer amount notification operation for each frame when the frame number buffer 3 is not provided will be described with reference to FIG. When the buffer amount notification request 30 is input, the frame delimiter search control unit 7 causes the selector 8 to select the frame delimiter search control unit 7 using the selection signal 20. Then, the start frame number 27 from the read control unit 5 is set as a read address (frame number 34) to be given to the buffer information memory 2 via the selector 8, and the “start address AD0” and “frame length LEN0” are read from the buffer information memory 2. "" 35 is read, and the size relationship between the read frame length LEN0 and the buffer amount notification amount threshold 31 is compared.
[0033]
As a result, when the frame length LEN0 is small, a read address (frame number 34) obtained by incrementing the frame number is given, and “head address AD1” and “frame length LEN1” ”35 are read from the buffer information memory 2 again. The magnitude relationship between the value obtained by adding the frame length LEN1 read this time to the previously read frame length LEN0 and the buffer amount notification amount threshold value 31 is compared.
[0034]
When “LEN0 + LEN1” is smaller, a read address (frame number 34) obtained by adding the frame number to +1 is given again, and “head address AD2” and “frame length LEN2” 35 are again set from the buffer information memory 2. Since “LEN0 + LEN1 + LEN2” <(buffer amount notification amount threshold 31) again, ““ start address AD3 ”and“ frame length LEN3 ”” 35 are read again.
[0035]
In this example, when “LEN0 + LEN1 + LEN2 + LEN3”> (buffer amount notification amount threshold 64), the notification buffer amount 38 is determined as (start address AD3) − (next start address) and notified as a buffer amount in units of frames. Will be. If (end address 19) − (next head address 26) <(buffer amount notification amount threshold 31), the search is not performed as described with reference to FIG. 2, but (end address 19) − (next head address 26). ) As a buffer amount.
[0036]
In the example shown in FIG. 3, the buffer information memory 2 is accessed four times in order to notify the buffer amount in units of frames. However, in actuality, there is a possibility that it takes time to access the buffer information memory 2 several hundred to several tens of thousands of times depending on the size of the buffer amount notification amount threshold 31 and the number of frames in the frame buffer 1. Further, a processing time is required in which the frame length is added and compared each time the “head address” and “frame length” 23 are read from the buffer information memory 2.
[0037]
Therefore, when there is no frame number buffer 3, it takes a huge amount of processing time to search and notify the buffer amount below a certain threshold in units of frames. In a system that employs a form in which communication is given for a long time, an increase in the search time causes an increase in delay and a decrease in throughput. On the other hand, when the frame number buffer 3 exists, as described above, it is possible to search the buffer amount in units of frames by one addition and two memory accesses, and the delay becomes extremely small. .
[0038]
If the frame number buffer 3 is not provided, the number of accesses to the memory may not be constant depending on the number of frames stored in the frame buffer 1. On the other hand, when the frame number buffer 3 is present, it is possible to retrieve the buffer amount in units of frames in a fixed time.
[0039]
Therefore, by providing the frame number buffer 3, in a system that communicates by giving the transmission buffer amount and is given the transmission time, the real time permitted to notify the transmittable buffer amount Can be sent within.
[0040]
Embodiment 2. FIG.
FIG. 4 is a block diagram showing a configuration of a variable length frame buffer device according to the second embodiment of the present invention. In the first embodiment described above, the case where the actual number of bytes of a frame is stored in the frame buffer 1 and the frame number buffer 3 has been described. However, there is a system that employs a communication mode in which a gap (IPG: Inter Packet Gap) is provided between frames to be transmitted and received, for example, Ethernet (registered trademark).
[0041]
That is, the second embodiment shows a configuration example of a variable-length frame buffer device that can transmit within the real time in which notification of the amount of buffer that can be transmitted is allowed, taking IPG time into consideration.
[0042]
The IPG is, for example, about 12 bytes in the Ethernet (registered trademark). However, since this IPG needs to be written and read simultaneously, the variable-length frame buffer device shown in FIG. 4 has the configuration shown in FIG. A write control unit 40 is provided instead of the write control unit 4, and a read control unit 41 is provided instead of the read control unit 5. Note that the end address 42 is used instead of the end address 19. Others are the same as or equivalent to the configuration shown in FIG.
[0043]
Next, the operation will be described. First, the buffering operation to the frame memory 1 will be described with reference to FIG. In FIG. 4, the write control unit 40 first sets the data 18 as the frame number 16 to “0” at the start of operation (for example, after power-on or reset), and sets the write address 10 “ Data (frame number “0”) 18 for IPG (for example, 12 bytes) is written in order from address 0 ”, and a standby state is entered. At this time, the write control unit 40 holds the start address of the IPG as the start address of the frame.
[0044]
Thereafter, when the input frame data 14 is input together with the input frame data valid signal 15, the write control unit 40 issues a write address 10 and the frame buffer 1 is received by the write prohibit signal 12 from the actual buffer amount management unit 6. It is determined whether writing is possible. If writing is possible, the input frame data 114 is written to the frame buffer 1 following the IPG area. At the same time, the data 18 having the frame number “0” is written in the same address space in the frame number buffer 3.
[0045]
After the data for one frame is stored in the frame number buffer 3 and the frame buffer 1 in this way, “the head address held and the frame length obtained by counting the length of the input frame data valid signal 15” 17 is set as the frame number. (In this case, “0”) 16 is written in the buffer information memory 2 as an address. After the writing to the buffer information memory 2 is completed, the frame number 16 is incremented by one. In parallel, the value of “start address + IPG + frame length” is notified as the end address 42 to the frame segmentation search control unit 7. The end address may be a value holding the next write address 10.
[0046]
Further, the write control unit 40 adds only the frame number (data 18) which is incremented by 1 to “1” until the next frame arrives, and continues to the frame number address, and only the frame number buffer 3 for IPG. Will be in a standby state. The write control unit 40 repeats the above operation.
[0047]
On the other hand, the read control unit 41 uses the output permission signal 4 as a trigger, and gives the frame number 22 incremented by 1 every time a frame is output to the buffer information memory 2 via the selector 8 as a read address, and the buffer information memory 2 Information (“start address” and “frame length”) 23 of the first frame of the frame buffer 1 is read out. Then, the information (only “first address”) is given to the frame buffer 1 as a read address 11, and the contents of the frame presence / absence information 13 from the actual buffer amount management unit 6 are determined. The actual buffer amount management unit 6 determines the presence / absence of frame data from the read address 11 to the frame buffer 1.
[0048]
The read control unit 41 reads the frame data 24 from the frame buffer 1 when the content of the frame presence / absence information 13 from the actual buffer amount management unit 6 is “present”, and outputs the output packet data (frame data) 24 and the output frame enable. The signal 25 is output to the outside. At this time, since the head address is the head of the IPG, the frame data 24 corresponding to the frame length is read from the address obtained by adding the IPG addresses. The read control unit 41 does not perform the above operation when the frame presence / absence information 13 from the actual buffer amount management unit 7 indicates that the frame buffer 1 is “empty”.
[0049]
At this time, the read control unit 41 calculates the next start address 26 using “start address + IPG + frame length” obtained at the time of output, and notifies the frame delimiter search control unit 7 of it. The next head address may be a value holding the next read address.
[0050]
Next, the buffer amount notification operation in units of frames will be described along FIG. 5 with reference to FIG. FIG. 5 is a diagram for explaining a buffer amount search operation for each frame performed in the variable-length frame buffer device shown in FIG.
[0051]
FIG. 5 shows an example of the state of the frame buffer 1, the buffer information memory 2, and the frame number buffer 3 when the above operation is repeated a plurality of times. As shown in FIG. 5, in the frame buffer 1, the IPG area 43 and the frame data area 44 are buffered alternately. Also, the frame number buffer 3 additionally stores the frame number for the IPG area 43.
[0052]
The buffer amount notification operation in units of frames according to the second embodiment is the same as that of the first embodiment except that the IPG area 43 is added. That is, it is possible to retrieve the buffer amount in units of frames by only one addition and two memory accesses.
[0053]
As described above, according to the second embodiment, the IPG can be simultaneously written and read, and the notification of the buffer amount that can be transmitted can be transmitted within the permitted real time in consideration of the IPG time. In addition to a communication mode that does not require IPG, an effective operation is possible even in a communication mode that requires IPG.
[0054]
Embodiment 3 FIG.
FIG. 6 is a block diagram showing the configuration of the variable-length frame buffer device according to the third embodiment of the present invention. In FIG. 6, the same reference numerals are given to components that are the same as or equivalent to the configuration illustrated in FIG. 4. Here, the description will be focused on the portion related to the third embodiment.
[0055]
In this third embodiment, there is shown a configuration example of a variable-length frame buffer device that can cope with a case where there is a deviation between operation clocks of frame data between devices in the communication mode that requires the IPG described in the second embodiment. Has been. That is, in the variable-length frame buffer device shown in FIG. 6, in the configuration shown in FIG. 4, a deviation adjusting unit 45 is provided at the input stage of the write control unit 40.
[0056]
For example, since the IPG may be less than a predetermined time, the deviation adjusting unit 45 inputs the write control unit 40 in order to secure time for writing the frame number in the IPG area of the frame number buffer 3. The operation is performed with a clock that is faster than the operation clock of the frame data 14 by a deviation DV or more, that is, the input frame data 14 is changed to a slightly faster clock and is written to the frame buffer 1 for adjustment.
[0057]
Therefore, the deviation adjusting unit 45 is configured by a FIFO (First in first out) buffer in which an input clock and an output clock are separately provided. When one or more frames are written, the deviation adjusting unit 45 performs an operation of reading one frame at a time according to the IPG interval. ing. The size of the FIFO buffer is not less than the maximum length of one frame so that the frame is not discarded.
[0058]
The operation of the variable-length frame buffer device according to the third embodiment is the same as that of the second embodiment except that the write control unit 40 operates with the same clock as the output clock of the deviation adjustment unit 45.
[0059]
That is, according to the third embodiment, in the communication mode that requires the IPG described in the second embodiment, there is no problem even when there is a deviation between the devices in the operation clock of the input frame data. Since it is possible to secure time for writing the frame number in the IPG area of the buffer 3, the same effects as those of the second embodiment can be obtained.
[0060]
Embodiment 4 FIG.
FIG. 7 is a block diagram showing a configuration of a variable-length frame buffer device according to the fourth embodiment of the present invention. In FIG. 7, the same reference numerals are given to components that are the same as or equivalent to the configuration illustrated in FIG. 4. Here, the description will be focused on the portion related to the fourth embodiment.
[0061]
In the fourth embodiment, a configuration example corresponding to the case where it is necessary to search for the buffer amount in units of frames a plurality of times is shown. That is, in the variable-length frame buffer device shown in FIG. 7, in the configuration shown in FIG. 4, a frame break search control unit 70 is provided instead of the frame break search control unit 7. The frame delimiter search control unit 70 is input with a communication permission time 73, and a plurality of buffer amount notification amount threshold values 71 (for example, A and B) are set. The case of performing by value is shown.
[0062]
In the frame delimiter search control unit 70, when a certain communication permission time 73 is given, the buffer amount search for each frame is performed a plurality of times as follows. That is, when a certain communication permission time 73 is given, the frame delimitation search control unit 70 searches for the buffer amount in units of frames that can be transmitted in the communication permission time 73, and then the frame units that could be transmitted. The remaining buffer amount after subtracting the buffer amount is notified of the buffer amount in frame units at a certain threshold. At this time, the notification of the buffer amount for each frame may be two or more.
[0063]
Next, referring to FIG. 7, the operation in the case where the buffer amount search for each frame is performed a plurality of times will be described along FIG. FIG. 8 is a diagram for explaining a buffer amount search operation for each frame performed in the variable length frame buffer device shown in FIG. FIG. 8 shows a case where the frame segmentation search control unit 70 performs three searches.
[0064]
In FIG. 8, first, in a first search, when a certain communication permission time 73 is given, a value obtained by adding the communication permission time 73 to the next head address 26 from the read control unit 41 is set as a read address 32. The frame number 33 is given to the number buffer 3 and the frame number 33 is read from the frame number buffer 3. This is {circle around (1)} shown in FIG. 8 and designates the read address “2” of the buffer information memory 2. Then, the start address AD2 is read from the buffer information memory 2 by the frame number ((1) shown in FIG. 8) 33, and is successively held as the start address AD2 (first search result 84).
[0065]
In the second search, a value obtained by adding the buffer amount notification amount threshold value A81 to the first head address AD2 as the first search result 84 is given to the frame number buffer 3 as a read address, and the frame number 33 from the frame number buffer 3 is supplied. Is read. This is {circle around (2)} shown in FIG. 8 and designates the read address “4” of the buffer information memory 2. Then, the head address AD4 is read from the buffer information memory 2 by the frame number ((2) shown in FIG. 8) 33, and the notification buffer amount A85 is obtained as “(start address AD4) − (next start address AD2)”. .
[0066]
In the third search, a value obtained by adding the buffer amount notification amount threshold value B82 to the first head address AD2 as the first search result 84 is given to the frame number buffer 3 as a read address, and the frame number 33 from the frame number buffer 3 is supplied. Is read. This is {circle around (3)} shown in FIG. 8 and designates the read address “5” of the buffer information memory 2. The head address AD5 is read from the buffer information memory 2 by the frame number ([3] shown in FIG. 8) 33, and the notification buffer amount B86 is obtained as (head address AD5)-(next head address AD2). As a result, the notification buffer amount A85 and the notification buffer amount B86 obtained by the above three searches are output as the buffer amount notification 72.
[0067]
As described above, according to the fourth embodiment, since the buffer amount search for each frame can be performed a plurality of times, the buffer amount in units of frames obtained by subtracting the data amount given the communication permission time is set to a plurality of buffers. It becomes possible to notify as a value of 2 or more using the amount notification amount threshold. Therefore, the following effects can be obtained.
[0068]
That is, when the communication permission time is given, the amount of data to be output at that time is subtracted, so that the notified buffer amount can be notified as a value closer to the actual buffer amount. In addition, since the buffer amount is notified by a plurality of buffer amount notification amount thresholds, for example, the transmission permission side can freely select when giving the next transmission permission time with reference to the notification amount, It becomes possible to perform some band control. In the fourth embodiment, the application example to the second embodiment has been described. Needless to say, the present invention can be similarly applied to the first and third embodiments.
[0069]
Embodiment 5 FIG.
FIG. 9 is a block diagram showing a configuration of a variable-length frame buffer device according to the fifth embodiment of the present invention. In the fifth embodiment, a configuration example of a variable-length frame buffer device that searches a buffer amount in units of frames across a plurality of variable-length frame buffer devices having the functions of the first to fourth embodiments is shown.
[0070]
The variable-length frame buffer device shown in FIG. 9 includes two variable-length frame buffer devices 101 and 102 and a search control unit 103 to simplify the description. The two variable-length frame buffer devices 101 and 102 have substantially the same configuration as the variable-length frame buffer device described in the first to fourth embodiments.
[0071]
That is, the two variable length frame buffer devices 101 and 102 respectively buffer the input frame data valid 1 and 2 and the input frame data 1 and 2, and output frame enable 1 in response to the output permission signals 1 and 2. , 2 and output frame data 1, 2 are output.
[0072]
In the two variable length frame buffer devices 101 and 102, one variable length frame buffer device 101 is a high priority buffer, and the other variable length frame buffer device 102 is a low priority buffer. High priority and low priority mean that data can be output from a low priority buffer only when there is no data in the high priority buffer.
[0073]
The search control unit 103 receives a buffer amount notification request 104 and a notification amount threshold 105 from the outside, and gives a buffer amount notification threshold 106 to the two variable length frame buffer devices 101 and 102. Then, the two variable-length frame buffer devices 101 and 102 output the actual buffer amounts 1 and 2 to the search control unit 103, respectively, and receive search commands 1 and 2 from the search control unit 103 to search the search control unit 103. Results 1 and 2 are output.
[0074]
Here, the correspondence with the items described in the first embodiment and the like is shown. The actual buffer amounts 1 and 2 correspond to “(tail address) − (next head address)”, the search instructions 1 and 2 correspond to the buffer amount notification request 30, and the search results 1 and 2 correspond to the buffer amount notification 36, 72. Then, the search control unit 103 performs a buffer amount search for each frame only once.
[0075]
Next, the operation of the variable-length frame buffer device according to the fifth embodiment will be described along FIG. 10 with reference to FIG. FIG. 10 is a flowchart for explaining the frame-unit buffer amount search operation performed by the variable-length frame buffer device shown in FIG.
[0076]
In FIG. 10, the search control unit 103 first enters a standby state until a buffer amount notification request 104 is input (step S101: No). When the buffer amount notification request 104 is input (step S101: Yes), for example, the magnitude relationship between a preset notification amount threshold 105 and “actual buffer amount 1 + actual buffer amount 2” is compared (step S102). When the notification amount threshold 105 is equal to or larger than “actual buffer amount 1 + actual buffer amount 2” (step S102: Yes), the output buffer amount notification 107 is “actual buffer amount 1 + actual buffer amount 2” (step S103). ).
[0077]
On the other hand, when the notification amount threshold 105 is smaller than “actual buffer amount 1 + actual buffer amount 2” (step S102: No), one of the notification amount threshold 105 and the actual buffer amounts 1 and 2 (here, the actual buffer 1) Are compared (step S104). As a result, when the notification amount threshold 105 <the actual buffer amount 1 (step S104: Yes), the buffer amount notification amount threshold 106 is set as the notification amount threshold 105 (step S105), and the search command 1 is issued (step S106). ). Then, the search result 1 obtained as a result is output as the buffer amount notification 107 (step S107).
[0078]
If the notification amount threshold value 105 ≧ the actual buffer amount 1 (step S104: No), the buffer amount notification amount threshold value 106 = the notification amount threshold value 105−the actual buffer amount 1 is set (step S108). ) And a search command 2 are issued (step S109). Then, using the search result 2 obtained as a result, the output buffer amount notification 107 is set to “actual buffer amount 1 + search result 2”.
[0079]
As described above, according to the fifth embodiment, it is possible to search the buffer amount in units of frames across a plurality of variable length frame buffer devices. Thereby, for example, it is possible to have a frame buffer device for each priority class, and to search the buffer amount in units of frames across a plurality of frame buffer devices according to the output order defined by the priority class.
[0080]
【The invention's effect】
As described above, according to the present invention, the frame number buffer for storing the frame number is provided in the same address space as the frame buffer for storing the variable-length frame data. The value obtained by adding the threshold value in the next read start address is given to the frame number buffer as a read address to obtain the frame number, and the read address is used as the read address to search for the start address that is a frame delimiter from the buffer information memory The buffer amount in units of frames can be searched with only one addition of “Yes” and two memory accesses. Therefore, when buffering variable-length frame data and notifying the amount of burst data that can be transmitted in units of frames, the processing time for searching for the amount of buffers below a certain threshold in units of frames can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a variable-length frame buffer device according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a frame-unit buffer amount search operation performed by the variable-length frame buffer device shown in FIG. 1 (when there is a frame number buffer).
3 is a diagram for explaining a frame-unit buffer amount search operation performed by the variable-length frame buffer device shown in FIG. 1 (when there is no frame number buffer); FIG.
FIG. 4 is a block diagram showing a configuration of a variable length frame buffer device according to a second embodiment of the present invention.
5 is a diagram for explaining a buffer amount search operation for each frame performed by the variable-length frame buffer device shown in FIG. 4; FIG.
FIG. 6 is a block diagram showing a configuration of a variable length frame buffer device according to a third embodiment of the present invention.
FIG. 7 is a block diagram showing a configuration of a variable length frame buffer device according to a fourth embodiment of the present invention.
8 is a diagram for explaining a buffer amount search operation in units of frames performed by the variable length frame buffer device shown in FIG. 7;
FIG. 9 is a block diagram showing a configuration of a variable length frame buffer device according to a fifth embodiment of the present invention.
10 is a flowchart illustrating a buffer amount search operation for each frame performed by the variable-length frame buffer device shown in FIG. 9. FIG.
[Explanation of symbols]
1 frame buffer (2 port memory), 2 buffer information memory (2 port memory), 3 frame number buffer (2 port memory), 4, 40 write control unit, 5, 41 read control unit, 6 real buffer amount management unit, 7 , 70 Frame delimited search control unit, 8 selector, 31 buffer amount notification amount threshold, 36 notification buffer amount, 45 deviation adjustment unit, 101 variable length frame buffer device (high priority), 102 variable length frame buffer device (low priority) 103 Search control unit.

Claims (5)

A frame buffer for storing variable-length frame data in the order of input;
A buffer information memory for storing a start address and a frame length when storing in the frame buffer with a frame number counted up by one for each input frame as an address;
A frame number buffer having the same address space as the frame buffer and storing the frame number;
In response to an external buffer amount notification request, a value obtained by adding a threshold value in the next read start address of the frame buffer is given as a read address to the frame number buffer to obtain a frame number, and the read number is used as the read address. Buffer amount search means for searching for a start address that is a frame delimiter from the buffer information memory and outputting the buffer amount between the searched start address and the next start address as a buffer amount notification for the buffer amount notification request When,
A variable-length frame buffer device comprising: Write control means for controlling writing to the frame buffer, the buffer information memory, and the frame number buffer, respectively. When a gap is required between frames, variable length frame data is stored in the frame buffer. And writing control means for controlling writing including data for the inter-frame gap and simultaneously writing the frame number in the region for the inter-frame gap in the frame number buffer. The variable-length frame buffer device according to claim 1. Provided at the input stage of the write control means, the operation clock of the input variable length frame data is converted into an early clock considering the clock deviation existing between the devices, and the write control means is operated with the converted early clock. The variable length frame buffer device according to claim 2, further comprising a deviation adjusting unit that performs the adjustment. When the communication permission time is given, the buffer amount search means obtains a frame number by giving a value obtained by adding the communication permission time to the read next start address of the frame buffer to the frame number buffer as a read address. A buffer amount in a frame unit that can be transmitted in the communication permission time is retrieved from the buffer information memory using the read address as a read address, and the remaining buffer amount is obtained by subtracting the retrieved buffer unit in a frame unit that can be transmitted. The variable length frame buffer device according to claim 1, wherein the search according to 1 is performed a plurality of times. A plurality of variable length frame buffer devices according to any one of claims 1 to 4;
Search control means for realizing buffer amount search in units of frames across the plurality of variable length frame buffer devices by controlling the buffer amount search means provided in each of the plurality of variable length frame buffer devices in association with each other. When,
A variable-length frame buffer device comprising:

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