JP2005020699A - Output circuit and semiconductor integrated circuit incorporating the same therein - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain high-speed operation with a simple circuit configuration in an output circuit which outputs a signal of a small amplitude. <P>SOLUTION: The output circuit for outputting an output signal having an amplitude smaller than a source voltage on the basis of a first drive signal is provided with: a first type MOS transistor QN10 in which the first driving signal is applied to its gate and which outputs a signal from its drain; a second type MOS transistor QP10 in which a second drive signal is applied to its gate and which outputs a signal from its drain; and feedback circuits 101 and 102 which generate the second drive signal by feeding an output signal resulting from combining the signal outputted by the MOS transistor QN10 and the signal outputted by the MOS transistor QP10 back to the gate of the MOS transistor QP10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an output circuit for outputting a signal to an external circuit, and further to a semiconductor integrated circuit incorporating such an output circuit.

  In recent years, interface signals have become very fast, and interface signal noise countermeasures and EMI (electromagnetic wave interference) countermeasures are required. As measures against noise and EMI, the amplitude of the interface signal is reduced. However, as described in Patent Document 1 below, when the signal amplitude is reduced by lowering the power supply voltage supplied to the output circuit, the power supply circuit becomes complicated. In addition, there is a possibility that the reference level of the signal does not match between the high power supply voltage system circuit and the low power supply voltage system circuit.

  Further, a differential signal may be used as the interface signal. FIG. 18 is a diagram illustrating an example of a conventional differential signal output circuit. A differential signal output circuit 81 shown in FIG. 18 is a circuit that outputs a first output signal J4 and a second output signal J4 bar as a pair of differential signals based on one input signal J1. However, in the differential signal output circuit 81, the drive signal J3 is delayed from the drive signal J2 by the delay time of the inverter INV82. Therefore, the first output signal J4 and the second output signal J4 bar are skewed. Will have.

  A differential signal output circuit capable of reducing the skew as described above is also used. FIG. 19 is a diagram showing another example of a conventional differential signal output circuit. A differential signal output circuit 91 shown in FIG. 19 is a circuit that outputs a first output signal K4 and a second output signal K4 bar as a pair of differential signals based on one input signal K1. The interface signal output circuit 91 further includes a capacitor C91 as compared with the interface signal output circuit 81 (see FIG. 18), and the drive signal K2 is delayed by the capacitor C91 to skew the drive signals K2 and K3. This can reduce the skew of the first output signal K4 and the second output signal K4 bar.

However, in the interface signal output circuit 91, the capacitance required for reducing the skew of the first output signal K4 and the second output signal K4 bar and the capacitance of the capacitor C91 due to variations in the manufacturing process. The capacitance may not match. As a result, the yield may decrease, or product defects may occur at the customer site. In addition, it is necessary to tighten margins for fluctuations in power supply potential, temperature fluctuations, etc., which may reduce the yield.
JP-A-6-326591 (first page, FIG. 1)

  In view of the above, a first object of the present invention is to enable high-speed operation with a simple circuit configuration in an output circuit that outputs a signal with a small amplitude. A second object of the present invention is to prevent a decrease in yield and the like in a differential signal output circuit that outputs a pair of differential signals. The third object of the present invention is to provide a semiconductor integrated circuit incorporating such an output circuit.

  In order to solve the above problems, an output circuit according to a first aspect of the present invention is an output circuit for outputting an output signal having an amplitude smaller than a power supply voltage based on a first drive signal. A first type first MOS transistor that applies a first drive signal to the gate and outputs a signal from the drain; and a second type that applies a second drive signal to the gate and outputs a signal from the drain. By feeding back the output signal obtained by combining the second MOS transistor, the signal output from the first MOS transistor, and the signal output from the second MOS transistor to the gate of the second MOS transistor A feedback circuit for generating a second drive signal.

  Here, the feedback circuit is supplied from the passive element having the first terminal connected to the connection point between the drain of the first MOS transistor and the drain of the second MOS transistor, and the second terminal of the passive element. And a buffer circuit for buffering the signal.

  An output circuit according to a second aspect of the present invention is an output circuit for outputting an output signal having an amplitude smaller than a power supply voltage based on a first drive signal, the first drive signal being applied to a gate. Is applied, and a first type first MOS transistor that outputs a signal from the drain; a first type second MOS transistor that applies a second drive signal to the gate and outputs a signal from the source; The second drive signal is obtained by inverting the output signal obtained by combining the signal output from the first MOS transistor and the signal output from the second MOS transistor and feeding back to the gate of the second MOS transistor. And a feedback circuit for generating.

  Here, the feedback circuit is supplied from the passive element having the first terminal connected to the connection point between the drain of the first MOS transistor and the source of the second MOS transistor, and the second terminal of the passive element. An inverter that inverts the signal may be included.

  An output circuit according to a third aspect of the present invention configures a pair of differential signals having an amplitude smaller than the power supply voltage based on the first and second drive signals configuring the pair of differential signals. An output circuit for outputting first and second output signals, wherein a first drive signal is applied to the gate and a signal is output from the drain, and a first type first MOS transistor and a gate having a first drive signal. A second type second MOS transistor that outputs a signal from the drain when a drive signal of 3 is applied, and a signal output from the first MOS transistor and a signal output from the second MOS transistor. A first feedback circuit for generating a third drive signal by feeding back the first output signal obtained in this way to the gate of the second MOS transistor, and a signal from the drain when the second drive signal is applied to the gate. Out Output from the third MOS transistor of the first type, the fourth MOS transistor of the second type that applies the fourth drive signal to the gate and outputs the signal from the drain, and the third MOS transistor. A second feedback circuit for generating a fourth drive signal by feeding back a second output signal obtained by synthesizing the signal and a signal output from the fourth MOS transistor to the gate of the fourth MOS transistor; It comprises.

  An output circuit according to a fourth aspect of the present invention forms a pair of differential signals having an amplitude smaller than the power supply voltage based on the first and second drive signals forming the pair of differential signals. An output circuit for outputting first and second output signals, wherein a first drive signal is applied to the gate and a signal is output from the drain, and a first type first MOS transistor and a gate having a first drive signal. A first type second MOS transistor that outputs a signal from the source when a drive signal of 3 is applied, and a signal output from the first MOS transistor and a signal output from the second MOS transistor. A first feedback circuit for generating a third drive signal by inverting the first output signal obtained in this way and feeding it back to the gate of the second MOS transistor, and the second drive signal applied to the gate and the drain From Is output from the third MOS transistor of the first type that outputs the signal from the source by applying the fourth driving signal to the gate and outputting the signal from the source. The fourth output signal is generated by inverting the second output signal obtained by combining the signal to be output and the signal output from the fourth MOS transistor and feeding back to the gate of the fourth MOS transistor. And a second feedback circuit.

  The output circuit according to the third or fourth aspect of the present invention includes a first inverting circuit that inverts an input signal and outputs a first drive signal, and a second drive that inverts the first drive signal. A second inverting circuit that outputs a signal may be further included.

  The output circuit according to the fifth aspect of the present invention is configured to output the first and second output signals constituting the pair of differential signals based on the first and second drive signals constituting the pair of differential signals. First and second signal level conversion circuits that output first and second drive signals by converting the first and second drive signals into predetermined level signals, respectively, and a first signal level conversion circuit The first differential circuit that outputs a signal corresponding to the difference between the signal output from the second signal level conversion circuit and the signal output from the second signal level conversion circuit, the signal output from the second signal level conversion circuit, and the first signal A second differential circuit that outputs a signal corresponding to the difference from the signal output from the level conversion circuit, and a first output that generates the first output signal based on the signal output from the first differential circuit A second output signal based on a signal output from the signal generation circuit and the second differential circuit; ; And a second output signal generation circuit for generating.

  Here, the first or second signal level conversion circuit may include a single-ended sense amplifier, or the first or second differential circuit may include a current mirror type differential amplifier circuit. However, the first or second output signal generation circuit may include an inverter.

  Further, a first inversion circuit that inverts the input signal and outputs a first drive signal, and a second inversion circuit that inverts the first drive signal and outputs a second drive signal are further included. You may do it.

  In that case, the first and second inversion circuits operate by receiving power from the first and second power supply potentials, and the first and second signal level conversion circuits, the first and second differences, The dynamic circuit and the first and second output signal generation circuits may operate by receiving power supply from the first and third power supply potentials.

  Alternatively, the first and second inversion circuits operate with power supplied from the first and second power supply potentials, and the first and second signal level conversion circuits operate with the first and third power supply potentials. So that the first and second differential circuits and the first and second output signal generation circuits operate with power supplied from the first and fourth power supply potentials. Anyway.

  At this time, the third power supply potential may be higher than the second power supply potential, and the fourth power supply potential may be higher than the third power supply potential, or the third power supply potential may be set. May be lower than the second power supply potential, and the fourth power supply potential may be lower than the third power supply potential.

  Furthermore, a semiconductor integrated circuit according to the present invention incorporates any one of the signal output circuits described above.

  According to the first to fourth aspects of the present invention, in an output circuit that outputs a signal having a small amplitude, high-speed operation can be performed with a simple circuit configuration by applying negative feedback using a feedback circuit. Can do. According to the fifth aspect of the present invention, in a differential signal output circuit that outputs a pair of differential signals, it is possible to prevent a decrease in yield and the like. Further, in the pair of differential output signals obtained according to the fifth aspect of the present invention, the eye pattern shape can be maintained even if the power supply voltage, the operating temperature, or the process varies.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a diagram showing a configuration of an output circuit according to the first embodiment of the present invention. The output circuit 10 includes an N-channel transistor QN10 whose gate is supplied with a drive signal, a P-channel transistor QP10 connected in series to the transistor QN10, an output terminal and protection device 101 connected to the drains of the transistors QP10 and QN10, And a buffer circuit 102 to which an output signal of the output circuit 10 is supplied via the protection device 101. The buffer circuit 102 is composed of two stages of inverters connected in series.

The source of the transistor QP10 is connected to the power supply potential V _DD , and the source of the transistor QN10 is connected to the power supply potential V _SS (in this embodiment, the ground potential). The protection device 101 is an element for protecting the input of the buffer circuit 102 from static electricity applied to the output terminal. For example, a resistor is used as the protection device 101. The output signal of the output circuit 10 is supplied to the input of the buffer circuit 102 via the protection device 101, and the signal output from the buffer circuit 102 is supplied to the gate of the transistor QP10, thereby forming a self-feedback circuit. Yes.

FIG. 2 is a diagram showing a waveform of an output signal of the output circuit shown in FIG. When the drive signal is at a low level, the transistor QN10 is in an off state, and the potential of the output signal is approximately (V _DD −V _SS ) / 2 due to the self-feedback action. When the drive signal is at a high level, the transistor QN10 is turned on, the potential of the output signal is lowered to near the power supply potential V _SS. Therefore, the amplitude of the output signal is a half swing that is approximately half of the power supply voltage (V _DD −V _SS ). Furthermore, this output circuit can perform high-speed operation by the function of self-feedback.

In the present embodiment, the high level of the drive signal to the power supply potential V _DD, may be a low level of power supply potential V _SS. Alternatively, the high level of the drive signal may be set to a potential other than the power supply potential V _DD . In that case, the output circuit according to the present embodiment also has a function as a level shifter. Note that the output signal of the output circuit 10 may be obtained from the output of one of the inverters constituting the buffer circuit 102.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a diagram showing the configuration of the output circuit according to the second embodiment of the present invention. This output circuit includes a P-channel transistor QP10 whose gate is supplied with a drive signal, an N-channel transistor QN10 connected in series to the transistor QP10, an output terminal and a protection device 101 connected to the drains of the transistors QP10 and QN10, And a buffer circuit 102 to which an output signal of the output circuit is supplied via the protection device 101.

The source of the transistor QP10 is connected to the power supply potential V _DD , and the source of the transistor QN10 is connected to the power supply potential V _SS (in this embodiment, the ground potential). The output signal of this output circuit is supplied to the input of the buffer circuit 102 via the protection device 101, and the signal output from the buffer circuit 102 is supplied to the gate of the transistor QN10, thereby forming a self-feedback circuit. Yes.

FIG. 4 is a diagram showing a waveform of an output signal of the output circuit shown in FIG. When the drive signal is at a high level, the transistor QP10 is in an off state, and the potential of the output signal is approximately (V _DD −V _SS ) / 2 due to the self-feedback action. When the drive signal becomes a low level, the transistor QP10 is turned on, and the potential of the output signal rises to near the power supply potential V _DD . Therefore, the amplitude of the output signal is a half swing that is approximately half of the power supply voltage (V _DD −V _SS ). Furthermore, this output circuit can perform high-speed operation by the function of self-feedback.

In the present embodiment, the high level of the drive signal to the power supply potential V _DD, may be a low level of power supply potential V _SS. Alternatively, the low level of the drive signal may be a potential other than the power supply voltage V _SS to. In that case, the output circuit according to the present embodiment also has a function as a level shifter. Note that the output signal of the output circuit may be obtained from the output of one of the inverters constituting the buffer circuit 102.

Next, a third embodiment of the present invention will be described.
FIG. 5 is a diagram showing a configuration of an output circuit according to the third embodiment of the present invention. This output circuit includes an N-channel transistor QN10 whose gate is supplied with a drive signal, an N-channel transistor QN20 connected in series to the transistor QN10, an output terminal connected to the drain of the transistor QN10 and the source of the transistor QN20, and a protection device. 101 and an inverter 103 to which the output signal of the output circuit is supplied via the protection device 101.

The drain of the transistor QN20 is connected to the power supply potential V _DD , and the source of the transistor QN10 is connected to the power supply potential V _SS (in this embodiment, the ground potential). The output signal of this output circuit is supplied to the input of the inverter 103 via the protection device 101, and the signal output from the inverter 103 is supplied to the gate of the transistor QN20, thereby forming a self-feedback circuit.

When the drive signal is at a low level, the transistor QN10 is in an off state, and the potential of the output signal is approximately (V _DD −V _SS ) / 2 due to the self-feedback action. When the drive signal is at a high level, the transistor QN10 is turned on, the potential of the output signal is lowered to near the power supply potential V _SS. Therefore, the amplitude of the output signal is a half swing that is approximately half of the power supply voltage (V _DD −V _SS ). Furthermore, this output circuit can perform high-speed operation by the function of self-feedback.

In the present embodiment, the high level of the drive signal to the power supply potential V _DD, may be a low level of power supply potential V _SS. Alternatively, the high level of the drive signal may be set to a potential other than the power supply potential V _DD . In that case, the output circuit according to the present embodiment also has a function as a level shifter. Note that the output signal of the output circuit may be obtained from the output of the inverter 103.

Next, a fourth embodiment of the present invention will be described.
FIG. 6 is a diagram showing a configuration of an output circuit according to the fourth embodiment of the present invention. The output circuit includes a P-channel transistor QP10 whose gate is supplied with a drive signal, a P-channel transistor QP20 connected in series to the transistor QP10, an output terminal connected to the drain of the transistor QP10 and the source of the transistor QP20, and a protection device. 101 and an inverter 103 to which the output signal of the output circuit is supplied via the protection device 101.

The source of the transistor QP10 is connected to the power supply potential V _DD , and the drain of the transistor QP20 is connected to the power supply potential V _SS (in this embodiment, the ground potential). The output signal of this output circuit is supplied to the input of the inverter 103 via the protection device 101, and the signal output from the inverter 103 is supplied to the gate of the transistor QP20, thereby forming a self-feedback circuit.

When the drive signal is at a high level, the transistor QP10 is in an off state, and the potential of the output signal is approximately (V _DD −V _SS ) / 2 due to the self-feedback action. When the drive signal becomes a low level, the transistor QP10 is turned on, and the potential of the output signal rises to near the power supply potential V _DD . Therefore, the amplitude of the output signal is a half swing that is approximately half of the power supply voltage (V _DD −V _SS ). Furthermore, this output circuit can perform high-speed operation by the function of self-feedback.

In the present embodiment, the high level of the drive signal to the power supply potential V _DD, may be a low level of power supply potential V _SS. Alternatively, the low level of the drive signal may be a potential other than the power supply voltage V _SS to. In that case, the output circuit according to the present embodiment also has a function as a level shifter. Note that the output signal of the output circuit may be obtained from the output of the inverter 103.

Next, an embodiment in which the present invention is applied to a differential signal output circuit will be described below.
FIG. 7 is a diagram showing a configuration of an output circuit according to the fifth embodiment of the present invention. This differential signal output circuit is configured to input a differential signal and output a differential signal by using two output circuits having a single configuration described above.

The differential signal output circuit shown in FIG. 7 includes two output circuits 10 according to the first embodiment shown in FIG. The two output circuits 10 receive differential drive signals AI and AI bars and output differential output signals AO and AO bars. As a result, a half-swing differential signal that is approximately half of the power supply voltage (V _DD −V _SS ) can be output. Instead of the output circuit 10, any one of the output circuits according to the second to fourth embodiments shown in FIGS. 3, 5, and 6 may be used.

FIG. 8 is a diagram showing the configuration of the output circuit according to the sixth embodiment of the present invention. This differential signal output circuit inputs a single signal and outputs a differential signal.
The differential signal output circuit shown in FIG. 8 includes inverters 104 and 105 and two output circuits 10 according to the first embodiment shown in FIG. The inverter 104 inverts the input signal A1 to generate a drive signal A2, and the inverter 105 inverts the drive signal A2 to generate a drive signal A3.

The two output circuits 10 receive differential drive signals A2 and A3, and output differential output signals A4 and A5. As a result, a half-swing differential signal that is approximately half of the power supply voltage (V _DD −V _SS ) can be output. Instead of the output circuit 10, any one of the output circuits according to the second to fourth embodiments shown in FIGS. 3, 5, and 6 may be used.

FIG. 9 is a diagram showing a configuration of an output circuit according to the seventh embodiment of the present invention. The differential signal output circuit 1 is a circuit that outputs a first output signal A8 and a second output signal A8 bar as a pair of differential signals based on an input signal A1, and includes inverters INV1, INV2, INV7. , INV8, single-ended sense amplifiers 2 and 3, and current mirror type differential amplifier circuits 4 and 5. Each of these circuits operates by receiving supply of electric power by the power supply voltage V _SS of a power supply potential V _DD and the low potential side of the high potential side.

As shown in FIG. 9, an input signal A1 is supplied to the inverter INV1, and the inverter INV1 outputs a drive signal A2 obtained by inverting the input signal A1. In this embodiment, the input signal A1 and the drive signal A2 are between a low level (here, the low-potential-side power supply potential V _SS ) and a high level (here, the high-potential-side power supply potential V _DD ). It changes with.
The drive signal A2 is supplied to the inverter INV2, and the inverter INV2 outputs a drive signal A3 obtained by inverting the drive signal A2. In the present embodiment, the drive signal A3 changes between a low level and a high level.

  The single-ended sense amplifier 2 includes a P-channel transistor QP1, an N-channel transistor QN1, and inverters INV3 and INV4. This single-ended sense amplifier 2 has substantially the same configuration as the output circuit 10 shown in FIG. 1, and a signal A4 obtained by inverting the drive signal A2 and further converting it to a predetermined level is converted into a differential amplifier circuit 4 and 5 is supplied. As the single-end sense amplifier in this embodiment and the following embodiments, any one of the output circuits shown in FIGS. 3, 5, and 6 is used in addition to the output circuit 10 shown in FIG. be able to.

In single-ended sense amplifier 2, a source-drain path of the source-drain path of the transistor QN1 of the transistor QP1 is connected in series between power supply potential V _SS power supply potential V _DD and the low potential side of the high potential side The drive signal A2 is supplied to the gate of the transistor QN1. The connection point between the transistors QP1 and QN1 is connected to the input of the inverter INV3, and the output signal of the inverter INV3 is supplied to the inverter INV4.

  The output of the inverter INV4 is connected to the gate of the transistor QP1, and the transistor QP1 forms a negative feedback loop from the output of the inverter INV4 to the input of the inverter INV3. Therefore, the level of the signal A4 output from the inverter INV4 is a level corresponding to the gain of the feedback loop. The signal A4 output from the inverter INV4 is fed back to the gate of the transistor QP1 and supplied to the differential amplifier circuits 4 and 5.

  The single-ended sense amplifier 3 includes a P-channel transistor QP2, an N-channel transistor QN2, and inverters INV5 and INV6. The single-ended sense amplifier 3 supplies a signal A5 obtained by inverting the drive signal A3 and converting it to a predetermined level to the differential amplifier circuits 4 and 5.

  The transistors QP2 and QN2 and the inverters INV5 and INV6 in the single-ended sense amplifier 3 are connected in the same manner as the transistors QP1 and QN1 and the inverters INV3 and INV4 in the single-ended sense amplifier 2. As a result, the single-ended sense amplifier 3 The sense amplifier 3 has a circuit configuration similar to that of the single-ended sense amplifier 2.

  The differential amplifier circuit 4 includes P-channel transistors QP3 and QP4 and N-channel transistors QN3 to QN5, and supplies a signal A6 corresponding to the difference between the signal A4 and the signal A5 to the inverter INV8. Specifically, the signal A6 output from the differential amplifier circuit 4 is at a low level when the signal A4 is at a lower potential than the signal A5, and is at a high level when the signal A4 is at a higher potential than the signal A5.

The sources of the transistors QP3 and QP4 are supplied with the power supply potential V _DD on the high potential side, and the gate and drain of the transistor QP3 and the gate of the transistor QP4 are connected to each other. The drain of the transistor QN3 is connected to the drain and gate of the transistor QP3, and the signal A4 is supplied to the gate of the transistor QN3. The drain of the transistor QN4 is connected to the drain of the transistor QP4, and the signal A5 is supplied to the gate of the transistor QN4. The potential at the connection point between the drain of the transistor QN4 and the drain of the transistor QP4 is supplied as a signal A6 to the inverter INV8.

The source of the transistor QN5 is the power supply voltage _{V SS} of the low potential side is supplied, the drain of the transistor QN5 is connected to the source of the transistor QN3, QN4. The enable signal EN1 is supplied to the gate of the transistor QN5. When the enable signal EN1 is at a high level, the transistor QN5 is turned on and the differential amplifier circuit 4 operates.

  The differential amplifier circuit 5 includes P-channel transistors QP5 and QP6 and N-channel transistors QN6 to QN8, and supplies a signal A7 corresponding to the difference between the signal A5 and the signal A4 to the inverter INV7. Specifically, the signal A7 output from the differential amplifier circuit 5 is at a high level when the signal A4 is at a lower potential than the signal A5, and is at a low level when the signal A4 is at a higher potential than the signal A5.

  The transistors QP5 and QP6 and the transistors QN6 to QN8 in the differential amplifier circuit 5 are connected in the same manner as the transistors QP3 and QP4 and the transistors QN3 to QN5 in the differential amplifier circuit 4, and as a result, the differential amplifier circuit 5 Has a circuit configuration similar to that of the differential amplifier circuit 4.

  A signal A7 is supplied to the inverter INV7, and the inverter INV7 outputs a signal obtained by inverting the signal A7 as the first output signal A8. A signal A6 is supplied to the inverter INV8, and the inverter INV8 outputs a signal obtained by inverting the signal A8 as the second output signal A8 bar.

FIG. 10 is a timing chart showing the operation of the differential signal output circuit 1.
As shown in FIG. 10, the input signals A1 at time t ₀ is changed from low level to high level, the drive signal A2 inverter INV1 outputs, after a predetermined delay time, changes from a high level to a low level. When the drive signal A2 is changed from high level to low level, the signal A4 output from the single-ended sense amplifier 2, the first level is a higher potential than the power supply voltage V _SS of the low potential side, than the first level It changes to the second level which is a high potential and lower than the power supply potential V _DD on the high potential side.

  On the other hand, when the drive signal A2 changes from the high level to the low level, the drive signal A3 output from the inverter INV2 changes from the low level to the high level after a predetermined delay time. When the drive signal A3 changes from the low level to the high level, the signal A5 output from the single-ended sense amplifier 3 changes from the second level to the first level.

  At the initial time, the potential of the signal A4 is lower than the potential of the signal A5, the signal A7 output from the differential amplifier circuit 5 is at a high level, and the first output signal A8 output from the inverter INV7. Is at a low level. Further, the signal A6 output from the differential amplifier circuit 4 is at a low level, and the second output signal A8 bar output from the inverter INV8 is at a high level.

Then, the input signal A1 at time t ₀ as described above changes from a low level to a high level, the potential of the signal A4 becomes higher than the potential of the signal A5. As a result, the signal A7 changes from high level to low level, and the first output signal A8 changes from low level to high level. The signal A6 changes from low level to high level, and the second output signal A8 bar changes from high level to low level.

Then, the input signal A1 at time t ₁ is changes from a high level to a low level, the drive signal A2, after a predetermined delay time, changes from low level to high level. When the drive signal A2 changes from the low level to the high level, the signal A4 output from the single-ended sense amplifier 2 changes from the second level to the first level.

  On the other hand, when the drive signal A2 changes from low level to high level, the drive signal A3 output from the inverter INV2 changes from high level to low level after a predetermined delay time. When the drive signal A3 changes from the high level to the low level, the signal A5 output from the single-ended sense amplifier 3 changes from the first level to the second level.

  Accordingly, the potential of the signal A4 becomes lower than the potential of the signal A5, the signal A7 changes from low level to high level, and the first output signal A8 changes from high level to low level. The signal A6 changes from high level to low level, and the second output signal A8 bar changes from low level to high level.

  Here, since the differential amplifier circuits 4 and 5 output the signals A6 and A7 corresponding to the potential difference between the signals A4 and A5, no skew occurs between the signals A6 and A7. Therefore, there is no skew between the first output signal A8 and the second output signal A8 bar.

Note that the timing at which the signals A2 to A5 change may fluctuate due to variations in manufacturing processes, temperature fluctuations, fluctuations in power supply potential (here, V _DD or V _SS ), and the like. However, even in such a case, since the differential amplifier circuits 4 and 5 output the signals A6 and A7 corresponding to the potential difference between the signal A4 and the signal A5, the first output signal A8 and the second output Even if the timing at which the signal A8 bar changes may fluctuate back and forth, there will be no skew between the first output signal A8 and the second output signal A8 bar.

  As described above, according to the differential signal output circuit according to the present embodiment, a capacitor is not required unlike the conventional differential signal output circuit 91 (see FIG. 19), thereby preventing a decrease in yield and the like. be able to.

Next, an eighth embodiment of the present invention will be described. FIG. 11 is a diagram showing an output circuit according to the eighth embodiment of the present invention. The differential signal output circuit 11 is a circuit that outputs a first output signal B8 and a second output signal B8 bar as a pair of differential signals on the basis of the input signal B1, and includes inverters INV1, INV2, INV7. , INV8, single-ended sense amplifiers 12 and 13, and current mirror type differential amplifier circuits 14 and 15. Each of these circuits operates by receiving supply of electric power by the power supply voltage V _SS of a power supply potential V _DD and the low potential side of the high potential side.

When the differential signal output circuit 11 is compared with the differential signal output circuit 1 described above (see FIG. 9), the single-ended sense amplifier 2 in the differential signal output circuit 1 is a signal A4 having a phase opposite to that of the drive signal A2. The single-ended sense amplifier 3 outputs a signal A5 having a phase opposite to that of the drive signal A3, whereas the single-ended sense amplifier 12 in the differential signal output circuit 11 has a signal B4 having the same phase as the drive signal B2. And the single-ended sense amplifier 13 outputs a signal B5 having the same phase as that of the drive signal B3. The differential amplifier circuits 14 and 15 in the differential signal output circuit 11 have a circuit configuration that is reversed with respect to the power supply potentials V _DD and V _{SS with} respect to the differential amplifier circuits 4 and 5 in the differential signal output circuit 1. ing.

  Similar to the differential signal output circuit 1, the differential signal output circuit 11 can output the first output signal B8 and the second output signal B8 bar without skew, and the conventional interface signal output circuit. Since no capacitor is required unlike 91 (see FIG. 19), it is possible to prevent a decrease in yield and the like.

Next, a ninth embodiment of the present invention will be described. FIG. 12 is a diagram showing an output circuit according to the ninth embodiment of the present invention. The differential signal output circuit 21 is a circuit that outputs a first output signal C8 and a second output signal C8 bar as a pair of differential signals based on the input signal C1. The inverters INV1, INV2, INV7 , INV8, single-ended sense amplifiers 22 and 23, and current mirror type differential amplifier circuits 4 and 5. Each of these circuits operates by receiving supply of electric power by the power supply voltage V _SS of a power supply potential V _DD and the low potential side of the high potential side.

  The differential signal output circuit 21 is different from the previously described differential signal output circuit 11 (see FIG. 11) in the configuration of single-ended sense amplifiers 22 and 23. The single-ended sense amplifier 22 includes N-channel transistors QN21 and QN22 and inverters INV23 and INV24, and supplies a signal C4 obtained by inverting the drive signal C2 to the differential amplifier circuits 4 and 5.

Source ~ drain path of transistor QN21 and QN22 are connected in series between power supply potential _{V SS} power supply potential _{V DD} and the low potential side of the high potential side, the gate of the transistor QN22 is driving signal C2 is Have been supplied. A connection point between the transistors QN21 and QN22 is connected to an input of the inverter INV23.

  The output of the inverter INV23 is connected to the gate of the transistor QN21, and the transistor QN21 forms a negative feedback loop from the output to the input of the inverter INV23. Therefore, the level of the signal output from the inverter INV23 is a level corresponding to the gain of the feedback loop. The output signal of the inverter INV23 is also supplied to the inverter INV24, and the inverter INV24 supplies the signal C4 obtained by inverting the output signal of the inverter INV23 to the differential amplifier circuits 4 and 5.

  The single-ended sense amplifier 23 includes N-channel transistors QN23 and QN24 and inverters INV25 and INV26, and supplies a signal C5 obtained by inverting the drive signal C3 to the differential amplifier circuits 4 and 5. The transistors QN23 and QN24 and the inverters INV25 and INV26 in the single-ended sense amplifier 23 are connected in the same manner as the transistors QN21 and QN22 and the inverters INV23 and INV24 in the single-ended sense amplifier 22, and as a result, The sense amplifier 23 has a circuit configuration similar to that of the single-ended sense amplifier 22.

  Similar to the differential signal output circuit 11, the differential signal output circuit 21 can output the first output signal B8 and the second output signal B8 bar without skew, and the conventional differential signal output. Since a capacitor is not required unlike the circuit 91 (see FIG. 19), a decrease in yield can be prevented.

  Next, a tenth embodiment of the present invention will be described. FIG. 13 is a diagram showing an output circuit according to the tenth embodiment of the present invention. The differential signal output circuit 31 is a circuit that outputs a first output signal D8 and a second output signal D8 bar as a pair of differential signals based on the input signal D1, and includes inverters INV31, INV32, INV37. , INV 38, single-ended sense amplifiers 32 and 33, and current mirror type differential amplifier circuits 34 and 35.

  The single-ended sense amplifier 32 includes a P-channel transistor QP31, an N-channel transistor QN31, and inverters INV33 and INV34. The circuit configuration is the same as that of the sense amplifier 2. Similarly, the single-ended sense amplifier 33 includes a P-channel transistor QP32, an N-channel transistor QN32, and inverters INV35 and INV36. The single-end sense amplifier 33 includes a single-ended sense amplifier 33 in the signal output circuit 1 (see FIG. 9) described above. The circuit configuration is the same as that of the end sense amplifier 3.

  The differential amplifier circuit 34 includes P-channel transistors QP33 and QP34 and N-channel transistors QN33 to QN35, and the differential amplifier circuit 4 in the signal output circuit 1 (see FIG. 9) described above. Has the same circuit configuration. Similarly, the differential amplifier circuit 35 includes P-channel transistors QP35 and QP36 and N-channel transistors QN36 to QN38, and the differential amplifier circuit in the signal output circuit 1 (see FIG. 9) described above. 5 has the same circuit configuration.

In the differential signal output circuit 31, compared with the signal output circuit 1 described above (see FIG. 9), the inverters INV31 and INV32 have a high-potential-side power supply potential _VDD1 and a low-potential-side power supply potential V. It is supplied with power by the _SS, a single ended sense amplifier 32 and 33, the differential amplifier circuit 34 and 35, the inverter INV37 and INV 38, the power supply potential _{V DD2} and the low potential side of the high potential side and differs in that power is being supplied by the potential V _SS.

here,
V _DD2 > V _DD1 (1)
Then, the differential signal output circuit 31 has a function as a booster circuit. For example, the power supply potential _{V SS} 0V, if the power supply voltage _{V DD1} 1.8V, the power supply potential _{V DD2} and 2.5V, on the basis of the input signal D1 of 1.8V level, the 2.5V level first The output signal D8 and the second output signal D8 bar can be output.

Also,
V _DD1 > V _DD2 (2)
Then, the differential signal output circuit 31 has a function as a step-down circuit. For example, if the power supply potential V _SS is 0 V, the power supply potential V _DD2 is 1.8 V, and the power supply potential V _DD1 is 2.5 V, the first 1.8 V level signal is generated based on the 2.5 V level input signal D1. The output signal D8 and the second output signal D8 bar can be output.

  Next, an eleventh embodiment of the present invention will be described. FIG. 14 is a diagram showing an output circuit according to the eleventh embodiment of the present invention. The differential signal output circuit 41 is a circuit that outputs a first output signal E8 and a second output signal E8 bar as a pair of differential signals on the basis of the input signal E1, and inverters INV31, INV32, INV47. , INV48, single-ended sense amplifiers 32 and 33, and current mirror type differential amplifier circuits 44 and 45.

  The differential amplifier circuit 44 includes P-channel transistors QP43 and QP44 and N-channel transistors QN43 to QN45, and the differential amplifier circuit 4 in the differential signal output circuit 1 (see FIG. 9) described above. Has the same circuit configuration. Similarly, the differential amplifier circuit 45 includes P-channel transistors QP45 and QP46 and N-channel transistors QN46 to QN48. The differential amplifier 45 in the differential signal output circuit 1 (see FIG. 9) described above. The circuit configuration is the same as that of the amplifier circuit 5.

In the differential signal output circuit 41, as compared with the differential signal output circuit 1 (see FIG. 9) described above, the inverters INV31 and INV32 have a high-potential power supply potential _VDD1 and a low-potential power supply. It is powered by a potential V _SS, the single-ended sense amplifiers 32 and 33 are powered by the power supply voltage V _SS of a power supply potential V _DD2 and the low potential side of the high potential side, the differential amplifier the circuit 44 and 45, the inverters INV47 and INV48, is different in that power is being supplied by the power supply voltage _{V SS} of a power supply potential _{V DD3} and the low potential side of the high potential side.

here,
V _DD3 > V _DD2 > V _DD1 (3)
Then, the differential signal output circuit 41 has a function as a booster circuit. This differential signal output circuit 41 is different from the previously described differential signal output circuit 31 (see FIG. 13) in the potential difference between the input signal E1, the first output signal E8, and the second output signal E8 bar. This is particularly effective when is large.

For example, in the differential signal output circuit 31 (see FIG. 13) described above, the first output signal D8 and the second output signal D8 bar of 5V level are output based on the input signal D1 of 1.8V level. to the the 0V as the power supply voltage _{V SS} of the low potential side, the 1.8V as a power source potential _{V DD1} of the high potential side, it is necessary to supply the 5V as supply potential _{V DD2} of the high potential side. However, when such a power supply potential is supplied, the single-ended sense amplifiers 32 and 33 operating at a power supply potential of 5V will receive the drive signals D2 and D3 of 1.8V level and perform a desired operation. Is difficult.

On the other hand, in the differential signal output circuit 41, 0V is set as the power supply potential V _SS on the low potential side, 1.8V is set as the power supply potential V _DD1 on the high potential side, 3.3V is set as the power supply potential V _DD2 , and the power supply potential V _If 5V is supplied as _DD3 , it becomes easy to output the first output signal E8 and the second output signal E8 bar of 5V level based on the input signal E1 of 1.8V level.

Also,
V _DD1 > V _DD2 > V _DD3 (4)
Then, the differential signal output circuit 41 has a function as a step-down circuit. This differential signal output circuit 41 is different from the previously described differential signal output circuit 31 (see FIG. 13) in the potential difference between the input signal E1, the first output signal E8, and the second output signal E8 bar. This is particularly effective when is large.

For example, in the differential signal output circuit 31 described above (see FIG. 13), the first output signal D8 and the second output signal D8 bar of 1.8V level are output based on the input signal D1 of 5V level. to the the 0V as the power supply voltage _{V SS} of the low potential side, the 5V as supply potential _{V DD1} of the high potential side, it is necessary to supply 1.8V as a power supply potential _{V DD2} of the high potential side. However, when such a power supply potential is supplied, the single-ended sense amplifiers 32 and 33 operating at a power supply potential of 1.8V receive the drive signals D2 and D3 of 5V level, and perform a desired operation. Is difficult.

On the other hand, in the differential signal output circuit 41, and 0V as the power supply voltage _{V SS} of the low potential side, the 5V as supply potential _{V DD1} of the high potential side, the 3.3V as a power source potential _{V DD2,} as a power supply potential _{V DD3} If 1.8V is supplied, it becomes easy to output the first output signal E8 and the second output signal E8 bar of 1.8V level based on the input signal E1 of 5V level.

Next, a twelfth embodiment of the present invention will be described. FIG. 15 is a diagram showing an output circuit according to the twelfth embodiment of the present invention. The differential signal output circuit 51 is a circuit that outputs a first output signal F8 and a second output signal F8 bar as a pair of differential signals based on the input signal F1, and inverters INV1, INV2, INV7. INV8, single-ended sense amplifiers 52 and 53, and current mirror type differential amplifier circuits 14 and 15. Each of these circuits operates by receiving supply of electric power by the power supply voltage V _SS of a power supply potential V _DD and the low potential side of the high potential side.

  The signal output circuit 51 is different from the differential signal output circuit 11 (see FIG. 11) described above in the configuration of single-ended sense amplifiers 52 and 53. The single-ended sense amplifier 52 includes N-channel transistors QN51 and QN52 and an inverter INV53, and supplies a signal F4 obtained by converting the drive signal F2 to a predetermined potential level to the differential amplifier circuits 14 and 15.

Source ~ drain path of transistor QN51 and QN52 are connected in series between power supply potential _{V SS} power supply potential _{V DD} and the low potential side of the high potential side, the gate of the transistor QN52 is driving signal F2 is Have been supplied. A connection point between the transistors QN51 and QN52 is connected to an input of the inverter INV53.

  The output of the inverter INV53 is connected to the gate of the transistor QN51, and the transistor QN51 forms a negative feedback loop from the output to the input of the inverter INV53. Therefore, the level of the signal F4 output from the inverter INV53 is a level corresponding to the gain of the feedback loop.

  The single-ended sense amplifier 53 includes N-channel transistors QN53 and QN54 and an inverter INV55, and supplies a signal F5 obtained by converting the drive signal F3 to a predetermined level to the differential amplifier circuits 14 and 15.

  The transistors QN53 and QN54 and the inverter INV55 in the single-ended sense amplifier 53 are connected in the same manner as the transistors QN51 and QN52 and the inverter INV53 in the single-ended sense amplifier 52. As a result, the single-ended sense amplifier 53 is The circuit configuration is the same as that of the single-ended sense amplifier 52.

  Thus, according to the differential signal output circuit 51, a function equivalent to that of the differential signal output circuit 11 can be realized with a smaller number of elements than the differential signal output circuit 11.

  Next, a thirteenth embodiment of the present invention is described. FIG. 16 is a diagram showing an output circuit according to a thirteenth embodiment of the present invention. The differential signal output circuit 61 is a circuit that outputs a first output signal G8 and a second output signal G8 bar as a pair of differential signals based on the input signal G1, and inverters INV31, INV32, INV37. , INV 38, single-ended sense amplifiers 62 and 63, and current mirror type differential amplifier circuits 34 and 35.

  The differential signal output circuit 61 is different from the previously described differential signal output circuit 31 (see FIG. 13) in the configuration of single-ended sense amplifiers 62 and 63. The single-ended sense amplifier 62 includes N-channel transistors QN61 and QN62 and an inverter INV63, and supplies a signal G4 obtained by converting the drive signal G2 to a predetermined level to the differential amplifier circuits 34 and 35.

Source ~ drain path of transistor QN61 and QN62 includes a power supply potential _{V DD2} of the high potential side are connected in series between power supply potential _{V SS} of the low potential side, the gate of the transistor QN62 is the drive signal G2 is Have been supplied. A connection point between the transistors QN61 and QN62 is connected to an input of the inverter INV63.

  The output of the inverter INV63 is connected to the gate of the transistor QN61, and the transistor QN61 forms a negative feedback loop from the output to the input of the inverter INV63. Therefore, the level of the signal G4 output from the inverter INV63 is a level corresponding to the gain of the feedback loop.

  The single-ended sense amplifier 63 includes N-channel transistors QN63 and QN64 and an inverter INV65, and supplies a signal G5 obtained by converting the drive signal G3 to a predetermined level to the differential amplifier circuits 34 and 35.

  The transistors QN63 and QN64 in the single-ended sense amplifier 63 and the inverter INV65 are connected in the same manner as the transistors QN61 and QN62 and the inverter INV63 in the single-ended sense amplifier 62. As a result, the single-ended sense amplifier 63 is The circuit configuration is the same as that of the single-ended sense amplifier 62.

  Thus, according to the differential signal output circuit 61, a function equivalent to that of the differential signal output circuit 31 can be realized with a smaller number of elements than the differential signal output circuit 31.

  Next, a fourteenth embodiment of the present invention is described. FIG. 17 is a diagram illustrating an output circuit according to a fourteenth embodiment of the present invention. The differential signal output circuit 71 is a circuit that outputs a first output signal H8 and a second output signal H8 bar as a pair of differential signals based on the input signal H1, and includes inverters INV31, INV32, INV47. , INV48, single-ended sense amplifiers 62 and 63, and current mirror type differential amplifier circuits 44 and 45.

  The differential signal output circuit 71 replaces the single-ended sense amplifiers 32 and 33 in the differential signal output circuit 41 (see FIG. 14) described above, and the differential signal output circuit 61 (see FIG. 16) described above. The single-ended sense amplifiers 62 and 63 are used.

  According to the differential signal output circuit 71, a function equivalent to that of the differential signal output circuit 41 can be realized with a smaller number of elements than the differential signal output circuit 41.

  The present invention can be used in an output circuit for outputting a signal to an external circuit and a semiconductor integrated circuit incorporating such an output circuit.

The figure which shows the structure of the output circuit which concerns on the 1st Embodiment of this invention. The figure which shows the waveform of the output signal of the output circuit shown in FIG. The figure which shows the structure of the output circuit which concerns on the 2nd Embodiment of this invention. The figure which shows the waveform of the output signal of the output circuit shown in FIG. The figure which shows the structure of the output circuit which concerns on the 3rd Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 4th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 5th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 6th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 7th Embodiment of this invention. 10 is a timing chart showing the operation of the differential signal output circuit shown in FIG. The figure which shows the structure of the output circuit which concerns on the 8th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 9th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 10th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 11th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 12th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 13th Embodiment of this invention. The figure which shows the structure of the output circuit which concerns on the 14th Embodiment of this invention. The figure which shows the structural example of the conventional differential signal output circuit. The figure which shows the other structural example of the conventional differential signal output circuit.

Explanation of symbols

10 output circuit 1, 11, 21, 31, 41, 51, 61, 71 differential signal output circuit 2, 3, 12, 13, 22, 23, 32, 33, 52, 53, 62, 63 single-ended Sense amplifier 4, 5, 14, 15, 34, 35, 44, 45 Differential amplifier circuit, 101 protection device, 102 buffer circuit, 103 to 105, INV1, INV2, ... inverter, QP1, QP2, ... P channel Transistor, QN1, QN2, ... N-channel transistor

Claims (17)

An output circuit for outputting an output signal having an amplitude smaller than a power supply voltage based on a first drive signal,
A first MOS transistor of a first type that applies a first drive signal to the gate and outputs a signal from the drain;
A second MOS transistor of a second type that applies a second drive signal to the gate and outputs a signal from the drain;
The second drive is performed by feeding back an output signal obtained by synthesizing the signal output from the first MOS transistor and the signal output from the second MOS transistor to the gate of the second MOS transistor. A feedback circuit for generating a signal;
An output circuit comprising: The feedback circuit is
A passive element having a first terminal connected to a connection point between the drain of the first MOS transistor and the drain of the second MOS transistor;
A buffer circuit for buffering a signal supplied from the second terminal of the passive element;
The output circuit according to claim 1, comprising: An output circuit for outputting an output signal having an amplitude smaller than a power supply voltage based on a first drive signal,
A first MOS transistor of a first type that applies a first drive signal to the gate and outputs a signal from the drain;
A second MOS transistor of a first type that applies a second drive signal to the gate and outputs a signal from the source;
The output signal obtained by combining the signal output from the first MOS transistor and the signal output from the second MOS transistor is inverted and fed back to the gate of the second MOS transistor. A feedback circuit for generating two drive signals;
An output circuit comprising: The feedback circuit is
A passive element having a first terminal connected to a connection point between the drain of the first MOS transistor and the source of the second MOS transistor;
An inverter for inverting the signal supplied from the second terminal of the passive element;
The output circuit according to claim 3, comprising: Based on the first and second drive signals constituting the pair of differential signals, for outputting the first and second output signals constituting the pair of differential signals having an amplitude smaller than the power supply voltage. An output circuit,
A first MOS transistor of a first type that applies a first drive signal to the gate and outputs a signal from the drain;
A second MOS transistor of a second type in which a third drive signal is applied to the gate and a signal is output from the drain;
A first output signal obtained by synthesizing a signal output from the first MOS transistor and a signal output from the second MOS transistor is fed back to the gate of the second MOS transistor to return the first output signal. A first feedback circuit for generating a drive signal of 3;
A third MOS transistor of the first type that applies a second drive signal to the gate and outputs a signal from the drain;
A fourth MOS transistor of a second type that applies a fourth drive signal to the gate and outputs a signal from the drain;
A second output signal obtained by synthesizing the signal output from the third MOS transistor and the signal output from the fourth MOS transistor is fed back to the gate of the fourth MOS transistor. A second feedback circuit for generating four drive signals;
An output circuit comprising: Based on the first and second drive signals constituting the pair of differential signals, for outputting the first and second output signals constituting the pair of differential signals having an amplitude smaller than the power supply voltage. An output circuit,
A first MOS transistor of a first type that applies a first drive signal to the gate and outputs a signal from the drain;
A second MOS transistor of the first type that applies a third drive signal to the gate and outputs a signal from the source;
The first output signal obtained by synthesizing the signal output from the first MOS transistor and the signal output from the second MOS transistor is inverted and fed back to the gate of the second MOS transistor. A first feedback circuit for generating a third drive signal thereby,
A third MOS transistor of the first type that applies a second drive signal to the gate and outputs a signal from the drain;
A fourth MOS transistor of a first type that applies a fourth drive signal to the gate and outputs a signal from the source;
The second output signal obtained by synthesizing the signal output from the third MOS transistor and the signal output from the fourth MOS transistor is inverted and fed back to the gate of the fourth MOS transistor. A second feedback circuit for generating a fourth drive signal by
An output circuit comprising: A first inverting circuit that inverts an input signal and outputs a first drive signal;
A second inverting circuit that inverts the first drive signal and outputs a second drive signal;
The output circuit according to claim 5, further comprising: An output circuit for outputting first and second output signals constituting a pair of differential signals based on first and second drive signals constituting a pair of differential signals,
First and second signal level conversion circuits for converting the first and second drive signals into signals of predetermined levels and outputting the signals, respectively;
A first differential circuit that outputs a signal corresponding to a difference between a signal output from the first signal level conversion circuit and a signal output from the second signal level conversion circuit;
A second differential circuit that outputs a signal corresponding to a difference between a signal output from the second signal level conversion circuit and a signal output from the first signal level conversion circuit;
A first output signal generation circuit that generates a first output signal based on a signal output from the first differential circuit;
A second output signal generation circuit for generating a second output signal based on a signal output from the second differential circuit;
An output circuit comprising:   9. The output circuit according to claim 8, wherein the first or second signal level conversion circuit includes a single-ended sense amplifier.   9. The output circuit according to claim 8, wherein the first or second differential circuit includes a current mirror type differential amplifier circuit.   The output circuit according to claim 8, wherein the first or second output signal generation circuit includes an inverter. A first inverting circuit that inverts an input signal and outputs a first drive signal;
A second inverting circuit that inverts the first drive signal and outputs a second drive signal;
The output circuit according to claim 8, further comprising:   The first and second inversion circuits operate by receiving power from the first and second power supply potentials, and the first and second signal level conversion circuits, the first and second differentials 13. The output circuit according to claim 12, wherein the circuit and the first and second output signal generation circuits operate by receiving power from the first and third power supply potentials.   The first and second inversion circuits operate by receiving power from the first and second power supply potentials, and the first and second signal level conversion circuits operate at the first and third power supply potentials. The first and second differential circuits and the first and second output signal generation circuits operate with power supplied from the first and fourth power supply potentials. The output circuit according to claim 12.   15. The output circuit according to claim 14, wherein the third power supply potential is higher than the second power supply potential, and the fourth power supply potential is higher than the third power supply potential.   The output circuit according to claim 14, wherein the third power supply potential is lower than the second power supply potential, and the fourth power supply potential is lower than the third power supply potential.   A semiconductor integrated circuit incorporating the output circuit according to claim 1.

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