JP2005018434A - Microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microprocessor which can execute a pipeline process of an encrypted command while preventing generation of a stall. <P>SOLUTION: After stored in a command register 111 of a command fetch part 11, the encrypted command sent from a command ROM 2 to the microprocessor 1 is decoded by an encrypted command decoding part 112 and the decoded command is held by a decoded command register 113. Then, the decoded command held by the decoded command register 113 is input to a command decoding part 12 via a selector 114 and a command cache 115 and decoded and calculation process is executed by a calculation executing part 13. Thus, the pipeline process of command queue encrypted command is sequentially executed by the command fetch part 11, the command decoding part 12 and the calculation executing part 13 in parallel. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor, and more particularly to a microprocessor that performs pipeline processing.
[0002]
[Prior art]
One technique for speeding up microprocessors is pipeline processing. In pipeline processing, the execution of instructions is divided into several stages, and a plurality of instructions are executed in parallel with little time. Thereby, a plurality of stages can be operated in parallel, and the processing efficiency of the microprocessor is improved. At this time, if all the stages can always be operated in parallel, high processing efficiency can be obtained.
[0003]
On the other hand, an instruction given to the microprocessor may be encrypted for the purpose of security protection of software. In this case, since the instruction (object code) stored in the instruction ROM outside the microprocessor is encrypted, in order to execute this instruction by the microprocessor, the code encrypted inside the microprocessor is used. Must be decrypted back to the original code before being encrypted.
[0004]
FIG. 7A shows an example of a stage configuration of pipeline processing including a stage of decryption of the encrypted instruction. In this example, the instruction is instruction fetch (F), decryption of encrypted instruction (DA), instruction decode (DB), operation execution (E), data cache access (M), and result writing (W). The six stages are sequentially processed. Here, the decryption (DA) stage of the encrypted instruction and the decode (DB) stage of the instruction are executed by the decoding unit of the microprocessor.
[0005]
FIG. 7B shows a state where a plurality of encrypted instructions, encryption instruction 1, encryption instruction 2,... Are sequentially pipelined in the above-described six stages. In this case, since the decoding (DA) stage and the instruction decoding (DB) stage of the encrypted instruction are executed in the decoding unit, the processing of the encrypted instruction 1 does not move to the execution (E) stage of the operation. Execution of the decryption (DA) stage of the encryption instruction 2 of the encryption instruction 2 cannot be started. Therefore, the pipeline is stopped (stall) before the decryption (DA) stage of the encrypted instruction (cycle 3).
[0006]
Similarly, in the encryption instruction 3, a stall occurs in cycles 4 and 5, and in the encryption instruction 4, a stall occurs in cycles 5, 6, and 7, and the processing efficiency of the pipeline decreases.
[0007]
A factor that causes a stall in pipeline processing is called a hazard, and a microprocessor that performs pipeline processing needs to take measures against this hazard.
[0008]
One of the countermeasures is that a hazard processing stage is provided in addition to the normal stage, and when the occurrence of a hazard is detected, the hazard processing stage is operated so that pipeline processing is continued (for example, (See Patent Document 1).
[0009]
[Patent Document 1]
JP 2000-105698 A (page 7-9, FIG. 1)
[0010]
[Problems to be solved by the invention]
However, in the method of providing a stage dedicated to the hazard processing as described above, when a hazard occurs, the number of stages required for the processing of the microprocessor becomes larger than that of the normal processing.
[0011]
Accordingly, an object of the present invention is to provide a microprocessor capable of pipelined processing of encrypted instructions while suppressing occurrence of stalls.
[0012]
[Means for Solving the Problems]
According to one aspect of the present invention, storage means for storing an externally applied instruction, encrypted instruction decryption means for decrypting an encrypted instruction stored in the storage means, and the encrypted instruction decryption means An instruction fetch unit having a decoded instruction holding unit that holds an instruction decoded by the output unit; a selection unit that selects and outputs either the output of the storage unit or the output of the decoded instruction holding unit; and the instruction Instruction decoding means for decoding an instruction output from the fetch unit, operation execution means for executing an operation based on a signal output from the instruction decoding means, and the encrypted instruction by a control signal output from the instruction decoding means A decoding control unit for controlling the execution of decoding by the decoding unit and for controlling the selection unit, and storing the storage unit in the instruction fetch unit. And the decryption control means causes the encryption instruction decryption means to decrypt the encrypted instruction and the selection means causes the decryption instruction holding means when the instruction is an encryption instruction. There is provided a microprocessor characterized in that the output is selected and output.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
(Embodiment)
FIG. 1 is a block diagram showing a configuration of a microprocessor according to an embodiment of the present invention.
[0015]
The microprocessor 1 includes an instruction fetch unit 11 that fetches an instruction read from the instruction ROM 2 outside the microprocessor 1, a decode unit 12 that decodes an instruction output from the instruction fetch unit 11, and a decode unit 12. A decryption control that controls decryption of the encrypted instruction when the instruction read from the instruction ROM 2 is an encrypted instruction. Part 14.
[0016]
Among these, the instruction fetch unit 11 includes an instruction register 111 that stores an instruction input from the instruction ROM 2, and an encrypted instruction decryption that decrypts the instruction stored in the instruction register 111 when the instruction is stored in the instruction register 111. Selecting one of the output of the decryption instruction register 113 holding the decryption instruction decrypted by the encryption section 112, the encrypted instruction decryption section 112, the output of the instruction register 111, and the output of the decryption instruction register 113 The selector 114 to be output and the instruction cache 115 to which the output of the selector 114 is input. The output of the instruction cache 115 is the output of the instruction fetch unit 11.
[0017]
Here, when an instruction in a group of encrypted instructions is executed, a decryption start instruction to be described later is executed immediately before the execution, and a decryption start signal is sent from the decoding unit 12 to the decryption control unit 14. Is output. When the decryption start signal is input (turned ON), the decryption control unit 14 instructs the encryption command decryption unit 112 to start decryption.
[0018]
On the other hand, at the end of the instructions in the instruction sequence of the group of encryption instructions, a decryption end instruction, which will be described later, is executed, and a decryption end signal is output from the decoding unit 12 to the decryption control unit 14. When the decryption end signal is input, the decryption control unit 14 instructs the encryption command decryption unit 112 to end the decryption (OFF). .
[0019]
While the start of decryption is instructed (while ON), the encrypted instruction decryption unit 112 reads the instruction stored in the instruction register 111 and executes decryption of the cipher.
[0020]
The decryption start instruction describes the encryption key (user key) data used for encryption, and this user key data is given to the encryption instruction decryption unit 112 via the decoding unit 12.
[0021]
In addition, when the decryption control signal output from the decryption control unit 14 is ON, the selector 114 also determines that the instruction input from the instruction ROM 2 is an encrypted instruction and outputs the decryption instruction register 113. Is selected and a decryption instruction is output.
[0022]
On the other hand, when the decryption control signal is OFF, the selector 114 outputs the instruction stored in the instruction register 111 as it is, assuming that the instruction input from the instruction ROM 2 is an unencrypted instruction.
[0023]
FIG. 2 is a block diagram showing an internal configuration of the encrypted instruction decryption unit 112 of FIG.
[0024]
The encrypted command decryption unit 112 outputs a write signal only when the decryption control signal is ON, and an encrypted command storage register 1122 that writes an external command with the write signal from the write control circuit 1121 And a user key storage register 1123 for writing user key data when the decryption control signal is ON.
[0025]
In addition, a mirror conversion circuit 1124 that performs mirror conversion, which will be described later, on the data in the encryption instruction storage register 1122 and user key data stored in the user key storage register 1123 are copied to the upper digit side to be twice as long. User-key expansion circuit 1125 that expands to the data of the data, exclusive-OR (xor) for each bit that performs an exclusive-OR (xor) operation for each bit of the output of the mirror conversion circuit 1124 and the output of the user key expansion circuit 1125 An arithmetic circuit 1126 is provided, and an output of the bitwise exclusive OR (xor) arithmetic circuit 1126 becomes a decryption instruction.
[0026]
Here, the decryption algorithm of the encrypted instruction decryption unit 112 will be described. Before that, the encryption method used in the encryption of the instruction of the microprocessor of the present embodiment will be described.
[0027]
FIG. 3 is a diagram for explaining the encryption process used in the instruction encryption of the microprocessor according to the present embodiment. Hereinafter, the encryption process will be described in order.
[0028]
(1) A user key prepared by arranging two user keys each having a 16-bit length, which is an encryption key dedicated to the user, and extending the user key to a 32-bit length is prepared in advance.
[0029]
(2) Perform an exclusive OR (xor) operation for each bit of the 32-bit length instruction (machine language) and the extended user key of 32 bits.
[0030]
Here, each bit of the instruction is represented as In, the bit of the extended user key is represented as Kn, the above operation result is represented as In xor Kn, and the operation result is referred to as an instruction masked with the user key. To do.
[0031]
(3) Perform mirror conversion of each bit of the instruction masked with the user key.
[0032]
In the mirror conversion, the n-th bit data is replaced with the (31-n) -th bit data. In this case, the 0-th bit data is the 31st bit and the first bit data is the 30th bit. .., 31st bit data is replaced with 0th bit.
[0033]
The data obtained as a result of this mirror conversion is an encrypted instruction, that is, an encrypted instruction.
[0034]
Next, the decryption algorithm of the encryption command decryption unit 112 will be described.
[0035]
FIG. 4 is a diagram for explaining a process of decrypting an encrypted instruction in the encrypted instruction decrypting unit 112. Hereinafter, the decoding process will be described in order.
[0036]
(1) The mirror conversion circuit 1124 mirror-converts the encryption command stored in the encryption command storage register 1122.
[0037]
As a result, the encryption command returns to the command masked with the user key described above.
[0038]
(2) A bitwise exclusive OR (xor) operation is performed between the instruction masked with the user key and the user key data expanded by the user key expansion circuit 1125.
[0039]
At this time, since the instruction masked with the user key is represented as In xor Kn, this operation is represented as (In xor Kn) xor Kn. When this logical expression is transformed, it becomes In xor (Kn xor Kn).
[0040]
Here, since the exclusive OR (xor) operation between the same data is 0, (Kn xor Kn) = 0, and the above equation is In xor 0 = In.
[0041]
In other words, the decoded instruction data In is obtained by this calculation.
[0042]
FIG. 5 is a diagram showing a format of a decoding start instruction and a decoding end instruction given to the microprocessor 1 of the present embodiment.
[0043]
FIG. 5A shows the format of the decryption start instruction. The decryption start instruction is a 32-bit instruction and is composed of a 16-bit decryption start operation (OP) code and a 16-bit user key.
[0044]
FIG. 5B shows the format of the decryption end instruction. The decoding end instruction is a 16-bit instruction and is composed only of a 16-bit decoding start operation (OP) code. However, since the decryption end instruction is placed at the end of the instruction sequence of the encrypted instruction, when it is given to the microprocessor 1, it is an encrypted 32-bit length instruction.
[0045]
FIG. 6 is a diagram showing stage transitions when pipeline processing is performed on encrypted instruction 1, encrypted instruction 2,..., Which is an instruction sequence of encrypted instructions, in microprocessor 1 of the present embodiment. It is.
[0046]
As shown in FIG. 6 (a), in the microprocessor 1, the encrypted instruction is instruction fetch (Fe), decryption of the encrypted instruction (Fu), instruction decode (D), and execution of operation (E). , Data cache access (M) and result writing (W) are sequentially processed in six stages.
[0047]
Among these, the instruction fetch unit 11 processes the instruction fetch (Fe) stage and the decryption (Fu) stage of the encrypted instruction.
[0048]
The instruction decode (D) stage is processed by the decode unit 12, and the processing after the operation execution (E) stage is processed by the operation execution unit 13.
[0049]
As described above, in the microprocessor 1, the instruction fetch (Fe) stage and the decryption (Fu) stage of the encrypted instruction are processed by the instruction fetch unit 11. At this time, the instruction fetch (Fe) stage includes an instruction fetch (Fe) stage. The register 111 is used, and the decryption instruction register 113 is used for the decryption (Fu) stage of the encryption instruction.
[0050]
Therefore, in the microprocessor 1 of the present embodiment, the process at the instruction fetch (Fe) stage and the process at the decryption (Fu) stage of the encrypted instruction can be simultaneously performed in parallel.
[0051]
Therefore, as shown in FIG. 6B, when pipeline processing of an instruction sequence of an encrypted instruction is performed by the microprocessor 1 of the present embodiment, all stages are not stalled between the stages. Can be operated in parallel.
[0052]
Thus, when the example of FIG. 6B is compared with FIG. 7B of the example of the conventional pipeline processing, for example, only four encrypted instructions can be processed in the conventional 12 cycles. However, in the present embodiment, processing of seven encrypted instructions can be executed.
[0053]
That is, the microprocessor 1 according to the present embodiment can improve the throughput of pipeline processing of encrypted instructions as compared with the conventional case.
[0054]
【The invention's effect】
According to the microprocessor of the present invention, it is possible to execute pipeline processing of encrypted instructions while suppressing the occurrence of stalls. Therefore, it is possible to improve the throughput of pipeline processing of encrypted instructions.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a microprocessor according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of an encrypted instruction decryption unit of the microprocessor according to the embodiment of the present invention.
FIG. 3 is a diagram for explaining a process of encrypting an instruction.
FIG. 4 is a diagram for explaining a process of decrypting an encrypted instruction in the microprocessor according to the embodiment of the present invention.
FIG. 5 is a diagram showing a format of a decoding start instruction and a decoding end instruction given to the microprocessor according to the embodiment of the present invention.
FIG. 6 is a stage transition diagram for explaining pipeline processing in the microprocessor according to the embodiment of the present invention.
FIG. 7 is a stage transition diagram for explaining pipeline processing in a conventional microprocessor;
[Explanation of symbols]
1 Microprocessor 2 Instruction ROM
11 Instruction fetch unit 12 Decoding unit 13 Operation execution unit 14 Decryption control unit 111 Instruction register 112 Encrypted instruction decryption unit 113 Decryption instruction register 114 Selector 115 Instruction cache 1121 Write control circuit 1122 Encrypted instruction storage register 1123 User key storage Register 1124 Mirror conversion circuit 1125 User key expansion circuit 1126 Exclusive OR (xor) circuit for each bit

Claims (8)

Storage means for storing an instruction given from the outside, encrypted instruction decryption means for decrypting an encrypted instruction stored in the storage means, and an instruction decrypted by the encrypted instruction decryption means An instruction fetch unit having a decoding instruction holding means; and a selection means for selecting and outputting either the output of the storage means or the output of the decoding instruction holding means;
Instruction decoding means for decoding an instruction output from the instruction fetch unit;
Calculation execution means for executing calculation based on a signal output from the instruction decoding means;
The decryption control means for controlling the execution of the decryption of the encrypted instruction decryption means by the control signal output from the instruction decode means, and for controlling the selection means,
When the instruction stored in the storage means of the instruction fetch unit is an encrypted instruction, the decryption control means causes the encrypted instruction decryption means to execute decryption of the encrypted instruction, A microprocessor characterized by causing the selection means to select and output the output of the decryption instruction holding means. A microprocessor in which instruction execution is pipelined in the order of an instruction fetch stage, an encryption instruction decryption stage, an instruction decode stage, and an operation execution stage;
2. The microprocessor according to claim 1, wherein processing at the decryption stage of the encrypted instruction and processing at the instruction fetch stage are executed by the instruction fetch unit. 3. The microprocessor according to claim 2, wherein the instruction fetch stage executes processing of a next instruction in parallel with processing of a current instruction at a decryption stage of the encrypted instruction. 2. The microprocessor according to claim 1, wherein start of decoding in said decoding means is controlled by a decoding start instruction, and end of decoding is controlled by a decoding end instruction. 5. The microprocessor according to claim 4, wherein the decryption start instruction is executed immediately before an instruction sequence of a group of encryption instructions. 5. The microprocessor according to claim 4, wherein the decryption end instruction is executed at the end of an instruction sequence of a group of encryption instructions. 5. The microprocessor according to claim 4, wherein the decryption start instruction is composed of an operation code for instructing decryption start and encryption key data used for decryption. The encryption key data output from the instruction decoding means after the decryption start instruction is decoded is input to the encrypted instruction decryption means, and during the execution of the decryption, the encryption instruction decryption means The microprocessor according to claim 7, wherein the microprocessor is held.

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