JP4939305B2 - Encryption / decryption device - Google Patents

Description

  The present invention relates to an encryption / decryption device, and more particularly to a technique for reducing a circuit scale.

  Conventionally, in an encryption / decryption device, an AES (Advanced Encryption Standard) method, which is a common key encryption method, has been adopted (see, for example, Non-Patent Document 1).

  In an encryption / decryption device adopting the AES method, an encryption key for performing an encryption operation and a decryption key for performing a decryption operation are respectively held in a register or the like.

  That is, first, the encryption key read from the memory or the like is held in the encryption key register. Next, a decryption key is generated by executing a key schedule operation on the encryption key, and the generated decryption key is held in the decryption key register. The encryption key is read from the encryption key register during the encryption operation, and the decryption key is read from the decryption key register during the decryption operation and used.

"Announcing the ADVANCED ENCRYPTION STANDARD (AES)", [online], National Institute of Standards and Technology (NIST), [Search May 1, 2007], Internet <URL: http://csrc.nist.gov/ publications / fips / fips197 / fips-197.pdf>

  In the AES system, a key having a maximum bit length of 256 bits is used. Therefore, it is necessary to provide a register having a length of 256 bits × 2 = 512 bits corresponding to the encryption key and the decryption key as the key register. Therefore, there is a problem that the circuit scale becomes large.

  The present invention has been made to solve the above problems, and an object thereof is to provide an encryption / decryption device capable of reducing the circuit scale.

In one embodiment of the present invention, the encryption / decryption operation circuit encrypts predetermined data based on an AES method using an encryption key having a predetermined bit length, and the encryption operation circuit encrypts the predetermined data. Both of the circuit functions of a decryption operation circuit that decrypts the predetermined data obtained by the conversion operation based on the AES method using a decryption key having the same bit length as the encryption key. The key schedule calculation circuit is for performing a process for generating the other from one of the encryption key and the decryption key, that is, a key schedule calculation process. Key storage device consists of less than 256 bits long and no more than 392 bits long, when a predetermined bit length is 196 bits long or 256 bits long, have the line operations for alternately stored in the encryption key and a decryption key, If the predetermined bit length is 128 bits long, it intends row operations simultaneously storing an encryption key and a decryption key.

  In the present invention, since the two keys are alternately stored in one key storage device, the circuit scale can be reduced as compared with the case where two key storage devices are used.

<Embodiment 1>
FIG. 1 is a block diagram schematically showing the configuration of the encryption / decryption device according to the first embodiment.

  As shown in FIG. 1, the encryption / decryption device according to the present embodiment includes an encryption / decryption operation circuit 100, a key schedule operation circuit 200, and an encryption / decryption key register 300. The encryption operation and the decryption operation are performed based on the method.

  The encryption / decryption operation circuit 100 performs encryption operation on predetermined data based on the AES method using an encryption key having a predetermined bit length (128 bits, 192 bits, or 256 bits in the AES method), And a circuit function of a decryption operation circuit that decrypts the predetermined data encrypted by the encryption operation circuit based on an AES method using a decryption key having the same bit length as the encryption key. Yes.

  The key schedule calculation circuit 200 is for performing a process for generating the other from one of the encryption key and the decryption key, that is, a key schedule calculation process.

  The encryption / decryption key register 300 is a key storage device that performs an operation of alternately storing an encryption key and a decryption key.

  In FIG. 2, a key storage device (encryption key register 301) for storing an encryption key and a key storage device (decryption key register 302) for storing a decryption key are separately provided for comparison, and these are provided as a key selection circuit. 400 shows an encryption / decryption device to be selected.

  In FIG. 2, first, the encryption key input from the outside is stored in the encryption key register 301. Next, the key schedule calculation circuit 200 generates a decryption key from the encryption key stored in the encryption key register 301 and stores it in the decryption key register 302. Then, the encryption / decryption operation circuit 100 executes the encryption key stored in the encryption key register 301 when executing the encryption operation, and the decryption key stored in the decryption key register 302 when executing the decryption operation. Each is obtained via the key selection circuit 400 and the calculation is executed.

  In such a case, for example, when the encryption key and the decryption key each have a 256-bit length, the total bit length of the key storage device is 256 bits × 2 = 512 bits, so that the circuit scale increases. There is a problem that.

  On the other hand, in the encryption / decryption device of FIG. 1 according to the present embodiment, the encryption / decryption key register 300 stores only one of the encryption key and the decryption key, and if necessary, The key schedule calculation circuit 200 generates one key from the other key, and overwrites the generated key to the encryption / decryption key register 300. This makes it possible to perform necessary encryption and decryption operations while suppressing the total bit length of the key storage device, that is, the bit length of the encryption / decryption key register 300 to 256 bits.

  That is, the encryption / decryption device of FIG. 1 according to the present embodiment pays attention to the fact that the encryption / decryption operation circuit 100 does not use the encryption key and the decryption key at the same time, and stores only one of the keys. The minimum necessary key storage device is provided. Therefore, as compared with FIG. 2, although the processing time for generating the other key from one key by the key schedule calculation circuit 200 is required, the circuit scale can be reduced.

  In FIG. 1, the operation of generating the other key from one key by the key schedule calculation circuit 200 and overwriting it on the encryption / decryption key register 300 is different from the operation type (for example, encryption operation) to the other (for example, encryption operation). This is performed only when a transition is made to a decoding operation.

  That is, when the decryption operation is performed after the encryption operation, the decryption key is overwritten on the encryption key stored in the encryption / decryption key register 300, and when the encryption operation is performed after the decryption operation. The encryption key is overwritten on the decryption key stored in the encryption / decryption key register 300. On the other hand, when the encryption operation is continued after the encryption operation, or when the decryption operation is continued after the decryption operation, the key is not overwritten on the encryption / decryption key register 300.

  In order to appropriately perform this overwriting, the encryption / decryption device determines whether the type of operation to be performed next is encryption / decryption, and the key currently stored in the encryption / decryption key register 300. It is necessary to detect which type of encryption key / decryption key.

  The detection of the type of operation described above may be performed by analyzing the operation command every time an operation command is input, or by acquiring and analyzing a program in which a series of operation commands are described in advance. You may go.

  Further, the detection of the key type may be performed by reading the key from the encryption / decryption key register 300 for each calculation, or, as shown in FIG. 3, the encryption / decryption key register 300. An encryption / decryption key discriminating circuit 310 is provided for storing the type of key stored in the internal bit (for example, “1” is stored for an encryption key and “0” is stored for a decryption key). It may be done by. Then, this built-in bit may be inverted at the timing when the key is rewritten.

  Alternatively, as shown in FIG. 4, an encryption / decryption key generation automatic circuit 320 may be provided in addition to the encryption / decryption key determination circuit 310. The encryption / decryption key generation automatic circuit 320 responds to an operation command input from the outside to the encryption / decryption device, and determines the type of the key stored in the encryption / decryption key register 300 as an encryption / decryption key determination circuit. The key schedule calculation circuit 200 generates a key and rewrites it as necessary. As a result, the key can be rewritten in response to an operation command input from the outside.

  As described above, the encryption / decryption device according to the present embodiment performs an operation of alternately storing the second key, that is, the encryption key and the decryption key, in one key storage device including the encryption / decryption key register 300. Do. Therefore, the circuit scale can be reduced as compared with the case where two key storage devices each including the encryption key register 301 and the decryption key register 302 are provided as shown in FIG.

  In the above description, the case where the bit length of the encryption / decryption key register 300 is the same as that of the encryption key and the decryption key (256 bits) has been described. If the bit length of the decryption key register 300 is equal to or larger than the bit length of the encryption key and the decryption key and less than twice (less than 512 bits), the circuit scale can be reduced compared to the case of FIG. is there.

<Embodiment 2>
In the first embodiment, the case where the key schedule calculation process is executed alone to generate the other key from one key has been described. However, in the AES scheme, the encryption key transitions to a decryption key by performing an encryption operation, and the decryption key transitions to an encryption key by performing a decryption operation. Therefore, by using this, it is possible to omit the key schedule calculation process that is executed redundantly.

  FIG. 5 is a block diagram schematically showing the configuration of the encryption / decryption device according to the second embodiment. FIG. 5 shows the encryption / decryption key register 300 overwritten with the decryption key or the encryption key generated by the arithmetic processing in the encryption / decryption arithmetic circuit 100 in FIG. As a result, the number of executions of the key schedule calculation process can be reduced, and the processing time can be shortened.

  6 to 7 correspond to pages 35 to 38 of Non-Patent Document 1, and an encryption key / decryption key having a 128-bit length performs an encryption / decryption operation so that a 128-bit length is decrypted. A transition generated as a key / encryption key is shown. 6 corresponds to the encryption operation, and FIG. 7 corresponds to the decryption operation.

  FIG. 6 shows an encryption key round [0] .k_sch before the encryption operation and an encryption key round [10] .k_sch after the encryption operation. Further, FIG. 7 shows a decryption key round [0] .ik_sch before the decryption operation and a decryption key round [10] .ik_sch after the decryption operation. Note that round [n] (0 <n <10) corresponds to a key in the middle of an operation, that is, a transitioning key.

  As shown in FIGS. 6 to 7, the encryption key round [10] .k_sch after the encryption operation is equal to the decryption key round [0] .ik_sch before the decryption operation, and the decryption key round [10] after the decryption operation ] .Ik_sch is equal to the encryption key round [0] .k_sch before the encryption operation. That is, the encryption key is changed to the decryption key by the encryption operation, and the decryption key is changed to the encryption key by the decryption operation.

  As described above, in the encryption / decryption device according to the present embodiment, the encryption / decryption operation circuit 100 is generated from the decryption key generated from the encryption key accompanying the encryption operation or from the decryption key accompanying the decryption operation. Each encryption key is written into the encryption / decryption key register 300. Therefore, in addition to the effect of the first embodiment, the number of executions of the key schedule calculation process can be reduced and the processing time can be shortened.

  This embodiment is particularly effective when the timing at which the key is rewritten is detected in advance. Therefore, for example, when the timing at which the key is rewritten is detected in advance, the encryption / decryption operation circuit 100 as described above is used (that is, the key schedule operation circuit 200 is not used alone, but encryption / decryption is used. When the key generation (used at the same time as the arithmetic circuit 100) is performed and the timing at which the key is rewritten is not detected in advance, the key is generated using the key schedule arithmetic circuit 200 alone as shown in FIG. do it.

<Embodiment 3>
In the first embodiment, when the bit length of the encryption / decryption key register 300 is less than twice the bit length of the encryption key and the decryption key (in other words, the bit length of the encryption key and the decryption key is the encryption / decryption key). The operation of alternately storing the encryption key and the decryption key in the encryption / decryption key register 300 when the bit length of the register 300 is larger than half the bit length) has been described.

  That is, when the bit length of the encryption key and the decryption key is larger than half the bit length of the encryption / decryption key register 300, the encryption key and the decryption key cannot be stored in the encryption / decryption key register 300 at the same time. However, if the bit length of the encryption key and the decryption key is less than half the bit length of the encryption / decryption key register 300, the encryption key and the decryption key are simultaneously used for the encryption / decryption key. It can be stored in the register 300.

  The encryption / decryption device according to the third embodiment is characterized in that, when a plurality of sets of encryption keys and decryption keys are used, the storage operation in the encryption / decryption key register 300 varies depending on the bit lengths. It is what.

  FIG. 8 is a block diagram schematically showing the configuration of the encryption / decryption device according to the present embodiment. 8, the encryption / decryption device includes an encryption / decryption key register 300a having a 256-bit length, and the encryption / decryption key register 300a has key storage areas 303 and 304 having a 128-bit length. ing.

  When the bit length of the encryption key and the decryption key is 128 bits or less, the encryption / decryption key register 300a performs the same operation as FIG. When the bit length of the key and the decryption key is larger than 128 bits, the operation of alternately storing them is performed as in the first embodiment.

  As described above, the encryption / decryption device according to the present embodiment includes the encryption / decryption key register 300a having a length of 128 × 2 = 256 bits or more and less than 196 × 2 = 392 bits, and includes an encryption key and a decryption key. If the bit length of the key is greater than 128 bits (specifically, 192 bits or 256 bits), these are alternately stored, and the bit length of the encryption key and the decryption key is 128 bits or less. In some cases (specifically, in the case of 128 bits), an operation of storing these simultaneously is performed. Therefore, in addition to the effect of the first embodiment, the processing time can be shortened when the bit length of the encryption key and the decryption key is 128 bits.

  In the above description, the case where the encryption / decryption key register 300a having a 256-bit length simultaneously stores the encryption key and the decryption key having a 128-bit length has been described. , May be the same. That is, as shown in FIG. 9, the key storage areas 303 and 304 may simultaneously store a first encryption key and a second encryption key each having a 128-bit length. Note that the first encryption key and the second encryption key constitute two types of keys having the same bit length and different values.

  When the bit length of the first encryption key is 128 bits, the encryption / decryption device of FIG. 9 stores the operation of storing the first encryption key and the second decryption key at the same time and the first decryption key (the first encryption key). And the operation of simultaneously storing the second decryption key (corresponding to the second encryption key). Further, when the bit length of the first encryption key is 192 bits or 256 bits, an operation of alternately storing the first encryption key and the first decryption key is performed. That is, when the bit length of the first encryption key is 128 bits, two types of keys can be used.

1 is a block diagram schematically showing a configuration of an encryption / decryption device according to Embodiment 1. FIG. It is a block diagram which shows typically one structure of the encryption / decryption apparatus for a comparison. 1 is a block diagram schematically showing a configuration of an encryption / decryption device according to Embodiment 1. FIG. 1 is a block diagram schematically showing a configuration of an encryption / decryption device according to Embodiment 1. FIG. 6 is a block diagram schematically showing a configuration of an encryption / decryption device according to Embodiment 2. FIG. FIG. 10 is a diagram illustrating an encryption operation in the encryption / decryption device according to the second embodiment. FIG. 10 is a diagram showing a decryption operation in the encryption / decryption device according to the second embodiment. FIG. 10 is a block diagram schematically showing a configuration of an encryption / decryption device according to a third embodiment. FIG. 10 is a block diagram schematically showing a configuration of an encryption / decryption device according to a third embodiment.

Explanation of symbols

  100 Encryption / Decryption Operation Circuit, 200 Key Schedule Operation Circuit, 300, 300a Encryption / Decryption Key Register, 301 Encryption Key Register, 302 Decryption Key Register, 303, 304 Key Storage Area, 310 Encryption / Decryption Key Discrimination Circuit, 320 encryption / decryption key generation automatic circuit, 400 key selection circuit.

Claims (2)

A cryptographic operation circuit that performs an encryption operation based on an AES method using an encryption key having a predetermined bit length, and the predetermined data encrypted by the encryption operation circuit has the predetermined bit length An encryption / decryption operation circuit having a decryption operation circuit that performs a decryption operation based on the AES method using a decryption key;
A key schedule calculation circuit capable of generating the other from either one of the encryption key and the decryption key;
A key storage device having a length of 256 bits or more and less than 392 bits ,
The key storage device
It said predetermined when the bit length is 196 bits long or 256 bits long, have the line the operation of storing the encryption key and the decryption key alternately,
Said predetermined when the bit length is 128 bits long, the encryption key and the decryption key at the same time line cormorants encryption / decryption device operates to store. Cryptographic operation circuit for performing encryption operation based on AES method using first encryption key having predetermined bit length or second encryption key having predetermined bit length, and encryption operation by the encryption operation circuit Encryption / decryption operation having a decryption operation circuit for performing the decryption operation based on the AES method using the first decryption key having the predetermined bit length or the second decryption key having the predetermined bit length Circuit,
A key schedule calculation circuit capable of generating the other from either one of the encryption key and the decryption key;
A key storage device having a length of 256 bits or more and less than 392 bits;
With
The key storage device
When the predetermined bit length is 196 bits length or 256 bits length, an operation of alternately storing the first encryption key and the first decryption key is performed,
When the predetermined bit length is 128 bits, an operation for simultaneously storing the first encryption key and the second encryption key and an operation for simultaneously storing the first decryption key and the second decryption key Alternate encryption / decryption device.

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