JP2005011504A - Flash memory devices that support efficient memory locking and methods of operating flash memory devices - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide flash memory devices that support sufficient memory locking and the driving method of the flash memory devices. <P>SOLUTION: Flash memory devices include at least one flash memory array and an address comparison circuit that is configured to indicate whether an applied row address associated with a first operation (that is. program, erase) is within or outside the unlock area of at least the one flash memory array. Moreover, a control circuit is also provided. This control circuit is configured to block the performance of the first operation on the first flash memory array detecting an indication from the address compare circuit that the applied row address is outside the unlock area of the flash memory array. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an integrated circuit of a memory device, and more particularly, to a flash memory device and a driving method of the flash memory device.

  Flash memory devices are a form of non-volatile memory that generally uses an array of EEPROM cells. In particular, the flash memory is implemented by an EEPROM technology in which a plurality of memory areas are erased and programmed by one programming operation. Normal EEPROM technology erases and programs only one area at a time, but the system can use flash memory to read and write different areas at the same time. Can work. The flash memory is generally divided into two types, a NOR type flash memory and a NAND type flash memory. NOR and NAND names come from the form of logic gates used for each storage cell. The NOR type flash is the first developed form. The NOR-type flash memory has a full address / data interface (random address / data interface) that allows random access in any area, although the erasing and writing times are relatively long. Such features only need to be updated from time to time to suit the storage of program code. The NOR type flash memory may have a durability in the range of 10,000 to 100,000 erase cycles. The NOR type flash memory is the base for an early flash-based removable media including all of CompactFlash and SmartMedia. In comparison, NAND flash typically has faster erase and write (ie, program) times than NOR flash, high density, low cost per bit, and higher durability. However, NAND flash I / O interfaces generally allow only sequential data access. Therefore, it is suitable for a large capacity device such as a PC card. NAND flash is leading various small media formats including MMC, secure digital, and memory stick. NAND flash memory forms the core of a fluid USB interface reservoir known as key drive.

Also, flash memory and other non-volatile memory devices have evolved with write protection characteristics to reduce accidental erasure of data to be protected and double writing of data. Examples of nonvolatile memory devices having write protection are disclosed in Patent Documents 1 to 3. However, conventional write protection techniques typically require locking one or more fixed-size blocks in the memory array and require the use of additional external pins to control the locking operation. Accordingly, despite such conventional non-volatile memory devices, there is a need for an improved non-volatile memory device with flexible write protection that limits the use of additional pins and protection against fixed-size blocks. It has been.
US Pat. No. 6,031,757 US Pat. No. 5,513,136 US Pat. No. 5,197,034

  A technical problem to be solved by the present invention is to provide a flash memory device that can perform a locking operation without using an additional external pin.

  The flash memory device according to an embodiment of the present invention may be configured such that a supply address supplied in association with one or more memory arrays and a first operation (ie, program, erase) is a release area of the one or more flash memory arrays. It includes an address comparison circuit that indicates whether it is internal or external. A control circuit is also provided. The control circuit prevents execution of the first operation in the flash memory array in response to an instruction detected by the address comparison circuit and indicating that the supply address is outside the release area of the flash memory array. Configured to do. The address comparator circuit is configured to latch a supply start address supplied in synchronization with a start clock signal, and to latch a supply end address supplied in synchronization with an end clock signal. And a configured end address register. The address comparison circuit is configured to receive a latched start address from the start address register and a start address comparator configured to receive the latched start address from the end address register. And an end address comparator. In addition, a Boolean logic unit may be further provided at the output of the start and end address comparators. The Boolean logic unit generates a release signal indicating whether the supply address associated with the first operation is inside or outside the release area of the flash memory array. Provided to the release circuit and serves to block the instruction if the value of the release signal indicates that the supply address is outside the release area.

  According to another embodiment of the present invention, the present invention includes a flash memory device having one or more flash memory arrays, wherein the flash memory array is electrically connected to a word line of the flash memory array. A word line control circuit and a bit line control circuit electrically connected to the bit lines of the flash memory array; The word line and bit line control circuit is responsive to a command control signal (ie, CTL). An address comparison circuit is also provided. The comparison circuit is configured to indicate whether a supply row address supplied in association with a program or erase command is inside or outside the release area of the flash memory array. The boundary of the release area can be specified by a start address and an end address indicating a row in the flash memory array. The start and end addresses can be stored in a register in the comparison circuit. The comparison circuit generates an activation level release signal if the supply row address is inside the release region, and generates an inactivation level release signal if the supply row address is outside the release region. By generating, it can be shown whether the supply row address is inside or outside the release area.

  The release signal and the command are provided to a main control circuit, and the main control circuit generates a command enable signal in response to the command and the release signal. The command enable signal may be a program enable signal if the command is a program command, and may be an erase command enable signal if the command is an erase command. The command enable signal is provided to a corresponding command control circuit, and the command control circuit generates the command control signal in response to the command enable signal. The command control signal can be provided to the bit line and word line control circuits and can operate to lock these circuits in the active state.

  According to another embodiment of the present invention, the main control circuit can respond to the address input pulse signal AIP received from one pin of the flash memory device. In addition, the flash memory device may include an address port that is narrower than the entire width of a supplied address. In this case, the flash memory device is configured to latch the first and second portions of the supply row address in synchronization with successive first and second leading edges of the address input pulse signal.

  The address comparison circuit includes separate start and end address registers. The start address register is configured to latch a supply start address supplied in synchronization with a start clock signal, and the end address register is configured to latch a supply end address supplied in synchronization with an end clock signal. Composed. These start and end clock signals can be generated by the main control circuit. In particular, the main control circuit generates the start clock signal in response to a first sequence of address input pulses and generates the end clock signal in response to a second sequence of address input pulses.

  In addition, another embodiment of the present invention includes a method of operating a flash memory device. The method includes loading a start and end address associated with a release area of a flash memory array into the flash memory device in response to a power up and / or reset operation. Next, during a normal mode operation, a supply address supplied in association with an erase or program command is loaded into the flash memory device. The supply address is compared with the start address to determine whether the supply address is greater than or equal to the start address. The supply address is compared with the end address to determine whether the supply address is less than or equal to the end address. Next, a release signal having an active level may be generated in response to determining whether the supply address is greater than or equal to the start address and whether the supply address is less than or equal to the end address.

  According to the present invention, the locking operation in the flash memory device can be performed without using an additional external pin.

  For a full understanding of the invention and its operational advantages and objectives achieved by the practice of the invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the invention and the contents described in the accompanying drawings. I must.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements.

  Referring to FIG. 1, a flash memory system 100 according to an embodiment of the present invention includes first and second flash memory devices 110-1 and 110-2, respectively. Each of these flash memory devices can be formed on each semiconductor integrated circuit substrate (for example, a semiconductor chip), and each substrate may be mounted in an individual integrated circuit package, or a plurality of substrates may be integrated into one integrated circuit package. A single large-capacity flash memory device may be configured by mounting side by side in a circuit package (not shown). The flash memory devices 110-1 and 110-2 can operate independently of each other, and can also operate in combination with other flash memory devices as illustrated.

  The first flash memory device 110-1 includes a first flash memory array 120-1. The first flash memory array 120-1 can be configured to support a plurality of rows and a plurality of columns of flash memory cells as in the conventional method. Each row of flash memory cells is electrically coupled to a respective word line, and each column of flash memory cells is electrically coupled to a respective bit line. The word line in the first flash memory array 120-1 receives the word line signal in response to the row address (shown as ADD <17: 8>) from the first word line control circuit 132-1. The first word line control circuit 132-1 may be included in the word line driver circuit and the first row decoder 130-1. The bit lines in the first flash memory array 120-1 provide read data to the first bit line control circuit 142-1, which is electrically connected to the first column decoder 140-1, and the first bit line control circuit. Write data is received from 142-1. The first column decoder 140-1 responds to the column segment address (indicated as ADD <7: 0>). The write data and the read data are provided to the first bit line control circuit 142-1 or provided from the first bit line control circuit 142-1 via the bidirectional data bus DATA <7: 0>. . Since the word line control circuit 132-1, the row decoder 130-1, the bit line control circuit 142-1 and the column decoder 140-1 may be of a conventional design, further explanation is omitted.

In the first flash memory array 120-1, the active area is programmed (ie, written) and erased in response to the program and erase commands, respectively, and the inactive area is not programmed and / or erased. The active area is shown as a release area 121-1, and the inactive area is shown as a lock area 123-1. Each of these regions 121-1 and 123-1 includes a plurality of flash memory cell rows constituting one or more adjacent row blocks in the first flash memory array 120-1. The lock area 123-1 extends from row 0 (LSB address) to an intermediate row in the first flash memory array 120-1. The intermediate row has a start row address STADD <17: 8> minus 1 (ie, intermediate row = STADD <17: 8> −1b, where “b” indicates binary notation and STADD <18> = 0b). The release area 121-1 extends from a start row address STADD <17: 8> to a row address defined as an end row address EDADD <17: 8> (here, EDADD <18> = 0b). Accordingly, in a preferred embodiment of the present invention, the first flash memory array 120-1 has 2 ¹⁰ addressable row flash memory cells partitioned into ⁸ segments at 8 bits / segment, the first flash memory array 120-1 means having a flash memory cell of ^{2 11} column.

  Referring to FIG. 2, the start and end row addresses can be programmed in corresponding registers in the first flash memory device 110-1. In another application, the end row address EDADD may correspond to the last addressable row flash memory cell in the first flash memory array 120-1 (ie, EDADD <18: 8> is 01111111111). be equivalent to). Setting the ending row address EDADD as the last address in the first flash memory array 120-1 means that the release region 121-1 may be flashed without interruption of one or more row blocks defined in the lock region. Useful when constructing a row block of flash memory cells spanning a memory array.

  The second flash memory device 110-2 is configured in the same manner as the first flash memory device 110-1. In particular, the second flash memory device 110-2 includes a second flash memory array 120-2 having the same capacity as the first flash memory array 120-1. The word lines in the second flash memory array 120-2 are sent from the second word line control circuit 132-2 and the second row decoder 130-2 in response to a row address (indicated as ADD <17: 8>). Receive a word line signal. The bit lines in the second flash memory array 120-2 provide read data to the second bit line control circuit 142-2 electrically connected to the second column decoder 140-2 or the second bit line control. Write data is received from the circuit 142-2. The second column decoder 140-2 responds to the column segment address (indicated as ADD <7: 0>). The write data and the read data are provided to the second bit line control circuit 142-2 via the bidirectional data bus DATA <7: 0>, and are provided from the second bit line control circuit 142-2. This data bus is shared by the first and second flash memory devices 110-1 and 110-2.

  The 19-bit address ADD <18: 0> is a plurality of address bytes (ie, 8 bytes) sequentially loaded on an address bus electrically connected to the first and second flash memory devices 110-1 and 110-2. Bit bytes). The 19-bit address can be indicated by a start address STADD and an end address EDADD when the first and second flash memory devices 110-1 and 110-2 are initialized. Thus, the 19-bit address is used to identify a particular row address and column segment while performing program, erase and read operations. The largest bit (i.e., ADD <18>) of the 19-bit address operates as a chip selection signal, and the chip selection signal is responsive to the respective command or other control signal in the first and second flash memory devices. Among these, it has a function of specifying which one is addressed. In the flash memory device system 100, the first flash memory device 110-1 has the next first address; 000. . . 0000 ≦ ADD <18: 0> ≦ 011. . . Associated with the memory space defined as 1111, the second memory device 110-2 has the next second address; . . 0000 ≦ ADD <18: 0> ≦ 111. . . Associated with a memory space defined as 1111.

  The second flash memory array 120-2 supports an active area that is programmed (ie, written) and erased in response to a program and erase command CMD, respectively, and an inactive area that is not programmed and / or erased. Configured as follows. In the present specification, the active region is described as a release region 121-2, and the inactive region is described as a lock region 123-2. Each of these regions 121-1 and 123-1 includes a plurality of row flash memory cells. In addition, the release area 121-2 includes a row corresponding to the row 0 (STADD <17: 8> = 000... 0000) to the end row address (EDADD <17: 8>, where EDADD <18> = 1b). Is shown extending to an intermediate row. The lock area 123-2 is shown to extend from the next row after the end row address to the last physical row address in the second flash memory array 120-2. By having a release area in the first and second flash memory arrays 120-1 and 120-2, the address is STADD <18: 0> = 0XXX. . . XXX to EDADD <18: 0> = 0111. . . 111 and STADD <18: 0> = 100... Within the first flash memory array 120-1. . . 000 to EDADD <18: 0> = 1XXX. . . The address space extending up to XXX and not interrupted extends to the first and second flash memory arrays 120-1 and 120-2. A separate address space configuration is possible in each flash memory array. For example, a plurality of start and end addresses may be formed in each flash memory device 110-1 and 110-2 to configure a plurality of active regions and a plurality of inactive regions in each flash memory array.

  The first flash memory device 110-1 includes an address comparison circuit 160-1 and a first control circuit. The first control circuit includes a main control circuit 170-1, an erase control circuit 150-1, and a program control circuit 152-1. Referring to FIG. 2, the address comparison circuit 160-1 responds to the largest portion of the received address indicated by ADD <18: 8> and a plurality of control signals generated by the main control circuit 170-1. To do. These control signals include a “start” clock signal STCLK, an “end” clock signal EDCLK, and a reset signal RESET. The address comparison circuit 160-1 generates a release signal ULK_1, and the release signal ULK_1 indicates that the received row address ADD <17: 8> indicates a row in the release area 121-1 of the first flash memory array 120-1. Indicates whether or not an instruction is given. The main control circuit 170-1 responds to the chip selection signal indicated by ADD <18>, the reset signal RST, the command signal CMD, the address input pulse signal AIP, and the release signal ULK_1. The value of the chip selection signal ADD <18> determines whether the first flash memory device 110-1 or the second flash memory device 110-2 is addressed by a supply command signal supplied.

  The main control circuit 170-1 generates a start clock signal STCLK, an end clock signal EDCLK, and a reset signal RESET and provides them to the address comparison circuit 160-1. Further, the main control circuit 170-1 generates the erase enable signal EEN_1 or the program enable signal PEN_1 according to the value of the release signal ULK_1. In particular, when a program operation is requested by the command signal CMD and the release signal ULK_1 is generated at an active high level, the program enable signal PEN_1 is generated at an active level, and the program operation can be performed in the release region 121-1. Similarly, if an erase operation is requested by the command signal CMD and the release signal ULK_1 is generated at an active high level, the erase enable signal EEN_1 is generated at an active level, and the erase operation is performed in the release region 121-1. It becomes possible. The erase control circuit 150-1 generates an active level control signal CTL_1 in response to the active erase enable signal EEN_1. Similarly, the program control circuit 152-1 generates an active level control signal CTL_1 in response to the active program enable signal PEN_1. The activation control signal CTL_1 operates so that the word line control circuit 132_1 and the bit line control circuit 142_1 are enabled.

  Similarly, the second flash memory device 110-2 includes an address comparison circuit 160-2 and a second control circuit. The second control circuit includes a main control circuit 170-2, an erase control circuit 150-2, and a program control circuit 152-2. Referring to FIG. 2, the address comparison circuit 160-2 has the largest received address indicated as ADD <18: 8> and a plurality of corresponding control signals STCLK generated by the main control circuit 170-2. , EDCLK, and RESET. Further, the address comparison circuit 160-2 generates a release signal ULK_2, and the release signal ULK_2 indicates that the received row address ADD <17: 8> is in the release area 121-2 of the second flash memory array 120-2. Indicates whether a low is indicated. The main control circuit 170-2 responds to the chip selection signal ADD <18>, the reset signal RST, the command signal CMD, the address input pulse signal AIP, and the release signal ULK_2. The main control circuit 170-2 generates a corresponding start clock signal STCLK, end clock signal EDCLK, and reset signal RESET, and provides them to the address comparison circuit 160-2. The main control circuit 170-2 generates the erase enable signal EEN_2 or the program enable signal PEN_2 according to the value of the release signal ULK_2. In particular, when a program operation is requested by the command signal CMD and the release signal ULK_2 is generated at the active high level, the program enable signal PEN_2 is generated at the active level, and the program operation can be performed in the release region 121-2. Similarly, if an erase operation is requested by the command signal CMD and the release signal ULK_2 is generated at the active high level, the erase enable signal EEN_2 is generated at the active level, and the erase operation is performed in the release region 121-2. It becomes possible. The erase control circuit 150-2 generates an active level control signal CTL_2 in response to the active erase enable signal EEN_2. Similarly, the program control circuit 152-2 generates an active level control signal CTL_2 in response to the active program enable signal PEN_2. The activation control signal CTL_2 operates so that the word line control circuit 132_2 and the bit line control circuit 142_2 are enabled.

  The address comparison circuits 160-1 and 160-2 in the first and second flash memory devices 110-1 and 110-2 may be configured as shown in FIG. In particular, FIG. 2 shows an address comparison circuit 160-i that includes a start address register 210 and an end address register 250. The start address register 210 generates a latched start address LSA <18: 8> in response to the supplied start address STADD <18: 8>. . . 211-3 is included. The start address register 210 is responsive to the active high start clock signal STCLK and the active high reset signal RESET. The end address register 250 generates a plurality of D-type flip-flops 211-4, 211-5... That generate a latched end address LEA <18: 8> in response to the supplied end address EDADD <18: 8>. . . 211-6 included. The end address register 250 responds to the active high end clock signal EDCLK and the active high reset signal RESET.

  The latched start address LSA <18: 8> and the supplied row address ADD <18: 8> are input to the first address comparison circuit 230. When the supplied row address ADD <18: 8> is greater than or equal to the latched start address LSA <18: 8>, the first address comparison circuit 230 generates an active high level start enable signal STEN. Similarly, the latched end address LEA <18: 8> and the supplied row address ADD <18: 8> are input to the second address comparison circuit 270. When the supplied row address ADD <18: 8> is smaller than or equal to the latched end address LEA <18: 8>, the first address comparison circuit 270 generates an active high level end enable signal EDEN.

  An exemplary embodiment of the first address comparison circuit 230 is illustrated as including a plurality of stages, designated 230-1 through 230-n in FIG. These stages perform a function of comparing the latched start address bit and the corresponding bit of the supplied address in bit units and receiving a result signal from the previous stage. The first stage 230-1 includes an XOR (exclusive OR) logic gate 601, an inverter 603, and NAND gates 605, 607, and 609. The second stage 230-2 includes an XOR logic gate 611, an inverter 613, and NAND gates 615, 617, 619. The third stage 230-3 includes an XOR logic gate 621, an inverter 623, and NAND gates 625, 627, and 629. The final stage 230-n includes an XOR logic gate 631, an inverter 633, NAND gates 635, 637, 639 and an output inverter 640 that converts an active low signal output from the NAND gate 639 into an active high start enable signal STEN.

  An exemplary embodiment of the second address comparison circuit 270 is shown to include a plurality of stages, designated 270-1 through 270-N in FIG. These stages perform a function of comparing the latched end address bit and the corresponding bit of the supplied address with each other in a bit unit and receiving a result signal from the previous stage. The first stage 270-1 includes an XOR logic gate 701, an inverter 703, and NAND gates 705, 707 and 709. The second stage 270-2 includes an XOR logic gate 711, an inverter 713, and NAND gates 715, 717, and 719. The third stage 270-3 includes an XOR logic gate 721, an inverter 723, and NAND gates 725, 727, and 729. The last stage 270-N includes an XOR logic gate 731, an inverter 733, NAND gates 735, 737, 739, and an output inverter 740 that converts an active low signal output from the NAND gate 739 into an active high end enable signal EDEN. .

  The start enable signal STEN and the end enable signal EDEN are provided to an output logic unit that performs an AND operation. The output logic unit includes a 2-input NAND gate 280 and an inverter 290. Based on such a configuration of the output logic unit, the active high start enable signal STEN and the active high end enable signal EDEN are simultaneously input. As a result, the active high release signal ULK_i is generated. The generated active high release signal ULK_i is provided to the corresponding main control circuit 170-1 or 170-2, and the supplied row address ADD <18: 8> corresponds to the corresponding first memory array 120-1 or 120-2. The operation of identifying whether the current state is within the release area is executed.

  Each of the D-type flip-flops 211-i shown in FIG. 2 can be configured by a conventional method or by the form shown in FIG. In particular, each D-type flip-flop 211-i can be composed of a plurality of CMOS transmission gates 303, 305, 307, and 309. These transmission gates sequentially pass the data input signal DI through a plurality of intermediate storage nodes 304, 306, 308 to generate an output DQ. The CMOS transmission gates 303, 305, 307, and 309 are synchronized with a pair of clock signals generated by the inverter string in response to a clock signal CLK (for example, STCLK or EDCLK in FIG. 2). The inverter string includes a pair of inverters 301 and 302. The intermediate storage node and the output DQ of the D-type flip-flop 211-i can be reset if a reset signal R (for example, RESET in FIG. 2) is set to an active high level. The logic unit configured to reset the intermediate storage node and the output DQ includes inverters 311, 315 and 319 and NAND gates 313 and 317.

  Each of the main control circuits 170-1 and 170-2 includes a start clock generator 400a that generates a start clock signal STCLK and an end clock generator 400b that generates an end clock signal EDCLK. These start and end clock signals STCLK and EDCLK are received by the corresponding address comparison circuits 160-1 and 160-2 as described with reference to FIG. In FIG. 4, a start clock generator 400a and an end clock generator 400b respond to a command input signal CMD_in, an address input pulse AIP, and a reset signal RST, respectively. The address input pulse AIP and the reset signal RST are received by the corresponding main control circuits 170-1 and 170-2, and the command input signal CMD_in is generated in each main control circuit. The start clock generator 400a (and end clock generator 400b) generates a pair of complementary output signals (denoted as DQ1, DQ1B and DQ2, DQ2B) and a pair of D-type flip-flops that collectively operate as a pulse counter. 405 and 407 are included. The data input DI of the first D-type flip-flop 405 receives the feedback signal and the command input signal CMD_in extracted from the first complementary output signal DQ1B. The data input DI of the first D-type flip-flop 407 receives the feedback signal generated by the second complementary output DQ2B of the second D-type flip-flop 407. The clock input of the first D-type flip-flop 405 is responsive to the address input pulse AIP, and the clock input of the first D-type flip-flop 407 is responsive to the positive output DQ1 of the first D-type flip-flop 405. A Boolean logic unit is provided in the form of NAND gates 401 and 411, inverters 403, 409 and 413, and a pulse generator 415. The pulse generator 415 including the inverter 417 and the AND gate 419 has a relatively short period when the node A at the output terminal of the inverter 409 and the positive output DQ1 of the first D-type flip-flop 405 are simultaneously set to the logic 1 level. Active high clock pulses are generated. This active high clock pulse is indicated by either the start clock signal STCLK generated by the start clock generator 400a or the end clock signal EDCLK generated by the end clock generator 400b.

  The operations of the start clock generator 400a and the end clock generator 400b will be described more specifically with reference to the timing diagram of FIG. In particular, FIG. 5 illustrates that an active high command input signal CMD_in is generated in response to receiving an address loading command (hereinafter referred to as SASCMD). During the period when the command input signal CMD_in is activated at a high level, the reception of three consecutive address input pulses AIP causes the inverter 409 to overlap the logic 1 level signal at the positive output DQ1 of the first D-type flip-flop 405. A signal output A having a logic 1 level is generated. As a result, the output of inverter 413 converts from low to high, and pulse generator 415 generates a logic one pulse having the same duration as the delay provided by inverter 417.

  In addition, the generation of three consecutive address input pulses AIP under the conditions shown in FIG. 5 is electrically connected to the address bus shown in FIG. 1 by loading the continuous portion of the 19-bit address ADD <18: 0>. And a corresponding address register (not shown) having an output unit. In particular, each address input pulse AIP causes the corresponding 19-bit address of 8 bits to be loaded into the address register. Therefore, as shown in the timing diagram of FIG. 6, the first address input pulse AIP synchronizes the loading of ADD <7: 0>, and the second address input pulse AIP synchronizes the loading of ADD <15: 8>. The third address input pulse AIP synchronizes the loading of ADD <18:16>. These address bytes are loaded into the start address STADD loaded during the first series of three consecutive address input pulses AIP and the end address EDADD loaded during the second series of three consecutive address input pulses AIP. Correspond. In order to maintain the reduced pins in the packaged device, the three groups of address bits are contiguous to the 8I / O pins of the packaged device including the first and second flash memory devices 110-1, 110-2. Can be provided.

  The first series of three consecutive address input pulses AIP consists of 11 start addresses (ie STADD <18: 8>, where STADD <17: 8> is mapped to a row address in the flash memory array). A start pulse signal STCLK having a logic 1 pulse is generated so as to load the largest bit into the start address register 210 of FIG. The second series of three consecutive address input pulses AIP is a logic 1 that operates to load the 11 largest bits of the end address (ie, EDADD <18: 8>) into the end address register 250 of FIG. A pulse end clock signal EDCLK is generated. These start address bits and end address bits are 11 bits of the start address LSA <18: 8> latched at the output ends of the start and end address registers 210 and 250 and 11 of the latched end address LEA <18: 8>. Reflected in bits.

  Referring to the address comparator 160-i of FIG. 2 and the timing diagram of FIG. 7, an example of an instruction and address application method in the flash memory device system 100 completes the instruction if the address is in the release area. If the address is not in the release area, the instruction is blocked. In this embodiment, the program command PRG is received by the flash memory device system 100 along with three consecutive address input pulses AIP. These pulses load all 19-bit addresses ADD <18: 8> into system 100, where ADD <18> operates as a chip select signal, ADD <17: 8> operates as a row address, and ADD < 7: 0> operates as a column segment address. A portion of this overall address is provided to the first address comparator 160-1, where the latched start address LSA <18: 8> is identical to 08Fh (ie, 00010001111b) and the latched end address LEA <18: 8> is the same as 3FFh (ie, 01111111111b).

  The chip select signal (i.e., ADD <18>) is indicated as “0” because the first flash memory device 110-1 (not the second flash memory device 110-2) performs the above-described program operation. Selected. The eleven bits (ie, ADD <18: 8> = 1AFh = 001110111b) of the supplied address are provided to the first address comparison circuit 230 and the second address comparison circuit 270 in the first address comparator 160-1. The Since the supplied address is larger than the latched start address LSA <18: 8>, the first address comparison circuit 230 generates the start enable signal STEN at an active high level. Further, since the supplied address is smaller than the latched end address LEA <18: 8>, the end enable signal EDEN is generated at the active high level by the second address comparison circuit 270. As shown in FIGS. 2 and 7, these two active high enable signals STEN and EDEN are received by a Boolean logic unit that performs an AND operation and generates an active high release signal ULK_1.

  As shown in FIG. 1, the active high release signal ULK_1 is sent to the main control circuit 170-1 which operates to generate an active high program enable signal PEN_1 corresponding to the received command (CMD, ie, CMD = PRG). Entered. On the other hand, the value of the chip selection signal operates so as to select the first flash memory device 110-1 and not the second flash memory device 110-2. A start enable signal STEN and an end enable signal EDEN are generated. Therefore, the inactivation releasing signal ULK_2 that operates to disable the main control circuit 170-2 is generated, and the program enable signal PEN_2 maintains the inactive low level.

  The generation of the active high level program enable signal PEN_1 is performed by enabling the program control circuit 152-1 to generate the active high control signal CTL_1. The generation of the active high control signal CTL_1 is such that the program operation continues at the row specified by the address ADD <17: 8> in the row first flash memory array 120-1. A similar operation can be performed by the control circuit in response to the erase operation. However, a read command executed in the release area or the lock area in the flash memory array does not require the selective generation of the corresponding enable signal by the main control circuit.

  The above-described operation performed by the flash memory device system 100 will be described with reference to the flowchart of FIG. In particular, FIG. 10 illustrates a method 500 of operating a flash memory device that includes setting a release region in the flash memory array while performing a power up and / or reset operation. As indicated by blocks 502, 504, and 506, each power-up and / or reset operation within the flash memory device may be performed by loading start and end addresses into the address compare circuit to delimit the release region within the flash memory array. The step of setting may be included. If the boundary of the release area is set, the flash memory device system can start executing normal program, erase and / or read operations in response to the corresponding command and address. The steps may include loading the next instruction (eg, read, program (write) or erase) and corresponding address (eg, chip select, row address and column address) into the flash memory device (block 508). . Next, a check step is performed to determine whether the received command is a read command (block 510). If the received command is a read command, a general read operation is performed (block 514). Control then returns to block 508. However, if the received instruction is not a read instruction, there is a check stage to determine whether the address associated with the instruction is within or outside the boundary of the release area in the corresponding flash memory array (i.e., outside). Performed (block 512). If the address is outside the boundary of the release area, the input instruction (ie, a program or erase instruction) is blocked (block 516) and control returns to block 508. However, if the address is within the boundary of the release area, an activation release signal (ie, ULK = 1) is generated (block 518). If the instruction is an erase instruction, the deactivation signal generates an active erase enable signal (ie, EEN = 1) and an erase operation is performed at the specified address (blocks 520, 522, and 528). On the other hand, if the instruction is a program instruction, the deactivation signal generates an active program enable signal (ie, PEN = 1), and a program operation is performed at a specified address (blocks 520, 524, and 526). . If a program or erase operation is performed, control returns to block 508 to process the next instruction and address.

  Although the present invention has been described based on one embodiment shown in the drawings, this is merely an example, and those skilled in the art can make various modifications and other equivalent embodiments. You will understand a certain point. For example, in this specification, an example in which data of a total of 32 bits is divided in units of 8 bits is described, but such a bit unit and the total number of bits can be arbitrarily changed. Therefore, the technical scope of the present invention should be determined based on the description of the claims.

  According to the present invention, the flash memory device can be used in various memory systems such as compact flash (registered trademark), smart media, large capacity memory such as a PC card, MMC, secure digital, and memory stick.

1 is a block diagram of a flash memory device according to an embodiment of the present invention. FIG. FIG. 2 is a circuit diagram of an address comparison circuit used in the flash memory device system of FIG. 1. FIG. 3 is a circuit diagram of a D-type flip-flop used in the address comparison circuit of FIG. 2. It is a circuit diagram of the clock generator used for the main control circuit of FIG. FIG. 5 is a timing diagram showing an operation of the clock generator of FIG. 4. FIG. 3 is a timing chart showing an operation of loading a start address (STADD) and an end address (EDADD) into the address comparison circuit of FIG. 2. FIG. 3 is a timing diagram illustrating an operation of generating a release signal by the address comparison circuit of FIG. 2 and an operation of generating a program enable signal by the main control circuit of FIG. 1. FIG. 3 is a circuit diagram of a first address comparator used in the address comparison circuit of FIG. 2. FIG. 3 is a circuit diagram of a second address comparator used in the address comparison circuit of FIG. 2. 2 is a flowchart showing an operation performed by the flash memory device system of FIG. 1.

Explanation of symbols

100 flash memory systems 110-1, 110-2 first and second flash memory devices 120-1, 120-2 first and second flash memory arrays 121-1, 121-2 release areas 123-1, 123-2 Lock regions 132-1 and 132-2 First and second word line control circuits 130-1 and 130-2 First and second row decoders 140-1 and 140-2 First and second column decoders 142-1, 142-2 First and second bit line control circuits 150-1, 150-2 Erase control circuits 152-1, 152-2 Program control circuits 160-1, 160-2 Address comparison circuits 170-1, 170-2 Main Control circuit

Claims (20)

An address comparison circuit configured to indicate whether the supply address supplied in association with the first operation is inside or outside the release area of the flash memory array;
Responsive to an indication that the supply address is outside the release region of the flash memory array detected by the address comparison circuit, the first operation in the flash memory array is prevented from being executed. And a control circuit. The address comparison circuit includes:
A start address register configured to latch a supply start address supplied in synchronization with the start clock signal;
The flash memory device according to claim 1, further comprising: an end address register configured to latch a supply end address supplied in synchronization with the end clock signal. The address comparison circuit includes:
A start address comparator configured to receive a latched start address from the start address register;
The flash memory device of claim 2, further comprising an end address comparator configured to receive a latched end address from the end address register. The start address comparator includes a Boolean logic unit configured to compare the latched start address with the supply address;
4. The flash memory device of claim 3, wherein the end address comparator includes a Boolean logic unit configured to compare the latched end address with the supply address.   The address comparator is configured to generate a release signal indicating whether the supply address associated with the first operation is inside or outside a release area of the flash memory array. The flash memory device according to claim 4.   The flash memory device according to claim 5, wherein the control circuit is responsive to the release signal. The control circuit includes:
The flash memory device of claim 1, further comprising a first clock generator comprising a pulse counter configured to generate a start clock signal in response to receiving a plurality of consecutive address input pulses. . The flash memory device includes:
8. The flash memory device of claim 7, further comprising a first address register configured to latch a start address of a release area in synchronization with the start clock signal. The control circuit includes:
The flash memory device of claim 1, further comprising a first clock generator configured to generate a start clock signal in response to receiving one or more address input pulses. A flash memory array;
A word line control circuit electrically connected to a word line of the flash memory array and responsive to a command control signal;
A bit line control circuit electrically connected to a bit line of the flash memory array and responsive to the command control signal;
If the supply row address to be supplied is within the release area, an active level release signal is generated, and if the supply row address is outside the release area, an inactive level release signal is generated to generate an instruction and An address comparison circuit configured to indicate whether the associated supply row address is internal or external to a release area of the flash memory array;
A main control circuit configured to generate a command enable signal in response to the command and the release signal;
And a command control circuit configured to generate the command control signal in response to the command enable signal.   The main control circuit is responsive to an address input pulse signal received from one pin of the flash memory device, and the flash memory device is synchronized with first and second leading edges of the address input pulse signal. The flash memory device of claim 10, wherein the flash memory device is configured to latch first and second portions of the supply row address.   The main control circuit is configured to generate a comparison reset signal in response to a leading edge of a reset signal received by the flash memory device, and the address comparison circuit is responsive to the comparison reset signal. The flash memory device according to claim 10. The address comparison circuit includes:
A start address register configured to latch a supply start address supplied in synchronization with the start clock signal;
11. The flash memory device according to claim 10, further comprising: an end address register configured to latch a supply end address supplied in synchronization with the end clock signal. The address comparison circuit includes:
A start address comparator configured to receive a latched start address and the supply row address from the start address register;
The flash memory device of claim 13, further comprising: an end address comparator configured to receive a latched end address and the supply row address from the end address register. The start address comparator includes a Boolean logic configured to compare the latched start address to the supply row address;
15. The flash memory device of claim 14, wherein the end address comparator includes a Boolean logic unit configured to compare the latched end address with the supply row address.   The main control circuit is configured to generate the start clock signal in response to a first sequence of address input pulses and to generate the end clock signal in response to a second sequence of address input pulses. 14. The flash memory device according to claim 13, wherein: Of the first plurality of consecutive address input pulses, at least first and second portions of the start address associated with the release region of the flash memory array are loaded into the flash memory device in synchronization with each pulse. Stages,
Loading at least first and second portions of the end address associated with the release region into the flash memory device in synchronization with each of the second plurality of consecutive address input pulses;
At least first and second portions of a supply address supplied in association with an erase or program command are loaded into the flash memory device in synchronization with each of a plurality of third consecutive address input pulses. Stages,
Comparing the supply address with the start and end addresses to determine whether the erase or program command is performed in the release area. The comparison step includes
18. The flash of claim 17, comprising evaluating whether the supply address is greater than or equal to the start address and evaluating whether the supply address is less than or equal to the end address. A method of operating a memory device. The comparison step includes
18. The flash of claim 17, comprising generating a release signal having a first level that enables execution of the erase or program instruction and a second level that prevents execution of the erase or program instruction. A method of operating a memory device. Loading a flash memory device with a start address associated with a release area of the flash memory array;
Loading an end address associated with the release area into the flash memory device;
Loading a supply address supplied in association with an erase or program instruction into the flash memory device;
Comparing the supply address with the start address to determine whether the supply address is greater than or equal to the start address;
Comparing the supply address with the end address to determine if the supply address is less than or equal to the end address;
Generating an activation level release signal in response to a determination that the supply address is greater than or equal to the start address and the supply address is less than or equal to the end address. A method of operating a flash memory device.

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