KR19990065224A - Flash memory device detects program pass / fail internally - Google Patents

Abstract

A nonvolatile memory device according to the present invention comprises at least two mats each having a plurality of memory cells arranged in a matrix of rows and columns; When the program / read operation for one of the mats is performed, the program / read operation for the other mat is not performed; A plurality of page buffers, each connected to columns corresponding to the mats, for sensing data of memory cells addressed during a read operation and latching data to be written during a program operation; A plurality of data lines respectively corresponding to the mats; Column decoders electrically connecting the addressed columns and the corresponding data lines of each mat according to an address for selecting a plurality of columns of the mats corresponding to the data lines during a program / read operation; And a sense data transferred on data lines through a column decoder corresponding to the selected mat as a read operation for a program verifying operation is performed after a program operation is performed on a selected mat among the mats. And a pass / fail flag generation circuit that receives write data transferred from the page buffers on the corresponding data lines through a column decoder corresponding to the mat and generates a program pass / fail flag signal.

Description

FLASH MEMORY DEVICE CAPABLE OF DETECTING INTERNALLY PROGRAM PASS / FAIL

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to flash memory devices having electrically erasable and programmable ROM cells.

Use of the device in non-volatile memory devices, typically with semiconductor memory, in particular with electrically erasable and programmable ROM cells. Is mainly used for storing a lot of data, such as a hard disk, a film substitute for a digital camera. Hereinafter, the nonvolatile memory device having the EEPROM cells is called a flash memory device.

In the NAND type flash memory device, the potential of the bit line corresponding to the cell to be programmed is biased at 0V, and the potential of the bit line corresponding to the cell whose program is prohibited is biased by the power supply voltage. At this time, the loading of data is performed in units of 512 bytes in a data latch and sensing circuit (or page buffer) connected to every bit line. If a program voltage is applied to the word line after data loading, the program operation is performed.

The program operation consists of an iterative loop of read operation for the program verify operation which determines whether the desired data has been written to the cell by the above-described actual program operation. This operation is repeated until all EEPROM cells have been program passed.

While the program operation is performed, fast cells are programmed even if the gates of the program inhibited EEPROM cells are also applied with the program voltage and the bit lines corresponding to the cells prohibited for program inhibition are biased to the supply voltage. ) Has a threshold voltage corresponding to the program state in the erased state. That is, fast cells among the program inhibited cells are programmed, and are called program interference.

The above-described type of fail is not detectable in the program verifying step in the program section, and may be detected by comparing the first loaded data with the programmed data after the program operation is performed. In general, in a system having the NAND flash memory device, after the program operation is performed, the first loaded data and the programmed data are compared. This comparison process takes a lot of time, which is another load on the system.

Accordingly, an object of the present invention is to provide a flash memory device capable of internally detecting a program fail due to program interference.

1 is a block diagram showing a circuit configuration of a flash memory device according to the present invention.

* Explanation of symbols on the main parts of the drawings

100, 110: Matt 120, 130: Row decoder

140, 150: page buffer 160, 170: column decoder

180: pass / fail flag generation circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, at least two mats each having a plurality of memory cells arranged in a matrix of rows and columns; When the program / read operation for one of the mats is performed, the program / read operation for the other mat is not performed; A plurality of page buffers, each connected to columns corresponding to the mats, for sensing data of memory cells addressed during a read operation and latching data to be written during a program operation; A plurality of data lines respectively corresponding to the mats; Column decoders electrically connecting the addressed columns and the corresponding data lines of each mat according to an address for selecting a plurality of columns of the mats corresponding to the data lines during a program / read operation; And a sense data transferred on data lines through a column decoder corresponding to the selected mat as a read operation for a program verifying operation is performed after a program operation is performed on a selected mat among the mats. And a pass / fail flag generation circuit that receives write data transferred from the page buffers on the corresponding data lines through a column decoder corresponding to the mat and generates a program pass / fail flag signal.

In this embodiment, the pass / fail flag generation circuit includes a plurality of XOR gates respectively connected between data lines corresponding to the mats.

(Action)

With such a device, a separate latch may be provided inside the chip to compare data loaded in the chip with data of a cell in which the program is performed after the program operation.

(Example)

Hereinafter, reference will be made in detail with reference to FIG. 1.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those of ordinary skill in the art, the present invention may be practiced only by the above description without these details.

1 is a block diagram illustrating a configuration of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a nonvolatile memory device includes two mats 100 and 110. Each of the mats 100 and 110 is a plurality of memory cells arranged in a matrix of rows and columns, as well known to those skilled in the art, although not shown in the figures. And a plurality of word lines extending along the lines, and a plurality of bit lines extending along the columns. The memory cells are electrically erasable and programmable ROM cells.

In this embodiment, the bit lines are 4k, that is, 4096, and the input / output structure (I / O organization) is x8. Each of the mats 100 and 110 is divided into eight memory blocks according to the input / output casting. That is, one memory block corresponds to one input / output and is composed of 512 bit lines.

Referring back to FIG. 1, a nonvolatile memory device according to the present invention includes row decoders 120 and 130 and data sensing and latch circuits corresponding to the mats 100 and 110, respectively. Data sensing and latch circuits (or page buffers 140 and 150), column decoders 160 and 170.

The data sensing and latch circuits 140 and 150 corresponding to the mats 100 and 110 are page buffers corresponding to the bit lines of the corresponding mats 100 and 110, respectively. It consists of. Each page butter senses data stored in an addressed memory cell during a read operation and latches data to be written during a program operation.

The page buffers are connected to the column decoders 160 and 170 which accept a column address from the outside and perform a coding operation. The column decoders 160 and 170 are connected to data lines DL0a-DL7a and DL0b-DL7b, respectively, assigned to respective inputs and outputs. The row decoders 120 and 130 corresponding to the mats 100 and 110 select one of word lines corresponding to the mats 100 and 110, and drive the selected word line at a voltage according to an operation mode.

Referring back to FIG. 1, a nonvolatile memory device according to the present invention is input to data lines DL0a-DL7a and DL0b-DL7b corresponding to the mats 100 and 110, respectively. A pad / fail flag generation circuit for accepting the outputs of the eight exclusive OR gates G1-G4 and the gates G1-G4 to which terminals are connected to determine whether a program operation has been performed (pass / fail flag generating circuit) 180.

In the structure of the nonvolatile memory device according to the present invention, the data lines DL0a-DL7a and DL0b-DL7b corresponding to each of the mats 100 and 110 are loaded when data for a program is loaded. The same data is loaded into. Each column decoder 160 and 170 corresponding to each of the mats 100 and 110 receives the same column decoding, and the same data is loaded into the corresponding page buffers. That is, the same data is loaded into the page buffer of the selected mat and the page buffers of the non-selected mat.

The program operation proceeds for the selected mat of the two mats 100 and 110, and the program operation proceeds based on the data loaded in the page butters of the selected mat. At this time, the data in the page buffer of the unselected mat is kept latched while the program operation is performed.

After the program operation for the selected mat is completed, a read operation for detecting whether program inhibited data of the selected mat is programmed is performed. In this case, after the read operation proceeds with page sensing of the selected word line of the mat where the program operation was performed, the sensed data is latched in the page buffers of the selected mat. The column decoders 160 and 170 corresponding to the mats 100 and 110 are then compared to compare the sensed data and data latched in page buffers corresponding to the unselected mat. A thermal coding operation is performed by

Then, the data of the page buffers provided on the data lines DL0a-DL7a and DL0b-DL7b corresponding to the mats 100 and 110 are XOR gates G1- ( G4). For example, if the states on the corresponding data lines DL0a-DL7a and DL0b-DL7b are different, the program operation may fail, and if the same, the program operation may be determined to have passed. Finally, the pass / fail flag generation circuit 180 generates a pass / fail flag signal according to the result determined by the XOR gates. Therefore, the final program pass / fail state can be determined by the device itself through a comparison process between the programmed data and the loaded data after the program operation is completed.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, since a separate latch is provided in the chip, after the program operation, the data loaded in the chip and the data of the cell in which the program is performed may be compared.

Claims (2)

At least two mats each having a plurality of memory cells arranged in a matrix of rows and columns; When the program / read operation for one of the mats is performed, the program / read operation for the other mat is not performed; A plurality of page buffers, each connected to columns corresponding to the mats, for sensing data of memory cells addressed during a read operation and latching data to be written during a program operation; A plurality of data lines respectively corresponding to the mats; Column decoders electrically connecting the addressed columns and the corresponding data lines of each mat according to an address for selecting a plurality of columns of the mats corresponding to the data lines during a program / read operation; And a sense data transferred on data lines through a column decoder corresponding to the selected mat as a read operation for a program verifying operation is performed after a program operation is performed on a selected mat among the mats. And a pass / fail flag generation circuit that receives the write data transferred from the page buffers on the corresponding data lines through a column decoder corresponding to the mat and generates a program pass / fail flag signal. The method of claim 1, The pass / fail flag generation circuit includes a plurality of XOR gates respectively connected between data lines corresponding to the mats.