JP2005009998A - Infrared solid image pickup element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an infrared solid image pickup element with high sensitivity and low noise. <P>SOLUTION: The infrared solid image pickup element is formed on a semiconductor substrate. It comprises an infrared absorbing part 1 for absorbing and converting incident infrared light to heat, an infrared detector 2 for converting the temperature variation due to heat generated in the infrared absorbing part 1 to electric signal, and at least one support wiring 312 which supports the infrared detector 2 apart from the semiconductor substrate 300 and serves as I/O wiring of the infrared detector 2. The infrared detector 2 has a first and a second vertical pn junction diodes 306 and 308 arranged face to face in the direction approximately perpendicular to the semiconductor substrate 300 putting an element separation region in between, and an embedded electrode layer 317 consisting of metal silicide formed along the bottom of the element separation region and conducting each end of the first and the second vertical pn junction diodes 306 and 308. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an infrared solid-state imaging device and a method for manufacturing the same, and particularly to a highly sensitive and non-cooling infrared solid-state imaging device.
[0002]
[Prior art]
In recent years, research and development of uncooled infrared solid-state imaging devices that do not require cooling to a nitrogen temperature have been actively conducted. The non-cooling type infrared solid-state imaging device converts incident infrared rays having a wavelength of around 10μ into heat by the infrared absorption part, and converts the temperature change of the heat sensitive part caused by the weak heat into an electrical signal by the thermoelectric conversion part, Infrared image information is obtained by reading out this electrical signal.
[0003]
Since this type of uncooled infrared solid-state imaging device does not require a cooling device, it can be reduced in size and on-chip, and the cost is being reduced with consumer applications in mind. Against this background, an uncooled infrared solid-state imaging device using a silicon pn junction diode that can share most of the manufacturing process with a conventional CMOS LSI has attracted attention.
[0004]
However, in this type of silicon pn junction diode type, dV / dT, which is a sensitivity index of the solid-state imaging device, is low, and it is necessary to further improve the S / N ratio.
[0005]
The noise component of the pn junction diode includes 1 / f noise due to the roughness and surface level of the silicon substrate surface, thermal noise depending on the amount of bias current, and shot noise due to variation in the amount of current passing through the pn junction. is there. Among these, 1 / f noise can be avoided by adopting a vertical pn junction structure having a silicon bulk as a current path, and an S / N ratio can be improved.
[0006]
Moreover, in the said non-cooling type infrared solid-state image sensor, the infrared detection part which consists of the thermosensitive conversion part (infrared absorption structure) which converts incident infrared rays into heat, and the thermoelectric conversion part which converts the heat | fever into an electrical signal thermally Separation and improvement of thermoelectric conversion efficiency are essential for improving infrared sensitivity.
[0007]
Therefore, the infrared solid-state imaging device is mounted in a vacuum package, and there is a method for suppressing diffusion of heat to the support substrate by etching and removing the silicon substrate and the element isolation oxide film around the infrared detection unit. Has been taken.
[0008]
At this time, the heat transport from the infrared detection unit to the support substrate is dominated by heat conduction through the support structure that supports the infrared detection unit on the hollow structure inside the support substrate, and from the material with low thermal conductivity. The leg-shaped support structure is designed to be thinner and longer as long as it can be designed.
[0009]
As a conventional example, FIG. 26 shows an example in which a polysilicide having a silicon vertical pn junction diode as a thermoelectric conversion means and having a low thermal conductivity is applied to a support leg in order to reduce heat transport of the infrared detection unit. This will be described with reference to a structural sectional view (see Patent Document 1).
[0010]
The infrared detection pixel has an infrared absorption layer 103, 104, a pn junction diode 106 in an SOI layer 105 formed for thermoelectric conversion on a hollow structure 102 formed in a single crystal silicon support substrate 101, A solid-state image sensor unit 108 including a buried silicon oxide film layer 107 supporting the SOI layer 105, and supporting the solid-state image sensor unit 108 on the hollow structure 102 and outputting an electric signal from the solid-state image sensor unit 108 And a connecting portion (not shown) for connecting the solid-state imaging device portion 108 to the vertical signal line and the horizontal address line.
[0011]
The support portion 109 includes a support wiring structure and support insulating structures 110, 111, and 112 that protect the support wiring structure. The support wiring structure is a stacked structure of a polycrystalline silicon region 113 and a metal silicide region 114. The solid-state image sensor unit 108 and the support unit 109 are provided on the hollow structure 102 and thermally separated from the silicon support substrate 101, whereby the temperature of the solid-state image sensor unit 108 is efficiently modulated by incident infrared rays. Yes.
[0012]
In the infrared sensor disclosed in Patent Document 1, the gate electrode of the MOS transistor in the peripheral circuit and the process of forming the support wiring are shared, thereby making it possible to maximize the process consistency and to obtain a high-sensitivity support structure. It can be manufactured well at low cost. In addition, by using polysilicon and titanium silicide having low thermal conductivity as compared with metal as the support wiring, the thermal separation property of the solid-state imaging element portion is improved while keeping the electric resistance as the input / output electrode low.
[0013]
However, since the conventional uncooled infrared solid-state imaging device uses gate polysilicon as polysilicon to simplify the process, the thickness of the polysilicon is reduced to prevent boron penetration of the pMOS gate electrode. This is not easy, and the cross-sectional area of the support wiring is reduced, that is, the heat separability of the solid-state imaging device portion is limited.
[0014]
Further, a temperature detector unit formed of a plurality of serially connected silicon pn junction diodes formed corresponding to each pixel arranged two-dimensionally on the SOI substrate and biased in a forward direction, and temperature detection An infrared solid-state imaging device having a cavity portion formed in each region where a vessel portion is formed and a support mechanism made of a material having a high thermal resistance for supporting the temperature detector portion on the substrate on the cavity portion is disclosed. (See Patent Document 2).
[0015]
In the silicon pn junction diode, a p-layer and an n-layer are alternately formed on a single crystal silicon layer to form a plurality of silicon pn-junction diodes. Yes. Further, platinum silicide formed in a self-aligned manner in the wiring opening is used as the metal wiring for short circuit.
[0016]
According to the infrared solid-state imaging device, silicon pn junction diodes can be arranged at high density in a region having a limited area in a pixel, and the number of silicon pn junction diodes is increased to achieve high sensitivity. Can do. Also, the process is simplified by using platinum silicide formed in a self-aligned manner in the wiring opening as the metal wiring for short-circuiting.
[0017]
However, in the infrared solid-state imaging device described in Patent Document 2, a current component flowing in the vicinity of the surface of the SOI substrate is present in the current flowing through the silicon pn junction diode, and therefore 1 caused by the roughness and surface level of the substrate surface. A large amount of / f noise component is contained in the detection signal, and the S / N ratio is degraded.
[0018]
[Patent Document 1]
JP 2002-107224 A
[Patent Document 2]
International Publication WO99 / 31471
[0019]
[Problems to be solved by the invention]
As described above, in the conventional example, by using polysilicon and titanium silicide, which have lower thermal conductivity than metal, as the support wiring, the electrical resistance of the input / output electrode is kept low, while the solid-state imaging device portion. The heat separability was improved. At the same time, by forming the gate electrode of the MOS transistor of the peripheral circuit and the support wiring in the same layer, the compatibility with the conventional LSI process is maximized, and a high-sensitivity support structure is manufactured with high yield and low cost. It was possible.
[0020]
Conventionally, however, gate polysilicon has been used as polysilicon to simplify the process, so boron penetration of the pMOS gate electrode must be suppressed, and it is not easy to reduce the thickness of the polysilicon film. There has been a limit to the reduction in the cross-sectional area of the wiring, that is, the thermal separability of the solid-state imaging device.
[0021]
In addition, there is a problem in that there is a current component flowing near the silicon substrate surface, and the 1 / f noise component cannot be completely removed, and the S / N ratio decreases.
[0022]
The present invention has been made in view of these points, and an object thereof is to provide an infrared solid-state imaging device with high sensitivity and low noise, and a method for manufacturing the same.
[0023]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides an infrared absorption portion that is formed on a semiconductor substrate and absorbs incident infrared rays and converts the infrared rays into heat, and changes in temperature due to heat generated in the infrared absorption portions are converted into electrical signals. An infrared detection unit having a thermoelectric conversion unit to convert; and at least one support that supports the infrared detection unit spaced apart from the semiconductor substrate and has an input / output wiring of the infrared detection unit. The thermoelectric converters are respectively formed in a direction substantially orthogonal to the surface of the semiconductor substrate, and are arranged in a direction substantially opposite to the surface of the semiconductor substrate across the element isolation region, and the first and second vertical pn At least one structure having a junction diode and a conductive layer formed along the bottom surface of the element isolation region and conducting each one end of the first and second vertical pn junction diodes. .
[0024]
The present invention also includes an infrared absorption unit that is formed on a semiconductor substrate and absorbs incident infrared rays to convert it into heat, and a thermoelectric conversion unit that converts a temperature change caused by heat generated in the infrared absorption unit into an electrical signal. An infrared solid-state imaging device comprising: an infrared detection unit including: an infrared detection unit; and at least one support that supports the infrared detection unit apart from the semiconductor substrate and includes an input / output wiring of the infrared detection unit. An SOI substrate in which a single crystal silicon substrate, a buried insulating layer, and a single crystal silicon layer are sequentially stacked is used as the semiconductor substrate, and the single crystal silicon layer remains in a part of the single crystal silicon layer. Etching away to form a first groove for the first element isolation region, and vertical pn contact as a thermoelectric conversion part located on both sides of the first groove and the first groove Removing the single crystal silicon layer in the second element isolation region formed adjacent to the diode region to form a second groove; and embedding an insulating material in the first and second grooves; Impurity ions are implanted into the single crystal silicon layer in the region of the infrared detection unit, and the first n is sandwiched between the first element isolation regions. ⁺ Electrode region and first p ⁺ Forming an electrode region; and implanting impurity ions into the single-crystal silicon layer in the region of the infrared detection unit to form the first n ⁺ A second p below the electrode region ⁺ Forming an electrode region, wherein the first p ⁺ A second n below the electrode region ⁺ Forming an electrode region; forming an input / output wiring of the support on the second element isolation region; removing an insulating material embedded in the first groove; Forming a first insulating layer on a sidewall of the element isolation region; and forming a second p on the bottom surface of the first element isolation region. ⁺ An electrode region and the second n ⁺ Forming a bottom electrode layer connecting the electrode region and the first n ⁺ An electrode region and the first p ⁺ Forming a surface electrode layer on the surface of the electrode region; forming a second insulating layer that embeds the first element isolation region; and separating the infrared detection unit from the semiconductor substrate; and Forming at least one support for supporting the detection unit.
[0025]
Also, an infrared detection unit formed on a semiconductor substrate and having an infrared absorption unit that absorbs incident infrared rays and converts the infrared rays into heat, and a thermoelectric conversion unit that converts a temperature change caused by the heat generated in the infrared absorption units into an electrical signal. An infrared solid-state imaging device comprising: at least one support that supports the infrared detection unit spaced apart from the semiconductor substrate and has input / output wirings of the infrared detection unit. Then, an SOI substrate in which a single crystal silicon substrate, a buried insulating layer and a single crystal silicon layer are sequentially stacked is used as the semiconductor substrate, and a part of the single crystal silicon layer is removed by etching so that the single crystal silicon layer remains. Forming a first groove for the first element isolation region and a second groove for the input / output wiring, and thermoelectric elements located on both sides of the first groove and the first groove. Forming a third groove by removing the single crystal silicon layer in the second element isolation region formed adjacent to the vertical pn junction diode region as the replacement portion and in the region other than the input / output wiring portion Burying an insulating material in the first, second and third trenches, and implanting impurity ions into the single crystal silicon layer in the region of the infrared detecting portion to sandwich the first element isolation region At the first n ⁺ Electrode region and first p ⁺ Forming an electrode region; and implanting impurity ions into the single-crystal silicon layer in the region of the infrared detection unit to form the first n ⁺ A second p below the electrode region ⁺ Forming an electrode region, wherein the first p ⁺ A second n below the electrode region ⁺ Forming an electrode region; removing an insulating material embedded in the first trench; forming a first insulating layer on a sidewall of the first element isolation region; and the first element isolation. A bottom electrode layer is formed on each of the bottom of the region and the input / output wiring portion, and the first n ⁺ Electrode region and first p ⁺ Forming a surface electrode layer on the surface of the electrode region, connecting the diode and the input / output wiring portion to each other, forming a second insulating layer for embedding the first element isolation region, and the infrared ray Forming at least one support for separating the detection unit from the semiconductor substrate and supporting the infrared detection unit.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an infrared solid-state imaging device and a manufacturing method thereof according to the present invention will be specifically described with reference to the drawings.
[0027]
(First embodiment)
FIG. 1 is a plan view of a first embodiment of an infrared solid-state imaging device according to the present invention, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.
[0028]
As shown in FIGS. 1 and 2, the infrared solid-state imaging device of the present embodiment is generated by an infrared absorption unit 1 that absorbs incident infrared light formed on an SOI substrate and converts it into heat, and the infrared absorption unit 1. The infrared detector 2 that converts the temperature change caused by the heat into an electrical signal, and the infrared detector 2 is supported at a distance from the semiconductor substrate 300 and at least one support that also serves as an input / output wiring of the infrared detector 2 Wiring 312.
[0029]
The infrared detection unit 2 includes first and second vertical pn junction diodes 306 and 308 that are arranged to face each other with a first element isolation region in a direction substantially orthogonal to the semiconductor substrate 300, and the first and second Embedded electrode layer 317 made of metal silicide for conducting each one end of each of the vertical pn junction diodes 306 and 308.
[0030]
The first vertical pn junction diode 306 is formed in order from the top in the depth direction of the substrate. ⁺ Electrode layer 307 and p ⁺ The second vertical pn junction diode 308 is formed in order from the top in the depth direction of the substrate. ⁺ Electrode layer 309 and n ⁺ An electrode layer 311. P of the first vertical pn junction diode 306 ⁺ N of electrode layer 310 and second vertical pn junction diode 308 ⁺ The electrode layer 311 is connected by a buried electrode layer 317 made of metal silicide.
[0031]
N of the first vertical pn junction diode 306 ⁺ The electrode layer 307 and the support wiring 312 are connected via the contact 320 and the metal wiring layer 321, and the second vertical pn junction diode p ⁺ The electrode layer 309 and the support wiring 312 are connected to each other through a contact 320 and a conductive layer 321.
[0032]
In the present embodiment, the first and second vertical silicon pn junction diodes 306 and 308 arranged opposite to each other with the first element isolation region 303 interposed therebetween are directly connected in series by the buried electrode layer 317 made of metal silicide. The diffusion layer wiring region that connects the electrode existing at the bottom of the substrate and the contact diffusion layer region existing on the substrate surface, which has been a problem with conventional vertical pn junction diodes, becomes unnecessary, and infrared solid-state imaging is achieved by reducing parasitic resistance. An infrared solid-state imaging device having a high S / N ratio can be realized by improving the sensitivity as an element and reducing the 1 / f noise component. In addition, since the contact diffusion layer on the substrate surface, which has been conventionally required, is not required, the element area can be further reduced.
[0033]
FIG. 3 is a cross-sectional view showing a manufacturing process of an embodiment of the infrared solid-state imaging device according to the present invention. In this embodiment, a so-called SOI substrate in which a buried silicon oxide film layer 301 and a single crystal silicon layer 302 are sequentially stacked on a single crystal silicon support substrate 300 is used as a semiconductor substrate. The thickness of the buried silicon oxide film 301 and the single crystal silicon layer 302 is not particularly limited. For example, in the SOI substrate of FIG. 3, the thickness of the buried silicon oxide film is 150 nm, the thickness of the single crystal silicon layer is 400 nm, p-type impurity concentration 2 × 10 ¹⁶ / Cm ³ It is said.
[0034]
Next, an element isolation region is formed by STI (Shallow-Trench-Isolation). First, the first element isolation region 303 is patterned by photolithography, and the single crystal silicon layer 302 is etched by RIE (Reactive-Ion-Etching) so that at least a part of the single crystal silicon layer 302 remains. One opening 341 is formed (FIG. 4). For example, in this embodiment, the single crystal silicon layer 302 is etched by 300 nm.
[0035]
Further, the second element isolation region 304 is patterned by a photolithography technique, and the single crystal silicon layer 302 is entirely etched by RIE to form the second opening 342.
[0036]
Next, an element isolation silicon oxide film 305 is embedded in the first and second openings 341 and 342 by CVD (Chemical-Vapor-Deposition) and planarized by CMP (Chemical-Mechanical-Polishing) (FIG. 2).
[0037]
Next, first and second vertical pn junction diodes 306 and 308 to be thermoelectric conversion elements are formed. First, n of the first vertical pn junction diode 306 ⁺ The electrode region 307 is patterned by a photolithography technique, and n is formed in a region close to the surface of the single crystal silicon substrate 302 by ion implantation. ⁺ An electrode region 307 is formed. As the injection conditions, for example, 40 keV, 5 × 10 ¹⁵ / Cm ² It is desirable to implant arsenic ions at a degree.
[0038]
In addition, the p of the second pn junction diode 308 ⁺ The electrode region 309 is patterned by a photolithography technique, and p is formed in a region close to the surface of the single crystal silicon substrate 302 by ion implantation. ⁺ An electrode region 309 is formed. As an injection condition, for example, boron fluoride is 7 keV, 5 × 10 ¹⁵ / Cm ² Degree is desirable.
[0039]
Next, p of the first pn junction diode 306 ⁺ The buried electrode region 310 is patterned by a photolithography technique, and is ion-implanted to a depth near the bottom of the first element isolation region 303. ⁺ A buried electrode region 310 is formed. As the injection conditions, for example, boron is 130 keV, 4.5 × 10 ¹⁴ / Cm ² Degree is desirable.
[0040]
In addition, n of the second pn junction diode 308 ⁺ The buried electrode region 311 is patterned by a photolithography technique, and is ion-implanted to a depth near the bottom of the first element isolation region 303. ⁺ A buried electrode region 311 is formed. As an injection condition, for example, phosphorus is 280 keV, 2 × 10 ¹⁴ / Cm ² The degree is desirable (FIG. 5).
[0041]
Next, the support wiring 312 is formed. The process of forming the support wiring 312 can be shared with the process of forming the gate electrode of the MOS transistor used for the peripheral circuit, and the process can be simplified. First, a polysilicon film having a thickness of 250 nm is formed by CVD, and then a support wiring 312 is formed by photolithography and RIE.
[0042]
Next, a silicon nitride film having a thickness of 100 nm is formed on the entire surface of the substrate by CVD, and etched back by RIE to form a sidewall 313 at the stepped portion by the support wiring 312 (FIG. 6).
[0043]
Next, silicide formation is performed on the substrate surface electrodes and buried electrodes of the first and second vertical pn junction diodes 306 and 308 and the support wiring. First, a portion other than the first element isolation region 303 is masked by a photolithography technique, the element isolation silicon oxide film 305 in the first element isolation region 303 is removed with a diluted hydrofluoric acid solution, and the resist mask is peeled off. Thereafter, a silicon nitride film is deposited to a thickness of 100 nm by CVD and etched back by RIE to form a sidewall silicide prevention film 314 on the sidewall of the first element isolation region 303 (FIG. 7).
[0044]
The silicide prevention film 314 may be formed after the first opening is formed in the first element isolation region 303 and before the element isolation insulating film is embedded therein. The same applies to the embodiments described later.
[0045]
The subsequent silicide formation process can be shared with the MOS transistor gate electrode formation process used in the peripheral circuit, and the process can be simplified.
[0046]
First, after removing the natural oxide film on the surface of the substrate by wet etching with a dilute hydrofluoric acid solution, a titanium thin film 315 having a film thickness of 25 nm is formed by a sputtering method, and an appropriate annealing process is performed, whereby a vertical pn junction is formed. The substrate surface electrode 316, the buried electrode 317, and the support wiring 312 of the diode are silicided (FIG. 8).
[0047]
Next, the titanium thin film 315 in a region where no silicide reaction occurs is removed with a mixed solution of sulfuric acid and hydrogen peroxide.
[0048]
Next, the first element isolation region 303 is re-embedded. First, a silicon nitride film 318 having a thickness of 35 nm and a silicon oxide film 319 having a thickness of 800 nm are deposited on the entire surface of the substrate by CVD as an interlayer insulating film, and planarized to 600 nm from the substrate surface by CMP. At this time, since the width of the first element isolation region 303 is 500 nm or less and narrower than the interlayer insulating film thickness, the insulating film is embedded in the first element isolation region 303 by the interlayer film CVD process and the CMP process. (Fig. 9)
[0049]
Next, contacts, interlayer insulating films, and wirings are formed. First, a contact pattern is formed on the substrate surface electrode 316 of the first and second vertical pn junction diodes 306 and 308 and on the contact formation portion 320 of the support wiring 312 by a photolithography technique, and a contact hole is formed by RIE. A tungsten film having a thickness of 400 nm is deposited on the entire surface of the substrate by CVD, and contact holes are filled by performing CMP (FIG. 10).
[0050]
Next, an aluminum alloy having a film thickness of 500 nm is deposited on the entire surface of the substrate by sputtering, patterned by photolithography and RIE, and after forming a metal wiring 321, an infrared absorption layer 322 that also serves as a passivation for a MOS transistor, etc. A silicon oxide film 323 having a thickness of 800 nm and a silicon nitride film 324 having a thickness of 300 nm are stacked (FIG. 11).
[0051]
Next, the silicon nitride film 324 and the silicon oxide film 323 are etched by RIE to form bonding pad openings.
[0052]
Next, a hollow structure is formed for thermal separation of the infrared solid-state imaging element portion. First, in silicon anisotropic etching for forming a hollow structure, a silicon oxide film having a thickness of 200 nm is deposited on the entire surface of the substrate by CVD as a protective oxide film for preventing etching of the bonding pad.
[0053]
Next, an etching hole 326 for forming a hollow structure is formed by RIE, and the single crystal silicon support substrate 300 is exposed. At this time, the infrared solid-state imaging device portion 327 and the support wiring structure portion 328 are patterned with the pattern of the etching hole 326. Further, a resist mask is formed in a portion other than the support wiring structure portion 328 using a photolithography technique, and the silicon oxide films 319 and 323 and the silicon nitride film 324 are etched by RIE, so that the cross-sectional area of the support wiring structure portion 328 is increased. Decrease and increase thermal resistance.
[0054]
Next, a hollow structure 329 is formed inside the single crystal silicon support substrate 300 by silicon anisotropic wet etching using TMAH (Tetra-Methyl-Ammonium-Hydroxide) (FIG. 12).
[0055]
Next, the protective oxide film is removed to expose the bonding pad, and at the same time, the silicon oxide film 323, the second element isolation region 304, and the buried silicon oxide film 301 constituting the support wiring structure portion 328 are etched to form the support wiring structure. In order to reduce the cross-sectional area of the portion 328, a hydrofluoric acid-based etching process is performed. At this time, in order to increase the selectivity between the bonding pad and the protective oxide film, it is preferable to use a mixed liquid of acetic acid and ammonium fluoride as the etchant. Further, the width of the support wiring structure 328 is about 500 nm, and the hydrofluoric acid-based etching process for removing the pad protection film 325 having a thickness of 200 nm is performed to 400 nm including over the oxide film around the support wiring structure 328. All are removed.
[0056]
Through the above steps, the infrared solid-state imaging device shown in FIGS. 1 and 2 is obtained. The effects of the infrared solid-state imaging device of the present embodiment are as follows. First, p of the first pn junction diode 306 ⁺ N of buried electrode 310 and second pn junction diode 308 ⁺ Since the buried electrode 312 is directly connected by the buried electrode layer 317 made of titanium silicide, the diffusion layer that connects the buried electrode and the contact diffusion layer region existing on the substrate surface, which is a problem in the conventional vertical pn junction diode, is used. The wiring area becomes unnecessary. Thereby, the parasitic resistance of the pn junction diode is reduced, and the sensitivity as an infrared solid-state imaging device can be improved. At the same time, the current component flowing from the diffusion layer wiring region to the vicinity of the substrate surface is greatly reduced, the 1 / f noise component can be reduced, and an infrared solid-state imaging device with a higher S / N ratio can be realized.
[0057]
Further, since adjacent pn junction diodes can be directly connected in series without using a contact diffusion layer to be formed on the substrate surface, the element area can be reduced and the element volume can be reduced as much as the contact region is unnecessary. . As a result, if the amount of infrared rays incident on the thermosensitive element is the same, in this embodiment, the element heat capacity is reduced compared to the conventional one, so that the temperature change of the element during infrared irradiation increases, and at the same time an improvement in sensitivity can be expected. , Response is faster, and the frame rate as an image sensor can be increased.
[0058]
FIG. 13 is a cross-sectional view of a structure related to a conventional example and a device described in the present embodiment when a prototype is manufactured according to the same device design rule. A margin rule 330 regarding a misalignment of masks for forming an element region, a contact, a diffusion layer, and a silicide prevention film layer is a, a contact diameter rule 331 is b, n ⁺ Diffusion layer and p ⁺ If the distance 332 between the diffusion layers is c and the element separation rule 333 is also c, the conventional example requires a width of 6a + 2b + 2c per element, but in this embodiment, it can be formed with 2a + b + c per element. , The device area can be reduced to about ½.
[0059]
In this embodiment, two pn junction diodes as thermal elements are connected in series. However, it goes without saying that this patent is effective even if two or more pn junction diodes are arranged. There is no. For example, in a silicon pn junction diode type infrared solid-state imaging device, the sensitivity as an imaging device increases as the number of pn junction diodes connected in series increases, but the breakdown voltage of an SOI MOS transistor used in a peripheral circuit is less than 10 V or less. Therefore, the number of pn junction diodes connected in series is more preferably 8-12.
[0060]
In this embodiment, metal silicide is used as the support wiring 311 in order to reduce heat conduction to the support substrate 300 as much as possible. However, the metal wiring 321 is used as the support wiring in preference to reduction of parasitic resistance. However, the effect obtained in the present embodiment is effective.
[0061]
(Second Embodiment)
In the second embodiment, the metal silicide layer, which is the material of the embedded electrodes of the first and second vertical pn diodes, is formed in the same layer in the same process as the support wiring.
[0062]
In the second embodiment, metal silicide having a lower thermal conductivity than metal can be used for the support wiring without adding a new wiring layer to the existing LSI process, and boron penetration of the pMOS gate electrode is suppressed. Therefore, it is possible to reduce the thickness of the support wiring and reduce the cross-sectional area of the support wiring, that is, to improve the thermal isolation of the solid-state imaging device. Objective.
[0063]
FIG. 14 is a plan view of a second embodiment of the infrared solid-state imaging device according to the present invention, and FIG. 15 is a cross-sectional view taken along the line AA ′ of FIG. As can be seen by comparing FIG. 1 and FIG. 14, the infrared solid-state imaging device of the present embodiment is different from FIG. 1 in the structure of the support wiring.
[0064]
14 to 23 are cross-sectional views showing manufacturing steps of the second embodiment of the infrared solid-state imaging device according to the present invention. Below, it demonstrates centering around difference with the manufacturing process of 1st Embodiment.
[0065]
First, an SOI substrate in which an embedded silicon oxide film layer 401 and a single crystal silicon layer 402 are sequentially stacked on a single crystal silicon support substrate 400 is used as a semiconductor substrate. The thicknesses of the buried silicon oxide film 401 and the single crystal silicon layer 402 of the SOI substrate are not particularly limited. For example, in this embodiment, the thickness of the buried silicon oxide film is 150 nm and the thickness of the single crystal silicon layer is 400 nm. , P-type impurity concentration is 2 × 10 ¹⁶ / Cm ³ The SOI substrate was used (FIG. 16).
[0066]
Next, an element isolation region is formed by STI (Shallow-Trench-Isolation). First, the first element isolation region 403 and the support wiring portion 404 are patterned by a photolithography technique, and at least a part of the single crystal silicon layer 402 remains by RIE (Reactive-Ion-Etching) of the single crystal silicon layer 402. Etch like so. For example, in this embodiment, the single crystal silicon layer 402 is etched by 300 nm (FIGS. 17 and 18).
[0067]
Next, the second element isolation region 405 is patterned by a photolithography technique, and the single crystal silicon layer 402 is entirely etched by RIE (FIGS. 19 and 20).
[0068]
Thereafter, the silicon oxide film is embedded in the first element isolation region and the second element isolation region and the vertical pn junction diode is formed by the same process as in the first embodiment.
[0069]
Next, silicide formation of the substrate surface electrode and the buried electrode of the vertical pn junction diode and the support wiring is performed. First, a portion other than the first element isolation region 403 is masked by a photolithography technique, the element isolation silicon oxide film embedded in the first element isolation region 403 is etched by RIE, and the resist mask is peeled off. At this time, a sidewall silicide prevention film 406 made of a silicon oxide film is formed on the sidewall of the first element isolation region 403 (FIGS. 21 and 22).
[0070]
Note that a silicide prevention film may be formed in the same manner as in the first embodiment.
[0071]
The subsequent silicide formation process can be shared with the MOS transistor gate electrode formation process used in the peripheral circuit, and the process can be simplified.
[0072]
Next, after removing the natural oxide film on the substrate surface by wet etching with a dilute hydrofluoric acid solution, a titanium thin film 407 having a film thickness of 25 nm is formed by a sputtering method, and an appropriate annealing treatment is performed, whereby vertical pn The substrate surface electrode 408, the buried electrode 409, and the support wiring 404 of the junction diode are silicided (FIG. 23).
[0073]
Next, the titanium thin film 407 in a region where the silicide reaction does not occur is removed with a mixed solution of sulfuric acid and hydrogen peroxide.
[0074]
Thereafter, since the process from the re-embedding process of the first element isolation region to the formation of the hollow structure is the same as that of the first embodiment, the description thereof is omitted. The final form after these steps is as shown in FIGS.
[0075]
Note that the planar shape of the support wiring portion 404 is not limited to FIG. 14, and various shapes such as the shape shown in FIG. 1 can be adopted.
[0076]
The effects of the infrared solid-state image sensor of the second embodiment are as follows. First, sensor sensitivity can be improved by reducing the thermal conductivity of the support wiring. 24A and 24B are cross-sectional views in the case where the support wirings in the conventional example and the present embodiment are formed according to the same design rule (cross-sectional view along the line BB ′ in FIG. 14).
[0077]
In the conventional example, the gate electrode of the MOS transistor is used as a support wiring material from the viewpoint of simplification of the process, so that the thinning is restricted in order to suppress boron penetration of the pMOS gate electrode, and the total thickness of the polysilicon is It is as thick as 250 nm. In contrast, in the process according to the present embodiment, the single crystal silicon film serving as the electrode material can be thinned according to the etching amount of the first element isolation region 403. For example, in the second embodiment, the single crystal silicon film thickness is 100 nm.
[0078]
FIG. 24C shows an example in which the etching amount of the first element isolation region 403 is about 375 nm and all of the support wiring is titanium silicide as an application example of this embodiment. In these three types of support wirings, the thickness of the titanium silicide layer responsible for electrical conduction is set to 25 nm in all examples, and the parasitic resistance values of the support wirings are equal. On the other hand, the thermal conductivity of these support wirings is almost determined by the silicon film and the silicide film, and when the thermal conductivity per 1 μm is calculated, the conventional example is 3.0 × 10 6. ^-6 [Μm · W / K], Embodiment 2 is 1.5 × 10 ^-6 [Μm · W / K], all silicided is 0.75 × 10 ^-6 [Μm · W / K]. That is, in this embodiment, the thermal conductivity of the support wiring is lower than in the conventional case, and the heat insulation of the thermal cell, that is, the sensitivity of the cell is improved.
[0079]
In addition, the arrangement of the pn junction diodes is not limited to the stripe shape, and can be two-dimensionally arranged. Thereby, the freedom degree of design of an infrared detection part increases. For example, FIG. 25 shows a top view of an infrared solid-state imaging device having a plurality of pn junction diodes.
[0080]
In the figure, reference numeral 501 denotes a support wiring, 502 a thermal cell wiring, 503 a second element isolation region, and 504 a first element isolation region and a buried electrode of a vertical pn junction diode. As shown, pn junction diodes can be arranged two-dimensionally.
[0081]
【The invention's effect】
As described above in detail, according to the present invention, an infrared solid-state imaging device having a high S / N ratio can be realized by reducing the 1 / f noise component or the like.
[Brief description of the drawings]
FIG. 1 is a plan view of a first embodiment of an infrared solid-state imaging device according to the present invention.
FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.
FIG. 3 is a cross-sectional view showing a manufacturing process of an embodiment of an infrared solid-state imaging device according to the present invention.
4 is a cross-sectional view subsequent to FIG. 3;
5 is a cross-sectional view showing a manufacturing step that follows FIG. 4. FIG.
6 is a cross-sectional view showing a manufacturing step that follows FIG. 5. FIG.
7 is a cross-sectional view showing a manufacturing step that follows FIG. 6. FIG.
8 is a cross-sectional view showing a manufacturing step that follows FIG. 7. FIG.
9 is a cross-sectional view showing a manufacturing step that follows FIG. 8. FIG.
10 is a cross-sectional view showing a manufacturing step that follows FIG. 9; FIG.
11 is a cross-sectional view showing a manufacturing step that follows FIG. 10; FIG.
12 is a cross-sectional view showing a manufacturing step that follows FIG. 11. FIG.
FIG. 13 is a structural cross-sectional view relating to a conventional example and a device described in the present embodiment when a prototype is manufactured according to the same device design rule.
FIG. 14 is a plan view of a second embodiment of an infrared solid-state imaging device according to the present invention.
15 is a cross-sectional view taken along line AA ′ in FIG.
FIG. 16 is a sectional view showing a manufacturing process of the second embodiment.
FIG. 17 is a cross-sectional view showing a manufacturing step that follows FIG. 16;
18 is a cross-sectional view showing a manufacturing step that follows FIG. 17; FIG.
FIG. 19 is a cross-sectional view showing a manufacturing step that follows FIG. 18;
20 is a cross-sectional view showing a manufacturing step that follows FIG. 19; FIG.
FIG. 21 is a cross-sectional view showing a manufacturing step that follows FIG. 20;
22 is a cross-sectional view showing a manufacturing step that follows FIG. 21. FIG.
FIG. 23 is a cross-sectional view showing a manufacturing step that follows FIG. 22;
24A is a cross-sectional view of a conventional support wiring portion, FIG. 24B is a cross-sectional view of the support wiring portion of the present embodiment formed according to the same design rule as FIG. Sectional drawing which shows the example which made the etching amount of the element isolation region 403 into about 375 nm, and all the support wiring became titanium silicide.
FIG. 25 is a plan view showing another embodiment of the infrared solid-state imaging device according to the present invention.
FIG. 26 is a cross-sectional view of a conventional infrared solid-state image sensor.
[Explanation of symbols]
1 Infrared absorber
2 Infrared detector
101 Single crystal silicon support substrate
102 Hollow structure
103, 104 Infrared absorbing layer
105 Single crystal silicon layer
106 pn junction diode
107 buried silicon oxide film layer
108 Solid-state image sensor unit
109 Support
110, 111, 112 Support insulation structure
113 Polycrystalline silicon region
114 Metal silicide region
300 Single crystal silicon support substrate
301 buried silicon oxide film
302 single crystal silicon
303 first element isolation region
304 Second element isolation region
305 Device isolation silicon oxide film
306 first pn junction diode
307 n ⁺ Electrode area
308 Second pn junction diode
309 p ⁺ Electrode area
310 p ⁺ Embedded electrode area
311 Support wiring
312 n ⁺ Embedded electrode area
313 sidewall
314 Sidewall silicide prevention film
315 Titanium thin film
316 Substrate surface electrode of vertical pn junction diode
317 Embedded electrode of vertical pn junction diode
318 Silicon nitride film
319 Silicon oxide film
320 Support wiring contact part
321 metal wiring
322 Infrared absorber
323 Silicon oxide film
324 Silicon nitride film
325 Bonding pad protective oxide film
326 Etching hole
327 Infrared solid-state image sensor
328 Support wiring structure
329 Hollow structure
400 single crystal silicon support substrate
401 buried silicon oxide film
402 single crystal silicon
403 First element isolation region
404 Support wiring
405 Second element isolation region
406 Sidewall silicide prevention film
407 Titanium thin film
408 Vertical surface pn junction diode substrate surface electrode
409 Embedded electrode of vertical pn junction diode
500 Thermal cell
502 Wiring in thermal cell
501 Support wiring
503 element isolation region
504 embedded electrode of first element isolation region and vertical pn junction diode according to first embodiment
505, 506 Vertical pn junction diode
507 Conventional vertical pn junction diode
508 n ⁺ Diffusion layer
509 p ⁺ Diffusion layer

Claims (8)

An infrared detection unit formed on a semiconductor substrate and having an infrared absorption unit that absorbs incident infrared rays and converts the infrared rays into heat; and a thermoelectric conversion unit that converts a temperature change caused by the heat generated in the infrared absorption unit into an electrical signal;
And supporting at least one infrared detection unit spaced apart from the semiconductor substrate, and having input / output wiring of the infrared detection unit, and
The thermoelectric converter is
First and second vertical pn junction diodes formed in a direction substantially orthogonal to the surface of the semiconductor substrate and arranged opposite to the surface of the semiconductor substrate in a substantially horizontal direction across an element isolation region;
An infrared solid comprising at least one structure formed along a bottom surface of the element isolation region and having a conductive layer that conducts one end of each of the first and second vertical pn junction diodes. Image sensor. The first vertical pn junction diode includes a first conductivity type first diffusion layer, a second conductivity type second diffusion layer formed in order from the top in the depth direction of the semiconductor substrate, Have
The second vertical pn junction diode includes a third diffusion layer of a second conductivity type, a fourth diffusion layer of a first conductivity type formed in order from the top in the depth direction of the semiconductor substrate, Have
The infrared solid-state imaging device according to claim 1, wherein the conductive layer is connected to the second and fourth diffusion layers. The infrared solid-state imaging device according to claim 1, wherein the conductive layer is a metal silicide layer. 4. The silicidation prevention film comprising an insulating layer formed adjacent to each of the first and second vertical pn junction diodes along a side wall of the element isolation region. Infrared solid-state imaging device. The infrared solid-state imaging device according to claim 1, wherein the conductive layer and the input / output wiring of the support are made of a common material. An infrared detection unit formed on a semiconductor substrate and having an infrared absorption unit that absorbs incident infrared rays and converts the infrared rays into heat; and a thermoelectric conversion unit that converts a temperature change caused by the heat generated in the infrared absorption unit into an electrical signal;
An infrared solid-state imaging device comprising: at least one support that supports the infrared detection unit apart from the semiconductor substrate and has input / output wirings of the infrared detection unit;
An SOI substrate in which a single crystal silicon substrate, a buried insulating layer, and a single crystal silicon layer are sequentially stacked is used as the semiconductor substrate, and a part of the single crystal silicon layer is etched away so that the single crystal silicon layer remains. Forming a first groove for a first element isolation region;
Removing the single crystal silicon layer in the second element isolation region formed adjacent to the vertical pn junction diode region as a thermoelectric conversion portion located on both sides of the first groove and the first groove; Forming a second groove
Embedding an insulating material in the first and second grooves;
Implanting impurity ions into the single crystal silicon layer in the region of the infrared detection unit to form a first n ⁺ electrode region and a first p ⁺ electrode region with the first element isolation region interposed therebetween, respectively. When,
Impurity ions are implanted into the single crystal silicon layer in the region of the infrared detection unit to form a second p ⁺ electrode region below the first n ⁺ electrode region, and the first p ⁺ electrode Forming a second n ⁺ electrode region below the region;
Forming input / output wiring of the support on the second element isolation region;
Removing the insulating material embedded in the first trench;
Forming a first insulating layer on a sidewall of the first element isolation region;
A bottom electrode layer connecting the second p ⁺ electrode region and the second n ⁺ electrode region is formed on the bottom surface of the first element isolation region, and the first n ⁺ electrode region and the first n ⁺ electrode region are formed. Forming a surface electrode layer on the surface of the p ⁺ electrode region of 1;
Forming a second insulating layer that embeds the first element isolation region;
And a step of forming at least one support for separating the infrared detection unit from the semiconductor substrate and supporting the infrared detection unit. An infrared detection unit formed on a semiconductor substrate and having an infrared absorption unit that absorbs incident infrared rays and converts the infrared rays into heat, and a thermoelectric conversion unit that converts a temperature change caused by the heat generated in the infrared absorption units into an electrical signal. And
An infrared solid-state imaging device comprising: at least one support that supports the infrared detection unit apart from the semiconductor substrate and has input / output wirings of the infrared detection unit;
An SOI substrate in which a single crystal silicon substrate, a buried insulating layer, and a single crystal silicon layer are sequentially stacked is used as the semiconductor substrate, and a part of the single crystal silicon layer is etched away so that the single crystal silicon layer remains. Forming a first groove for a first element isolation region and a second groove for the input / output wiring;
A second element isolation region formed adjacent to a vertical pn junction diode region as a thermoelectric conversion portion located on both sides of the first groove and the first groove, and other than the input / output wiring portion Removing the single crystal silicon layer in a region to form a third groove;
Embedding an insulating material in the first, second and third grooves;
Implanting impurity ions into the single crystal silicon layer in the region of the infrared detection unit to form a first n ⁺ electrode region and a first p ⁺ electrode region with the first element isolation region interposed therebetween, respectively. When,
Impurity ions are implanted into the single crystal silicon layer in the region of the infrared detection unit to form a second p ⁺ electrode region below the first n ⁺ electrode region, and the first p ⁺ electrode Forming a second n ⁺ electrode region below the region;
Removing the insulating material embedded in the first trench;
Forming a first insulating layer on a sidewall of the first element isolation region;
Forming bottom electrode layers on the bottom surface of the first element isolation region and the input / output wiring part, respectively, and forming surface electrode layers on the surfaces of the first n ⁺ electrode region and the first p ⁺ electrode region; Connecting the diode and the input / output wiring portion to each other;
Forming a second insulating layer that embeds the first element isolation region;
And a step of forming at least one support for separating the infrared detection unit from the semiconductor substrate and supporting the infrared detection unit. The method for manufacturing an infrared solid-state imaging device according to claim 6, wherein the bottom electrode layer and the surface electrode layer are metal silicide layers.

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