JP4410071B2 - Infrared solid-state imaging device - Google Patents

Description

  The present invention relates to an infrared solid-state imaging device used in an infrared sensor or the like.

  In recent years, development of an uncooled infrared solid-state imaging device that does not need to be cooled to a nitrogen temperature has become active. In an uncooled infrared solid-state imaging device, an incident infrared ray having a wavelength of about 10 μm is converted into heat by an infrared absorption structure, and the temperature change of the heat sensitive portion caused by the weak heat is converted into an electrical signal by a thermoelectric conversion portion. The infrared image information is obtained by reading out the electrical signal.

  The above-described uncooled infrared solid-state imaging device can be reduced in size and on-chip because it does not require a cooling device, and is proceeding toward cost reduction with consumer applications in mind. Against this background, an uncooled infrared solid-state imaging device using a silicon pn junction diode that can share most of the manufacturing process with a conventional CMOS LSI has attracted attention. However, in such a silicon pn junction diode type, dV / dT which is a sensitivity index of the infrared solid-state imaging device is low, and it is necessary to further improve the S / N ratio.

  Noise components of the pn junction diode include 1 / f noise due to the roughness and surface level of the silicon substrate surface, thermal noise depending on the amount of bias current, and shot noise due to variations in the amount of current passing through the pn junction. is there. Among these, 1 / f noise can be avoided by using a vertical pn junction structure with a silicon bulk as a current path, and an improvement in the S / N ratio can be expected.

  In addition, in the above-described uncooled infrared solid-state imaging device, an infrared detection unit composed of a thermosensitive unit (infrared absorbing structure) that converts incident infrared rays into heat and a thermoelectric conversion unit that converts the heat into electrical signals is thermally surrounded. In order to improve infrared sensitivity, it is essential to improve the thermoelectric conversion efficiency.

Therefore, an infrared solid-state imaging device is mounted in a vacuum package, and there is a method for suppressing diffusion of heat to the support substrate by etching and removing the silicon substrate and the element isolation oxide film around the infrared detection unit. Has been taken.

  At this time, the heat transport from the infrared detection unit to the support substrate is dominated by heat conduction through the support structure that supports the infrared detection unit on the hollow structure inside the support substrate. The leg-shaped support structure is designed to be thinner and longer as long as it can be designed. However, as the pixel size is being reduced to about 40 μm × 40 μm, it is much larger than this. It is becoming difficult to achieve a high sensitivity improvement.

  Conventionally, as an infrared imaging device using a silicon pn junction diode, the temperature dependence of the forward characteristics of the pn junction has been achieved, but dV / dT cannot be sufficiently high.

Therefore, as a conventional example, an infrared imaging device using a pn junction reverse bias having a large dV / dT has been proposed (see Patent Document 1).

JP-A-3-212979

  However, in the conventional example, since a reverse bias is applied to the pn junction, when even a little visible light is incident on the pn junction diode, it operates as a photodiode and the function as an infrared sensor is lost. .

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a silicon pn junction diode type infrared solid-state imaging device having higher sensitivity.

  In order to solve the above problems, an infrared solid-state imaging device of the present invention is formed on an upper part of a semiconductor substrate having a hollow structure inside, and an infrared absorption part for absorbing incident infrared light and converting it into heat, and the upper part of the hollow structure A thermoelectric conversion unit formed of a pn junction diode that converts a temperature change due to heat generated in the infrared absorption unit into an electrical signal, and exists between the infrared absorption unit and the thermoelectric conversion unit, and And a visible light blocking layer that blocks visible light from entering the thermoelectric converter.

  In the infrared solid-state imaging device of the present invention, a visible light blocking layer is formed between the infrared absorbing portion and the thermoelectric conversion portion so as to shield the thermoelectric conversion portion. With this structure, when the pn junction diode of the thermoelectric conversion unit is reverse-biased, the operation as a photodiode is suppressed, and the thermoelectric conversion unit does not malfunction.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Example 1]
First, an infrared solid-state imaging device that is Embodiment 1 of the present invention will be described with reference to FIGS.

  1 is a top view of the infrared solid-state imaging device, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. In FIG. 2, a buried silicon oxide layer 202 and an SOI layer 203 are sequentially stacked on a silicon substrate 201. A diaphragm 228 having a hollow structure is formed on the silicon substrate 201 and plays a role of preventing heat generated by absorbing infrared rays from escaping to the silicon substrate 201. In the SOI layer 203, an element isolation oxide film 204 in which silicon oxide is embedded in a trench structure is formed.

A p ⁺ electrode region 207 having an impurity concentration of 4 × 10 ¹⁵ cm ⁻² is formed at the bottom of the portion of the SOI layer 203 (thermoelectric conversion element region) sandwiched between the element isolation oxide films 204. A pn junction diode region 205 having a conductivity type of p type and an impurity concentration of 1.5 × 10 ¹³ cm ⁻² is formed above the p ⁺ electrode region 207, and charges generated by thermoelectric conversion are formed in this region. Accumulates. Then a within pn junction diode region 205, the region of the SOI layer 203 surface, ^{n +} electrode regions 206 impurity concentration of 5 × 10 ¹⁵ cm ^-2 is formed, pn from the ^{n +} electrode region 206 surface One electrode of the pn junction diode constituted by the junction diode region 205 and the n ⁺ electrode region 206 is drawn out. Further, a p ⁺ region 209 having an impurity concentration of 4 × 10 ¹⁵ cm ⁻² is formed so as to be connected to the p ⁺ electrode region 207. A p ⁺ contact diffusion layer region 208 having an impurity concentration of 2 × 10 ¹⁴ cm ⁻² is formed on the p ⁺ region 209, and the other side of the pn junction diode is formed from the surface of the p ⁺ contact diffusion layer region 208. The electrode is pulled out.

  On the surface of the SOI layer 203 where the thermoelectric conversion element region is not provided (this is referred to as “peripheral region”), a peripheral circuit 212 including a gate 210 and a side wall 212 is formed. The charges generated in the thermoelectric conversion element region are read out and signal processed.

A first interlayer insulating film 221 made of a silicon oxide film is formed on the SOI layer 203. The first interlayer insulating film 221 is made of a member such as tungsten, and the first contact electrode 222-1 connected to the n ⁺ electrode region 206 and the second contact electrode connected to the p ⁺ contact diffusion layer region 208. 222-2 is formed.

  A second interlayer insulating film 224 is formed on the first interlayer insulating film 221, and a visible light blocking layer 225 made of aluminum and having a thickness of 0.5 to 0.6 μm is formed thereon. . The visible light blocking layer 225 may be an aluminum single layer, but in order to completely block visible light, for example, 5 nm TiN, 60 nm Ti, 0.5 μm Al, 20 nm TiN, and 10 nm A laminated structure of Ti may be used. On the visible light blocking layer 225, a silicon oxide film 226 and a silicon nitride film 227 are laminated in this order, and these constitute an infrared absorption layer 228.

According to the infrared solid-state imaging device of FIG. 2, the visible light blocking layer 225 having a thickness of 0.5 to 0.6 μm is formed between the infrared absorbing layer 228 and the thermoelectric conversion element region. It plays a role of preventing visible light from entering the thermoelectric conversion element region. Conventionally, when visible light is incident on the thermoelectric conversion element region, the thermoelectric conversion element operates like a photodiode, and the charge accumulated in the pn junction diode region 205 is other than the readout clock unique to the infrared solid-state imaging device. The amount of current increase due to the temperature change of the diode due to the outflow toward the n ⁺ electrode region 206 at the timing was cancelled. Therefore, in this embodiment, Al is inserted as a visible light blocking layer immediately above the thermoelectric conversion element region constituting the pn junction diode, both visible light and infrared light are reflected, and only the infrared light is absorbed and absorbed by the upper absorption film. By converting, only the infrared component can be extracted as a signal.

  Next, a method for manufacturing the infrared solid-state imaging device according to the first embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 3, a so-called SOI substrate 200 is prepared in which a buried silicon oxide film layer 202 and a single crystal silicon layer 203 are sequentially stacked on a single crystal silicon support substrate 201 as a semiconductor substrate.

  Next, as shown in FIG. 4, element isolation is performed using an STI (Shallow-Trench-Isolation) structure. That is, an element isolation region is defined by a photolithography technique, the single crystal silicon layer 203 in the element isolation region is removed by etching by RIE (Reactive-Ion-Eching), and then the element isolation oxide film 204 is formed by CVD (Chemical-Vapor-). It is embedded by Deposition and planarized by CMP (Chemical-Mechanical-Polishing). At this time, the portion of the support structure 234 in FIG. 1 is also defined as an element isolation region, and the element isolation oxide film 204 is embedded.

After the element isolation oxide film 204 is formed, as shown in FIG. 5, as a means for forming a pn junction diode that becomes a thermoelectric conversion element, first, a p-type diffusion layer region is defined by photolithography technology, and, for example, boron is doped by ion implantation. Implantation is performed at 75 keV and 1.5 × 10 ¹³ cm ⁻² to form a pn junction diode region 205. Next, similarly, an n ⁺ diffusion layer region is defined in a shallow region of the SOI layer 203 and, for example, As is implanted at 40 keV and 5 × 10 ¹⁵ cm ⁻² to form an n ⁺ electrode region 206. Next, in the same manner, a p ⁺ electrode region 207 is formed in a deep region of the SOI layer 203 by, for example, implanting B at 7 keV and 4 × 10 ¹⁵ cm ⁻² to form a p ⁺ contact diffusion layer formed on the substrate surface. In order to connect the region 208 and the p ⁺ electrode region 207, a p ⁺ region 209 extending in the substrate depth direction is formed. As these formation conditions (ion implantation conditions), for example, the p ⁺ contact diffusion layer region 208 has B of 130 keV and 2 × 10 ¹⁴ cm ⁻² , and the p ⁺ region 209 has B of 100 keV, 2.5 × 10 ¹³ cm ⁻² and 75 keV, 6 × 10 ¹³ cm ⁻² and 40 keV, 1.5 × 10 ¹³ cm ⁻² and 7 keV, 4 × 10 ¹⁵ cm ⁻² .

  Next, as shown in FIG. 6, after forming the polysilicon layer 210, the support structure 234 is processed by photolithography and RIE. In this step, the gate electrode 210 of the MOS transistor used for the peripheral circuit is also formed at the same time. Thereafter, a silicon nitride film is formed on the entire surface of the substrate by CVD, and etched back by RIE, thereby forming a side wall 211 at the stepped portion by the gate electrode and the support wiring. In this state, a source / drain impurity region is formed in a self-aligning manner by ion implantation using the gate electrode 210 and the side wall 211 as a mask.

Next, as shown in FIG. 7, a silicon nitride film is deposited on the entire SOI layer 203 by CVD, and a photomask is formed in regions other than the n ⁺ electrode region 206 and the p ⁺ contact region 208 of the pn junction diode in the thermoelectric conversion element region. And RIE of the silicon nitride film is performed to form a silicide block film 217. This prevents the n ⁺ electrode region 206 and the p ⁺ region contact 208 of the pn junction diode from becoming conductive due to silicide. Thereafter, the gate insulating film is etched with dilute hydrofluoric acid or the like using the gate electrode, the support wiring, the side wall 212 and the silicide block film 217 as a mask, and the gate electrode 211 of the MOS transistor 213, the source / drain region, The silicon layers of the ⁺ electrode region 206 and the p ⁺ contact region 208 are exposed. Next, a titanium film 218 for silicide formation is deposited on the entire surface. By performing an appropriate annealing process from this state, the exposed silicon of the gate electrode 211 of the MOS transistor 213, the source / drain region, the n ⁺ electrode region 206 of the pn junction diode, the p ⁺ contact region 208, and the support wiring is titanium. Reacting with the film 218, a titanium silicide layer 219 is formed. After the titanium silicide layer 219 is formed, the titanium film 218 in a region where no silicide reaction is performed is removed with a mixed solution of sulfuric acid and hydrogen peroxide.

  Next, as shown in FIG. 8, a silicon nitride film 220 and a first interlayer insulating film 221 made of a silicon oxide film are deposited on the entire surface of the SOI layer 203 by CVD, and planarized by CMP.

  Next, as shown in FIG. 9, contact holes 222 are formed in the first interlayer insulating film 221 by RIE, tungsten is deposited on the entire surface of the SOI layer 203 by CVD, and CMP is performed to embed the contact holes. The first contact electrode 222-1 and the second contact electrode 222-2 are formed.

  Next, as shown in FIG. 10, an aluminum alloy is deposited on the entire surface by sputtering, patterned by photolithography and RIE, and metal wiring for connecting the first contact electrode 222-1 and the second contact electrode 222-2. 223 is formed. After the metal wiring 223 is formed, a silicon oxide film is deposited as the second interlayer insulating film 224, and then an Al film is deposited as the visible light blocking layer 225 so as to cover the entire surface of the thermoelectric conversion element region. The visible light blocking layer 225 is not limited to Al as long as it does not transmit visible light. For example, Ag, Al, Au, Rh, Cu, Ti, or a laminated structure thereof may be used. Further, if the wiring layer used in the LSI is used as the visible light blocking layer 225, the process can be simplified. At this time, the visible light blocking layer 225 has a structure in which Ti, TiN, or a laminated film thereof is arranged on at least one of the upper and lower sides of Al, or Ta, TaN, or a laminated layer thereof on at least one of the upper and lower sides of Cu. A structure in which a film is arranged is good. Thereafter, a silicon oxide film 226 and a silicon nitride film 227 are deposited as the infrared absorption layer 235. At this time, in order to sufficiently absorb infrared rays, the total of the silicon oxide film 226 and the silicon nitride film 227 is desirably 0.5 μm or more.

  Then, an etching hole 229 for forming the diaphragm 228 is formed by RIE, and the silicon substrate 201 is exposed.

  Next, a diaphragm 228 is formed inside the silicon substrate 201 by anisotropic wet etching for silicon by TMAH (Tetra-Methyl-Ammonium-Hydroxide).

  Through the above steps, the infrared solid-state imaging device shown in FIG. 2 is completed.

  Each of the above-described embodiments exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is based on the material, shape, structure, and arrangement of components. Etc. are not limited only to those disclosed in the embodiments. The present invention can be variously modified and implemented without departing from the spirit of the present invention.

It is a top view of the infrared solid-state imaging device of Example 1 of the present invention. It is sectional drawing in AA 'of FIG. It is a manufacturing-process figure of the infrared solid-state imaging device of Example 1 of this invention. It is a manufacturing-process figure of the infrared solid-state imaging device of Example 1 of this invention. It is a manufacturing-process figure of the infrared solid-state imaging device of Example 1 of this invention. It is a manufacturing-process figure of the infrared solid-state imaging device of Example 1 of this invention. It is a manufacturing-process figure of the infrared solid-state imaging device of Example 1 of this invention. It is a manufacturing-process figure of the infrared solid-state imaging device of Example 1 of this invention. It is a manufacturing-process figure of the infrared solid-state imaging device of Example 1 of this invention. It is a manufacturing-process figure of the infrared solid-state imaging device of Example 1 of this invention.

Explanation of symbols

200 ... SOI substrate 201 ... Silicon substrate 202 ... Embedded silicon oxide layer 203 ... SOI layer 204 ... Element isolation oxide film 205 ... pn junction diode region 206 ... n ⁺ electrode region 207 ... p ⁺ electrode region 208 ... p ⁺ contact diffusion layer region 209 ... p ⁺ region 210 ... gate electrode 211 ... sidewall 213 ... MOS transistor 217 ... silicide block film 218 ... titanium film 219 ... titanium silicide layer 220, 227 ... silicon nitride film 221 ... first interlayer insulating film 222 ... contact hole 222 DESCRIPTION OF SYMBOLS -1 ... 1st contact electrode 222-2 ... 2nd contact electrode 223 ... Metal wiring 224 ... 2nd interlayer insulation film 225 ... Visible light blocking layer 226 ... Silicon oxide film 228 ... Diaphragm 229 ... Etching hole 230 ... Input signal 231 ... output signal line 234 ... support structure 235 ... infrared absorbing layer

Claims (5)

An infrared absorption part formed on the top of a semiconductor substrate having a hollow structure inside, for absorbing incident infrared rays and converting them into heat;
A thermoelectric conversion unit formed of a pn junction diode formed on the hollow structure and converting a temperature change due to heat generated in the infrared absorption unit into an electrical signal;
A visible light blocking layer having a thickness of 0.5 to 0.6 μm, which is present between the infrared absorption unit and the thermoelectric conversion unit and blocks visible light from entering the thermoelectric conversion unit;
An infrared solid-state imaging device characterized by comprising:   The infrared solid-state imaging device according to claim 1, wherein the thermoelectric conversion unit performs reverse bias connection of a pn junction diode. The visible light blocking layer, an infrared solid-state imaging device according to claim 1 or 2, wherein the a structure for shielding at least the thermoelectric conversion portion. A first semiconductor layer formed on a semiconductor substrate having a hollow structure therein;
A first impurity region of a first conductivity type formed in the first semiconductor layer;
A second impurity region of a second conductivity type formed in the first impurity region;
A wiring layer formed on the first semiconductor layer and connecting the first impurity region and the second impurity region;
A visible light blocking layer formed on the wiring layer and having a thickness of 0.5 to 0.6 μm;
An infrared solid-state imaging device comprising: an infrared absorption layer formed of two insulating layers made of different materials, formed on the visible light blocking layer.   An infrared solid-state imaging device, wherein the first impurity region and the second impurity region form a pn junction, and the pn junction is operated in a reverse bias state.

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