JP2005006170A - Device for automatically adjusting duty cycle - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a duty cycle automatic adjusting device capable of automatically adjusting the duty cycle of a clock signal in a receiving side device. <P>SOLUTION: This duty cycle automatic adjusting device for receiving the clock signal from the outside and adjusting the ratio of the duty cycle of the clock signal is provided with a frequency dividing means for applying 1/2 frequency division to the clock signal, and a duty cycle adjusting means for equally adjusting the ratio of duty cycles of an intermediate timing signal in a high period, an intermediate timing signal in a low period and the clock signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

タイミング調整回路部４は、ＬＰＦ部３から高周波成分が除去された反転出力信号１／２ＣＬＫ＿Ｎと、１／２分周回路２から反転出力信号１／２ＣＬＫ＿Ｎとを受け取り、非反転出力信号１／２ＣＬＫがＨｉｇｈである期間に対し、この期間がちょうど中間となるタイミングを生成するものである。また、タイミング調整回路部４は、非反転出力信号１／２ＣＬＫのＨｉｇｈである期間の中間となるタイミングを生成し、その生成したタイミングで立ち上がる信号を出力ＣＬＫ合成回路部６に与える。
【００３５】
図５に示すように、タイミング調整回路部４は、直流成分除去部４２と、ノイズ除去部４３と、チャージポンプ部４１とを有している。
【００３６】
直流成分除去部４２は、ＬＰＦ部３からの反転出力信号１／２ＣＬＫ＿Ｎを受け取り、その反転出力信号１／２ＣＬＫ＿Ｎの直流成分を除去するものである。また、直流成分除去部４２は、直流成分を除去した反転出力信号１／２ＣＬＫ＿Ｎをノイズ除去部に与えるものである。
【００３７】
図１に示すように、直流成分除去部４２は、ＬＰＦ部３と接続するコンデンサ４２１を有する。
【００３８】
ノイズ除去部４３は、直流成分除去部４２からの反転出力信号１／２ＣＬＫ＿Ｎに、チャージポンプ部４１からの直流電位が調整された直流成分を付加した信号を受け取り、その直流成分を付加した信号のノイズ成分を除去するフィルタである。ノイズ除去部４３は、ノイズ成分を除去した出力信号をチャージポンプ部４１に与える。
【００３９】
ここで、出力信号に付加する直流成分は、反転出力信号１／２ＣＬＫのＨｉｇｈ期間がちょうど中間となるタイミングを生成するように、チャージポンプ部４１によりその直流電位を調整されたものである。すなわち、チャージポンプ部４１から直流電位が調整された直流成分が負帰還され、この直流成分を直流成分除去部４２からの出力信号に付加したものをノイズ除去部４３は取り入れる。
【００４０】
チャージポンプ部４１は、ノイズ除去部４３からノイズが除去された出力信号を受け取り、また１／２分周回路部２からの反転出力信号１／２ＣＬＫ＿Ｎを反転したものを取り込み、反転出力信号１／２ＣＬＫのＨｉｇｈ期間において、ノイズ除去部４３からの直流成分を付加した出力信号について、しきい値以上の電位となる期間（図３（Ｄ）のＴ１期間）と、しきい値未満の電位となる期間（図３（Ｄ）のＴ２期間）とが一致するようなタイミングを生成するものである。
【００４１】
すなわち、チャージポンプ部４は、予め設定された一定のしきい値を有しており、非反転出力信号１／２ＣＬＫのＨｉｇｈ期間の中間点となる時点を捉えるために電圧制御するものであり、この制御電圧（直流成分）をタイミング調整回路部４の入力側に負帰還させて入力信号に付加させるものである。
【００４２】
図１に示すように、チャージポンプ部４１は、トライステート反転出力バッファ４１１と、直流電位制御する抵抗４１２及びコンデンサ４１３と、コレクタ接地回路４１４とを有する。
【００４３】
トライステート反転出力バッファ４１１は、ノイズ除去部４３である抵抗４３及びコンデンサ４４と接続しており、ノイズ除去部４３からノイズが除去された直流成分が付加された信号を受け取り、また、１／２分周回路部２から１／２ＣＬＫ＿Ｎを反転したものを取りこみ、一定のしきい値に基づいて反転出力を行なうものである。
【００４４】
すなわち、トライステート反転出力バッファ４１１は、ノイズ除去部４３から直流電位が付加された信号の電位が、しきい値以上である場合はＬｏｗとして出力し、しきい値未満である場合はＨｉｇｈとして出力する。
【００４５】
トライステート反転出力バッファ４１１は、チャージポンプ部４１から出力される直流電位が高い場合、しきい値が一定であるので、しきい値以上の電位となる期間が長くなり、しきい値未満となる期間が短くなる。また、トライステート反転出力バッファ４１１は、チャージポンプ部４１から出力される直流電位が低い場合、しきい値以上の電位となる期間が短くなり、しきい値未満となる期間が長くなる。
【００４６】
なお、本実施形態では、トライステート反転出力バッファ４１１としてバイポーラ（規格７４ＡＬＳ２４０）を使用する。
【００４７】
直流電位制御部である抵抗４１２及びコンデンサ４１３は、トライステート反転出力バッファ４１１からの出力電位に応じて、電位を調整制御するものである。つまり、抵抗４１２及びコンデンサ４１３は、トライステート反転出力バッファ４１１からの出力電位がＬｏｗである場合、コンデンサ４１３に蓄積されている電荷が流出し、Ｈｉｇｈである場合、コンデンサ４１３に電荷が流入することで電位を調整制御する。
【００４８】
コレクタ接地回路４１４は、インピーダンスを変換するものである。
【００４９】
また、タイミング調整回路部５は、ＬＰＦ部３から高周波成分が除去された反転出力信号１／２ＣＬＫ＿Ｎと、１／２分周回路２から非反転出力信号１／２ＣＬＫとを受け取り、非反転出力信号１／２ＣＬＫがＬｏｗである期間に対し、この期間がちょうど中間となるタイミングを生成するものである。また、タイミング調整管理５は、非反転出力信号１／２ＣＬＫのＬｏｗである期間の中間となるタイミングを生成し、その生成したタイミングを出力ＣＬＫ合成回路部６に与える。
【００５０】
タイミング調整回路部５も、直流成分除去部５２と、ノイズ除去部５３と、チャージポンプ部５１とを有しており、これら構成要件の機能はタイミング調整回路部４の各構成要件と対応するものである。
【００５１】
チャージポンプ部５１は、ノイズ除去部５３からノイズが除去された出力信号を受け取り、また１／２分周回路部２からの非反転出力信号１／２ＣＬＫを反転したものを取り込み、非反転出力信号１／２ＣＬＫのＬｏｗ期間において、ノイズ除去部５３からの直流成分を付加した出力信号について、しきい値以上の電位となる期間（図３（Ｄ）のＴ３期間）と、しきい値未満の電位となる期間（図３（Ｄ）のＴ４期間）とが一致するようなタイミングを生成するものである。
【００５２】
出力クロック合成回路部６は、タイミング調整回路部４から非反転出力信号１／２ＣＬＫのＨｉｇｈ期間の中間となるタイミングと、タイミング調整回路部５から非反転出力信号１／２ＣＬＫのＬｏｗ期間の中間となるタイミングとを受け取り、また、１／２分周回路２から反転出力信号１／２ＣＬＫ及び非反転出力信号１／２ＣＬＫ＿Ｎを受け取り、これらを合成して非反転出力信号１／２ＣＬＫの２倍の周波数のクロック信号（すなわち、ＣＬＫＩＮ端子１に入力した入力信号（ＣＬＫＩＮ）と同じ周波数のクロック信号）であって、そのクロック信号のデューティー比の比率が等しく（すなわち、デューティー比が５０％）調整したクロック信号を出力するものである。
【００５３】
図１に示すように、出力クロック合成回路部６は、タイミング調整回路部５からの出力信号を反転した信号と１／２分周回路部２からの反転出力信号１／２ＣＬＫ＿Ｎとに基づいて論理積をとる論理積回路６１と、タイミング調整回路部４からの出力信号と１／２分周回路２部からの非反転出力信号１／２ＣＬＫとに基づいて論理積をする論理積回路６２と、論理積回路６１及び６２からの出力に基づいて排他的論理和をする排他的論理和回路６３とを有するものである。
【００５４】
出力クロック合成回路部６は、図１に示すように論理ゲートであるので、ＦＰＧＡの内部で構成するようにしてもよい。
【００５５】
（Ａ−２）第１の実施形態の動作
次に、第１の実施形態のデューティー比自動調整装置の動作について図面を参照して説明する。
【００５６】
なお、図３は、第１の実施形態のデューティー比自動調整装置の動作を示すフローチャートであり、図３も参照しながら説明する。
【００５７】
図３（Ａ）に示すように、ＣＬＫＩＮ端子１からの入力信号が、Ｄ型フリップフロップＤ−ＦＦ２１に与えられ、その入力信号の周波数が１／２に分周され、非反転出力信号１／２ＣＬＫが、Ｄ型フリップフロップＤ−ＦＦ２１のＱ出力端子から出力される。
【００５８】
図３（Ｂ）及び（Ｃ）に示すように、Ｄ型フリップフロップＤ−ＦＦ２１において、入力信号の立ち上がりエッジ毎に非反転出力信号１／２ＣＬＫが反転されて、反転出力信号１／２ＣＬＫ＿Ｎが、Ｄ型フリップフロップＤ−ＦＦ２１のＱ（バー）出力端子からＬＰＦ部３に与えられる。
【００５９】
また、この反転出力信号１／２ＣＬＫ＿Ｎは、Ｄ型フリップフロップＤ−ＦＦ２１のＤ入力端子に帰還される。
【００６０】
Ｄ型フリップフロップＤ−ＦＦ２１から与えられた反転出力信号１／２ＣＬＫは、ＬＰＦ部３において、高周波成分が除去されてタイミング調整回路部４及び５に与えられる。
【００６１】
タイミング調整回路部４において、ＬＰＦ部３からの出力信号は、直流成分除去部４２であるコンデンサ４２１により直流成分が除去される。
【００６２】
反転出力信号１／２ＣＬＫ＿Ｎに含まれる直流成分が除去された出力は、図３（Ｄ）に示すように、チャージポンプ部４１から直流電位が調整された直流成分が付加されて、その直流成分が付加された出力信号が、ノイズ除去部４３である抵抗４３１及びコンデンサ４３２に与えられ、ノイズが除去される。
【００６３】
ノイズ除去部４３からの出力信号は、チャージポンプ部４１の論理否定回路４１１に与えられる。
【００６４】
トライステート反転出力バッファ４１１において、一定のしきい値に基づいて、ノイズ除去部４３からの出力電位に応じた論理否定が行われる。
【００６５】
つまり、トライステート反転出力バッファ４１１において、ノイズ除去部４３からの出力について付加されている直流電位が高い場合、トライステート反転出力バッファ４１１のしきい値は一定であるため、トライステート反転出力バッファ４１１からの出力は、図３（Ｄ）に示すＴ１の期間（すなわち、電位がしきい値以上である期間）が、図３（Ｄ）に示すＴ２の期間（すなわち、電位がしきい値未満である期間）よりも長くなるように出力される。
【００６６】
また、ノイズ除去部４３からの出力について付加されている直流電位が低い場合、トライステート反転出力バッファ４１１からの出力は、図３（Ｄ）に示すＴ２の期間（すなわち、電位がしきい値未満である期間）が、図３（Ｄ）に示すＴ１の期間（すなわち、電位がしきい値以上である期間）よりも長くなるように出力される。
【００６７】
電流電位制御部である抵抗４１２及びコンデンサ４１３により、トライステート反転出力バッファ４１１からの出力電位に応じた電荷が制御される。
【００６８】
すなわち、トライステート反転出力バッファ４１１からの出力電位がＬｏｗである場合（図３（Ｄ）のＴ１の期間）、コンデンサ４１３から電荷が流出し、トライステート反転出力バッファ４１１からの出力電位がＨｉｇｈである場合（図３（Ｄ）のＴ２の期間）、コンデンサ４１３に電荷が流入する（図３（Ｅ））。
【００６９】
コンデンサ４１３の電荷の増減によるコンデンサの電極間の電圧は、コレクタ接地回路４１４によりインピーダンス変換が行われ、直流成分が直流成分除去部４２１の出力に対して負帰還される。
【００７０】
例えば、チャージポンプ部４１において、非反転出力信号１／２ＣＬＫのＨｉｇｈ期間で、チャージポンプ部４１への入力信号に付加されている直流電位が高い場合、すなわちＴ１の期間がＴ２に対して長い場合を例にして説明する。
【００７１】
この場合、トライステート反転出力バッファ４１１からの出力電位について、ｈｉｇｈとなる期間よりｌｏｗとなる期間の方が長くなり、これは、チャージポンプ部４１のコンデンサ４１３ヘ電荷が流入する時間に対し電荷が流出する時間が長くなることとなる（図３（Ｅ））。
【００７２】
従って、コンデンサ４１３の電荷は減少し、電極間の電圧も下がる。この電圧は、後段のコレクタ接地回路４１４によってインピーダンス変換され、チャージポンプ部４１の入力側へ帰還することにより、ＬＰＦ部３からの出力（図３（Ｄ）に示す出力）に付加される直流電位が下がることになる。
【００７３】
また例えば、チャージポンプ部４１において、非反転出力信号１／２ＣＬＫのＨｉｇｈ期間で、チャージポンプ部４１への入力信号に付加されている直流電位が低い場合、すなわちＴ１の期間がＴ２に対して短い場合は、トライステート反転出力バッファ４１１からの出力電位について、ｈｉｇｈとなる期間よりｌｏｗとなる期間の方が短くなり、これは、チャージポンプ部４１のコンデンサ４１３ヘ電荷が流入する時間に対し電荷が流出する時間が短くなることとなる。
【００７４】
従って、コンデンサ４１３の電荷は増加し、電極間の電圧も上がるので、この電圧は、後段のコレクタ接地回路４１４によってインピーダンス変換され、チャージポンプ４１の入力側へ帰還することにより、ＬＰＦ部３からの出力（図３（Ｄ）に示す出力）に付加される直流電位が上がることになる。
【００７５】
また、チャージポンプ部４１において、非反転出力信号１／２ＣＬＫのＬｏｗ期間は、トライステート反転出力バッファ４１１の出力はハイインピーダンスとなり、コンデンサ４１３の電荷は流入も流出もせず、そのときの状態に保持される（図３（Ｅ））。
【００７６】
このような動作を繰り返す事によって、チャージポンプ部４１からの出力はちょうどＴ１の期間＝Ｔ２の期間となるようなタイミングが自動的に制御されて、出力ＣＬＫ合成回路部６に出力される（図Ｇ）。
【００７７】
また、ＬＰＦ部３からの出力信号は、タイミング調整回路部５にも与えられ、タイミング調整回路部５において、非反転出力信号１／２ＣＬＫのＬｏｗ期間に対して、中間となるようなタイミングが自動的に制御されて、出力ＣＬＫ合成回路部６に出力される（図３（Ｆ）及び（Ｈ））。
【００７８】
１／２分周回路部２からの非反転出力信号１／２ＣＬＫ及び反転出力信号１／２ＣＬＫ＿Ｎと、タイミング調整回路部４からの非反転出力１／２ＣＬＫのＨｉｇｈ期間の中間となる出力信号及びタイミング調整回路部５からの非反転出力１／２ＣＬＫのＬｏｗ期間の中間となる出力信号とを受け取り、これらの信号に基づいて、非反転出力信号１／２ＣＬＫの２倍の周波数であり、デューティー比が５０％に調整されたクロック信号が出力される（図３（Ｉ））。
【００７９】
（Ａ−３）第１の実施形態の効果
以上、本実施形態によれば、出力ＣＬＫ合成回路部６からクロック信号が出力されるまでの過程で、出力されるクロック信号以上の周波数を持つクロック信号を発生させていないため、ＥＭＩの特性を損なうことなくデューティー比の整ったクロック信号を得ることができる。
【００８０】
また、本実施形態によれば、ＰＬＬ回路を備える必要がないので、回路構成を安価にすることができ、ＰＬＬ回路を備える場合に比べて非常に低コストで構成させることができる。また、出力ＣＬＫ合成回路部６の論理ゲートの部分についてＦＰＧＡの空きゲート等を利用することもでき、装置の実装面積も非常に小さくすることができる。
【００８１】
さらに、本実施形態によれば、装置の初段に１／２分周回路部２を備え、入力信号（ＣＬＫＩＮ）を分周して、入力信号（ＣＬＫＩＮ）を正規化することができるため、入力信号（ＣＬＫＩＮ）のデューティー比の偏り具合に変動があったとしても、出力クロック信号は全く影響を受けずに済むことができる。
【００８２】
（Ｂ）他の実施形態
（Ｂ−１）上述した実施形態のデューティー比自動調整装置は、他装置から供給されたクロック信号に基づいて動作するディジタル電子回路に広く適用することができる。
【００８３】
特に、外部からのクロック信号を分周することなく使用する電子回路装置や、外部からのクロック信号を逓倍して使用する電子回路装置や、又は縦続接続する複数の装置が後段の装置へ同じクロック信号を分配する電子回路装置に適用することができる。
【００８４】
（Ｂ−２）上述したデューティー比自動調整装置を縦続接続する装置に適用した場合の例を図４に示す。
【００８５】
図４は、縦続接続する６台のマルチキャビネット型ＰＢＸ（Ｐｒｉｖａｔｅ Ｂｒａｎｃｈ Ｅｘｃｈｎｇｅ）８−１〜８−６に、デューティー比自動調整装置１００−２〜１００−６を備えさせた場合の全体概念を示したものである。
【００８６】
従来では、各マルチキャビネット型ＰＢＸ８−１〜８−６は、それぞれＰＬＬ回路を備えることが必要であった。
【００８７】
しかし、図４に示すように、６台のマルチキャビネット型ＰＢＸ８−１〜８−６のうち、外部から網同期クロックを最初に供給されるマルチキャビネット型ＰＢＸ８−１が、ＰＬＬ回路９を備えこととし、それ以降の後段のマルチキャビネット型ＰＢＸ８−２〜８−６が、上述した実施形態のデューティー比自動調整回路１００−２〜１００−６を備えるものとすることで、各マルチキャビネット型ＰＢＸ８−２〜８−６が高価で取扱の難しいＰＬＬ回路を備えることなく安定したクロック信号を後段のマルチキャビネット型ＰＢＸに供給することが可能となる。
【００８８】
【発明の効果】
以上、本発明によれば、外部からのクロック信号を調整する過程で出力クロック信号以上の周波数を持つクロック信号を発生させずにクロック信号のデューティー比の比率を等しく調整できるので、ＥＭＩの特性を損なうことない。
【００８９】
また、本発明によれば、受信側装置がＰＬＬ回路を備える必要がないので、ＰＬＬ回路を備える場合に比べて非常に低コストで構成させることができ、又装置の実装面積も非常に小さくすることができる。
【図面の簡単な説明】
【図１】第１の実施形態のデューティー比自動調整装置の回路構成を示した回路図である。
【図２】送出側装置から送出されるクロック信号の波形が変形する様子を示す説明図である。
【図３】第１の実施形態のデューティー比自動調整装置の動作を示すタイムチャートである。
【図４】他の実施形態に利用した場合の全体構成図である。
【図５】第１の実施形態のデューティー比自動調整装置の内部構成を示したブロック図である。
【符号の説明】
１００…デューティー比自動調整装置、２…１／２分周回路部、３…ＬＰＦ部、
４…タイミング調整回路部、５…タイミング調整回路部、
６出力クロック（ＣＬＫ）合成回路部。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an automatic duty ratio adjustment device, for example, a duty ratio (duty ratio) of a clock signal provided in a receiving side device that uses a clock signal supplied from another device and uses the clock signal adjusted based on the clock signal. It can be applied to an adjusting device.
[0002]
[Prior art]
Conventionally, in a digital electronic circuit device, there are the following techniques for adjusting the duty ratio of a clock signal supplied from the outside.
[0003]
(1) By sending a frequency twice as high as that of the clock signal required by the receiving side device from the sending side device in advance and dividing and using the frequency twice that of the clock signal in the receiving side device, Waveform collapse (duty ratio deviation) on the transmission line can be ignored.
[0004]
(2) The receiving side device includes a PLL circuit, and the PLL circuit is used in synchronization with an external clock signal based on a highly accurate clock signal oscillated in the receiving side device.
[0005]
(3) Define the range of waveform distortion on the transmission line and design with a large margin.
[0006]
[Problems to be solved by the invention]
By the way, in recent years, high frequency clocking of digital electronic circuit devices has become violent, and the need for a design that takes into account EMI (Electromagnetic Interference) is increasing.
[0007]
In particular, the clock signal flowing in the cable between the backboard and the device has a large influence on EMI. Therefore, the high frequency component of the clock signal is removed by using an EMI filter, a damping resistor, or the like, so that the rectangular waveform approximates a sine waveform. It is common to use a waved waveform.
[0008]
However, in the receiving side device, it is difficult to keep the threshold value of the receiver IC at the center potential with respect to the amplitude range of the clock signal, and the duty ratio of the clock signal that has returned to the rectangular wave again on the output side of the receiver IC is lost. It will be.
[0009]
FIG. 2 is an explanatory diagram for explaining how the duty ratio of the clock signal changes.
[0010]
In FIG. 2, when the original signal (A) is sent to the transmission line, the clock signal is sent as a rounded waveform as shown in (B). In the receiving apparatus, the received clock signal is reproduced in a rectangular waveform based on the threshold value of the receiver IC, but the threshold value is set to a position where the duty ratio is necessarily 50%. It is not always possible.
[0011]
In particular, in the case of a device configuration in which the same circuit is connected in cascade, the duty ratio is biased in the same direction every time it is transmitted to a subsequent device, which eventually breaks down.
[0012]
In addition, logic simulation performed in LSI and FPGA design is often performed only on the assumption that the duty ratio of the clock signal is 50%, and the deviation of the duty ratio may cause an unexpected malfunction.
[0013]
In order to avoid this, the conventional technique as described above is adjusted so that the duty ratio of the clock signal is 50%. However, the above-described conventional technique has the following problems.
[0014]
(1) Since the sending side device needs to send a frequency twice as high as the clock signal to the receiving side device, there is a problem that the EMI characteristics deteriorate. In addition, since a correspondence relationship between the transmission-side device and the reception-side device is required, there is a problem that the transmission-side device cannot be applied when the transmission-side device is a different product from the reception-side device.
[0015]
(2) Although the clock signal with the highest accuracy can be expected because the receiving side apparatus uses the PLL circuit, there is a problem that the cost of the voltage controlled oscillator (VCO) used for the PLL circuit is very high. Further, there is a problem that the circuit is likely to be complicated and consumes a large substrate area.
[0016]
(3) The degree of freedom in design becomes low and the design becomes difficult. Further, it can be applied only when the characteristics of the transmission side device and the characteristics of the transmission path are known, and there is a problem that it is greatly affected when a design change occurs in the transmission side device.
[0017]
Therefore, in order to solve the above-described problems, there is a need for an automatic duty ratio adjusting device that automatically adjusts the duty ratio of a clock signal in the receiving side device.
[0018]
[Means for Solving the Problems]
In order to solve such a problem, the automatic duty ratio adjustment device of the present invention receives a clock signal with a biased duty ratio from the outside, and in the duty ratio automatic adjustment device that adjusts the ratio of the duty ratio of the clock signal equally, The frequency dividing means for dividing the frequency of the clock signal from the frequency divider by 1/2, the high frequency component removing means for removing the high frequency component contained in the frequency divided signal from the frequency dividing means, and the high frequency component during the High period of the frequency divided signal First voltage control means for adjusting the direct current component of the output waveform so that the period in which the potential of the output waveform from the removing means is equal to or greater than the threshold and the period in which the potential is less than the threshold are equal; In the Low period, the period in which the potential of the output waveform from the high frequency component removing means is equal to or higher than the threshold and the period in which the potential is lower than the threshold are equal A second voltage control means for adjusting a direct current component of the force waveform; an intermediate timing signal in the High period of the frequency-divided signal from the first voltage control means; and a low-level signal of the frequency-divided signal from the second voltage control means. And duty ratio adjusting means for adjusting the ratio of the duty ratio of the clock signal equally based on the intermediate timing signal in the period.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
(A) First embodiment
A first embodiment of an automatic duty ratio adjusting device of the present invention will be described with reference to the drawings.
[0020]
In this embodiment, the ratio of the duty ratio of the clock signal is equal (that is, the duty ratio is 50%) in the digital electronic circuit on the reception side based on the clock signal supplied from the transmission side device. This is a case where the present invention is applied to an automatic duty ratio adjusting device that adjusts to.
[0021]
In the present embodiment, the frequency of the input clock signal is assumed to be 8 MHz.
[0022]
(A-1) Configuration of the first embodiment
FIG. 5 is a block diagram showing a functional configuration of the automatic duty ratio adjusting device of the present embodiment. FIG. 1 is a circuit diagram showing a circuit configuration of the automatic duty ratio adjusting device of the present embodiment. Below, it demonstrates in detail, referring FIG.1 and FIG.5.
[0023]
As shown in FIG. 5, the automatic duty ratio adjusting apparatus 100 of the present embodiment includes a 1/2 frequency dividing circuit unit 2, a low-pass filter (LPF) unit 3, timing adjusting circuit units 4 and 5, an output clock ( CLK) combining circuit portion 6.
[0024]
The ½ divider circuit unit 2 receives the input signal (CLKIN) from the CLKIN terminal 1, divides the frequency of the input signal (CLKIN) by ½, and normalizes the non-inverted output signal 1 / 2CLK is generated.
[0025]
As shown in FIG. 1, the CK input terminal of the D-type flip-flop D-FF 21 is connected to the CLKIN terminal 1, and the Q output terminal is connected to the timing adjustment circuit unit 5. The Q (bar) inversion output terminal of the D-type flip-flop D-FF 21 is connected to the LPF unit 3. The D-type flip-flop D-FF21 inverts the non-inverted output signal 1 / 2CLK at every falling edge of the input signal (CLKIN), and outputs the inverted output signal 1 / 2CLK_N from the Q (bar) inverted output terminal to the LPF unit. 3 is output.
[0026]
Further, the Q (bar) inverted output terminal of the D flip-flop D-FF21 is connected to the D input terminal of the D flip-flop D-FF21 itself, and the inverted output signal 1 / 2CLK_N is fed back to the D input terminal. .
[0027]
Note that the ½ divider circuit section 2 of the present embodiment is provided with a D-type flip-flop D-FF21 and is shown as a feedback of the inverted output signal 1 / 2CLK_N from the Q (bar) inverted output terminal. However, a T-type flip-flop or a counter may be used as long as the frequency of the input signal (CLKIN) can be divided.
[0028]
In FIG. 1, the feedback resistor 22 (220Ω) is for delaying the inverted output signal 1 / 2CLK_N to prevent the generation of a double clock. This double clock is a phenomenon in which the output signal is inverted twice when the input signal (CLKIN) is inverted due to the influence of noise, reflected waves, etc. included in the input signal (CLKIN).
[0029]
The 1/2 divider circuit section 2 gives the non-inverted output signal 1 / 2CLK output from the Q output terminal to the timing adjustment circuit section 5, and the inverted output signal 1 output from the Q (bar) output terminal. / 2CLK_N is supplied to the timing adjustment circuit unit 4.
[0030]
The LPF unit 3 receives the inverted output signal 1 / 2CLK_N from the 1/2 frequency divider circuit unit 2, and removes the high frequency component of the inverted output signal 1 / 2CLK_N. The LPF unit 3 is connected to the timing adjustment circuit units 4 and 5 and provides a signal from which the high frequency component of the inverted output signal 1 / 2CLK_N is removed.
[0031]
As shown in FIG. 1, the LPF unit 3 is a simple lag filter using CR, but another LPF may be used.
[0032]
Note that the LPF unit 3 is shown as having a resistor 31 (47Ω) and a capacitor 32 (560 pF), but this is because a clock signal with a frequency of 8 MHz is assumed. It is necessary to adjust the resistance value and the capacitor value according to the frequency.
[0033]
Further, the output potential Vout output from the LPF unit 3 is represented by the following equation.
[0034]

The timing adjustment circuit unit 4 receives the inverted output signal 1 / 2CLK_N from which the high frequency component has been removed from the LPF unit 3 and the inverted output signal 1 / 2CLK_N from the 1/2 frequency divider circuit 2, and receives the non-inverted output signal 1 / 2CLK. The timing at which this period is exactly the middle is generated with respect to the period in which is high. In addition, the timing adjustment circuit unit 4 generates a timing that is an intermediate period during which the non-inverted output signal 1 / 2CLK is High, and supplies the output CLK synthesis circuit unit 6 with a signal that rises at the generated timing.
[0035]
As illustrated in FIG. 5, the timing adjustment circuit unit 4 includes a DC component removing unit 42, a noise removing unit 43, and a charge pump unit 41.
[0036]
The DC component removing unit 42 receives the inverted output signal 1 / 2CLK_N from the LPF unit 3 and removes the DC component of the inverted output signal 1 / 2CLK_N. The DC component removing unit 42 gives the inverted output signal 1 / 2CLK_N from which the DC component has been removed to the noise removing unit.
[0037]
As shown in FIG. 1, the DC component removal unit 42 includes a capacitor 421 that is connected to the LPF unit 3.
[0038]
The noise removing unit 43 receives a signal obtained by adding a direct current component whose direct current potential is adjusted from the charge pump unit 41 to the inverted output signal 1 / 2CLK_N from the direct current component removing unit 42, and the signal of the signal obtained by adding the direct current component. It is a filter that removes noise components. The noise removing unit 43 provides the output signal from which the noise component has been removed to the charge pump unit 41.
[0039]
Here, the direct current component added to the output signal is obtained by adjusting the direct current potential by the charge pump unit 41 so as to generate a timing at which the High period of the inverted output signal 1 / 2CLK is exactly in the middle. That is, the DC component whose DC potential has been adjusted is negatively fed back from the charge pump unit 41, and the noise removing unit 43 incorporates the DC component added to the output signal from the DC component removing unit 42.
[0040]
The charge pump unit 41 receives the output signal from which noise has been removed from the noise removing unit 43, takes in the inverted output signal 1 / 2CLK_N from the 1/2 frequency divider circuit unit 2, and takes the inverted output signal 1 / In the High period of 2CLK, the output signal to which the DC component from the noise removing unit 43 is added has a period that is a potential higher than the threshold (T1 period in FIG. 3D) and a potential that is lower than the threshold. A timing is generated such that the period (the period T2 in FIG. 3D) coincides.
[0041]
That is, the charge pump unit 4 has a predetermined constant threshold value, and performs voltage control in order to capture a time point that is an intermediate point of the High period of the non-inverted output signal 1 / 2CLK. This control voltage (DC component) is negatively fed back to the input side of the timing adjustment circuit unit 4 and added to the input signal.
[0042]
As shown in FIG. 1, the charge pump unit 41 includes a tristate inversion output buffer 411, a resistor 412 and a capacitor 413 that control a DC potential, and a collector ground circuit 414.
[0043]
The tri-state inversion output buffer 411 is connected to the resistor 43 and the capacitor 44 which are the noise removing unit 43, receives a signal to which a DC component from which noise has been removed is added from the noise removing unit 43, and also has a 1/2 An inverted version of 1 / 2CLK_N is taken from the frequency dividing circuit 2 and an inverted output is performed based on a certain threshold value.
[0044]
That is, the tri-state inversion output buffer 411 outputs as Low when the potential of the signal to which the DC potential is added from the noise removing unit 43 is equal to or higher than the threshold value, and outputs as High when the potential is lower than the threshold value. To do.
[0045]
The tri-state inversion output buffer 411 has a constant threshold value when the DC potential output from the charge pump unit 41 is high, and therefore, the period during which the potential is equal to or higher than the threshold value becomes long and becomes less than the threshold value. The period is shortened. In addition, when the DC potential output from the charge pump unit 41 is low, the tri-state inversion output buffer 411 has a shorter period during which the potential is equal to or higher than the threshold and a longer period during which the potential is less than the threshold.
[0046]
In the present embodiment, bipolar (standard 74ALS240) is used as the tristate inversion output buffer 411.
[0047]
The resistor 412 and the capacitor 413, which are DC potential control units, adjust and control the potential according to the output potential from the tristate inversion output buffer 411. That is, in the resistor 412 and the capacitor 413, when the output potential from the tristate inversion output buffer 411 is Low, the charge accumulated in the capacitor 413 flows out, and when the output potential is High, the charge flows into the capacitor 413. To adjust the potential.
[0048]
The collector ground circuit 414 converts impedance.
[0049]
Further, the timing adjustment circuit unit 5 receives the inverted output signal 1 / 2CLK_N from which the high frequency component has been removed from the LPF unit 3 and the non-inverted output signal 1 / 2CLK from the 1/2 frequency divider circuit 2, and receives the non-inverted output signal. The timing at which this period is exactly the middle is generated with respect to the period in which 1 / 2CLK is Low. Further, the timing adjustment management 5 generates a timing that is an intermediate period during which the non-inverted output signal ½ CLK is Low, and supplies the generated timing to the output CLK synthesis circuit unit 6.
[0050]
The timing adjustment circuit unit 5 also includes a DC component removal unit 52, a noise removal unit 53, and a charge pump unit 51, and the functions of these configuration requirements correspond to the configuration requirements of the timing adjustment circuit unit 4. It is.
[0051]
The charge pump unit 51 receives the output signal from which noise has been removed from the noise removing unit 53, and takes in the inverted signal of the non-inverted output signal 1 / 2CLK from the 1/2 frequency dividing circuit unit 2, and outputs the non-inverted output signal In the ½ CLK Low period, the output signal to which the DC component from the noise removing unit 53 is added has a period (T3 period in FIG. 3D) that is equal to or higher than the threshold and a potential that is lower than the threshold. The timing is generated so as to coincide with the period (T4 period in FIG. 3D).
[0052]
The output clock synthesizing circuit unit 6 includes a timing that is the middle of the high period of the non-inverted output signal 1 / 2CLK from the timing adjustment circuit unit 4, and an intermediate of the low period of the non-inverted output signal 1 / 2CLK from the timing adjustment circuit unit 5. In addition, the inverted output signal 1 / 2CLK and the non-inverted output signal 1 / 2CLK_N are received from the 1/2 divider circuit 2, and these are combined to have a frequency twice that of the non-inverted output signal 1 / 2CLK. Clock signal (that is, a clock signal having the same frequency as the input signal (CLKIN) input to the CLKIN terminal 1), and the clock signal having the same duty ratio ratio (that is, the duty ratio is 50%) adjusted. A signal is output.
[0053]
As shown in FIG. 1, the output clock synthesizing circuit unit 6 performs logic based on a signal obtained by inverting the output signal from the timing adjustment circuit unit 5 and an inverted output signal ½ CLK_N from the ½ divider circuit unit 2. A logical product circuit 61 that takes a product, a logical product circuit 62 that performs a logical product based on the output signal from the timing adjustment circuit unit 4 and the non-inverted output signal 1 / 2CLK from the 1/2 frequency divider circuit 2 unit, And an exclusive OR circuit 63 for performing an exclusive OR based on outputs from the AND circuits 61 and 62.
[0054]
Since the output clock synthesis circuit unit 6 is a logic gate as shown in FIG. 1, it may be configured inside the FPGA.
[0055]
(A-2) Operation of the first embodiment
Next, the operation of the automatic duty ratio adjusting device of the first embodiment will be described with reference to the drawings.
[0056]
FIG. 3 is a flowchart showing the operation of the automatic duty ratio adjusting apparatus of the first embodiment, and will be described with reference to FIG.
[0057]
As shown in FIG. 3A, the input signal from the CLKIN terminal 1 is applied to the D-type flip-flop D-FF 21, the frequency of the input signal is divided by half, and the non-inverted output signal 1 / 2CLK is output from the Q output terminal of the D-type flip-flop D-FF21.
[0058]
As shown in FIGS. 3B and 3C, in the D-type flip-flop D-FF21, the non-inverted output signal 1 / 2CLK is inverted every rising edge of the input signal, and the inverted output signal 1 / 2CLK_N is The signal is supplied to the LPF unit 3 from the Q (bar) output terminal of the D-type flip-flop D-FF21.
[0059]
The inverted output signal 1 / 2CLK_N is fed back to the D input terminal of the D flip-flop D-FF21.
[0060]
The inverted output signal ½ CLK supplied from the D-type flip-flop D-FF 21 is supplied to the timing adjustment circuit units 4 and 5 after the high frequency component is removed in the LPF unit 3.
[0061]
In the timing adjustment circuit unit 4, a DC component is removed from the output signal from the LPF unit 3 by a capacitor 421 that is a DC component removal unit 42.
[0062]
As shown in FIG. 3D, the output from which the DC component included in the inverted output signal 1 / 2CLK_N is removed is added with the DC component whose DC potential is adjusted from the charge pump unit 41, and the DC component is The added output signal is applied to the resistor 431 and the capacitor 432 which are the noise removing unit 43, and noise is removed.
[0063]
An output signal from the noise removing unit 43 is given to the logic negation circuit 411 of the charge pump unit 41.
[0064]
In the tri-state inversion output buffer 411, a logical negation according to the output potential from the noise removing unit 43 is performed based on a certain threshold value.
[0065]
That is, in the tristate inversion output buffer 411, when the DC potential added to the output from the noise removing unit 43 is high, the threshold value of the tristate inversion output buffer 411 is constant. The output from the period T1 shown in FIG. 3D (that is, the period in which the potential is equal to or higher than the threshold value) is the period T2 shown in FIG. 3D (that is, the potential is less than the threshold value). It is output so as to be longer than a certain period.
[0066]
When the DC potential applied to the output from the noise removing unit 43 is low, the output from the tristate inversion output buffer 411 is the period T2 shown in FIG. 3D (that is, the potential is less than the threshold value). Is output so as to be longer than the period T1 shown in FIG. 3D (that is, the period in which the potential is equal to or higher than the threshold value).
[0067]
The electric charge according to the output potential from the tristate inversion output buffer 411 is controlled by the resistor 412 and the capacitor 413 which are current potential control units.
[0068]
That is, when the output potential from the tristate inversion output buffer 411 is Low (period T1 in FIG. 3D), the charge flows out from the capacitor 413, and the output potential from the tristate inversion output buffer 411 is High. In some cases (period T2 in FIG. 3D), charge flows into the capacitor 413 (FIG. 3E).
[0069]
The voltage between the electrodes of the capacitor due to the increase / decrease in the charge of the capacitor 413 is subjected to impedance conversion by the collector ground circuit 414, and the DC component is negatively fed back to the output of the DC component removing unit 421.
[0070]
For example, in the charge pump unit 41, when the DC potential added to the input signal to the charge pump unit 41 is high during the High period of the non-inverted output signal 1 / 2CLK, that is, when the period of T1 is longer than T2. Will be described as an example.
[0071]
In this case, the output potential from the tri-state inversion output buffer 411 is longer in the low period than in the high period. This is because the charge is charged with respect to the time when the charge flows into the capacitor 413 of the charge pump unit 41. The outflow time will be longer (FIG. 3E).
[0072]
Therefore, the electric charge of the capacitor 413 decreases and the voltage between the electrodes also decreases. This voltage is subjected to impedance conversion by the collector ground circuit 414 at the subsequent stage and fed back to the input side of the charge pump unit 41, whereby a direct current potential added to the output from the LPF unit 3 (the output shown in FIG. 3D). Will go down.
[0073]
Further, for example, in the charge pump unit 41, when the DC potential added to the input signal to the charge pump unit 41 is low during the High period of the non-inverted output signal 1 / 2CLK, that is, the period of T1 is shorter than T2. In this case, the output potential from the tri-state inversion output buffer 411 is shorter in the low period than in the high period. This is because the charge is charged with respect to the time when the charge flows into the capacitor 413 of the charge pump unit 41. The outflow time will be shortened.
[0074]
Accordingly, the charge of the capacitor 413 increases and the voltage between the electrodes also rises. Therefore, this voltage is impedance-converted by the collector ground circuit 414 in the subsequent stage, and is fed back to the input side of the charge pump 41, so that the voltage from the LPF unit 3 The DC potential added to the output (the output shown in FIG. 3D) is increased.
[0075]
Further, in the charge pump unit 41, during the low period of the non-inverted output signal 1 / 2CLK, the output of the tristate inverted output buffer 411 becomes high impedance, and the charge of the capacitor 413 does not flow in or out, and is maintained in the state at that time. (FIG. 3E).
[0076]
By repeating such an operation, the output from the charge pump unit 41 is automatically controlled so that the timing exactly equal to the period of T1 = the period of T2 is output to the output CLK synthesis circuit unit 6 (FIG. G).
[0077]
The output signal from the LPF unit 3 is also supplied to the timing adjustment circuit unit 5, and the timing adjustment circuit unit 5 automatically performs an intermediate timing with respect to the low period of the non-inverted output signal ½ CLK. And output to the output CLK synthesis circuit unit 6 (FIGS. 3 (F) and 3 (H)).
[0078]
The output signal and timing that are intermediate between the high period of the non-inverted output signal 1 / 2CLK and the inverted output signal 1 / 2CLK_N from the 1/2 frequency divider circuit unit 2 and the non-inverted output 1 / 2CLK from the timing adjustment circuit unit 4 An output signal that is an intermediate part of the low period of the non-inverted output 1 / 2CLK from the adjustment circuit unit 5 is received, and based on these signals, the frequency is twice that of the non-inverted output signal 1 / 2CLK, and the duty ratio is A clock signal adjusted to 50% is output (FIG. 3I).
[0079]
(A-3) Effects of the first embodiment
As described above, according to the present embodiment, a clock signal having a frequency equal to or higher than the output clock signal is not generated in the process until the clock signal is output from the output CLK synthesis circuit unit 6. A clock signal with a uniform duty ratio can be obtained without loss.
[0080]
Moreover, according to this embodiment, since it is not necessary to provide a PLL circuit, it is possible to reduce the circuit configuration, and it is possible to configure the circuit at a very low cost compared to the case where a PLL circuit is provided. In addition, an empty gate of the FPGA can be used for the logic gate portion of the output CLK synthesis circuit unit 6, and the mounting area of the device can be made very small.
[0081]
Further, according to the present embodiment, the first stage of the apparatus includes the 1/2 frequency divider circuit unit 2 and can divide the input signal (CLKIN) to normalize the input signal (CLKIN). Even if the duty ratio of the signal (CLKIN) varies, the output clock signal can be completely unaffected.
[0082]
(B) Other embodiments
(B-1) The duty ratio automatic adjustment device of the above-described embodiment can be widely applied to digital electronic circuits that operate based on a clock signal supplied from another device.
[0083]
In particular, an electronic circuit device that uses an external clock signal without dividing it, an electronic circuit device that uses an external clock signal by multiplying it, or a plurality of devices that are connected in cascade are connected to the subsequent device using the same clock. The present invention can be applied to an electronic circuit device that distributes signals.
[0084]
(B-2) FIG. 4 shows an example in which the above-described automatic duty ratio adjusting device is applied to a cascade connection device.
[0085]
FIG. 4 shows an overall concept when six multi-cabinet type PBXs (Private Branch Exchange) 8-1 to 8-6 connected in cascade are provided with automatic duty ratio adjusting devices 100-2 to 100-6. It is a thing.
[0086]
Conventionally, each multi-cabinet type PBX 8-1 to 8-6 has to be provided with a PLL circuit.
[0087]
However, as shown in FIG. 4, among the six multi-cabinet type PBXs 8-1 to 8-6, the multi-cabinet type PBX 8-1 to which a network synchronization clock is first supplied from the outside includes the PLL circuit 9. Then, the subsequent multi-cabinet type PBX 8-2 to 8-6 includes the duty ratio automatic adjustment circuits 100-2 to 100-6 of the above-described embodiment, so that each multi-cabinet type PBX 8- It is possible to supply a stable clock signal to the subsequent multi-cabinet type PBX without providing a PLL circuit that is expensive and difficult to handle.
[0088]
【The invention's effect】
As described above, according to the present invention, the ratio of the duty ratio of the clock signal can be adjusted equally without generating a clock signal having a frequency higher than that of the output clock signal in the process of adjusting the clock signal from the outside. There is no loss.
[0089]
In addition, according to the present invention, since it is not necessary for the receiving side apparatus to include a PLL circuit, the receiving side apparatus can be configured at a very low cost as compared with the case of including a PLL circuit, and the mounting area of the apparatus can be made very small. be able to.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a circuit configuration of an automatic duty ratio adjusting device according to a first embodiment.
FIG. 2 is an explanatory diagram showing a state in which the waveform of a clock signal sent from a sending side device is deformed.
FIG. 3 is a time chart showing the operation of the automatic duty ratio adjusting device of the first embodiment.
FIG. 4 is an overall configuration diagram when used in another embodiment.
FIG. 5 is a block diagram showing an internal configuration of the automatic duty ratio adjusting device of the first embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Duty ratio automatic adjustment apparatus, 2 ... 1/2 frequency divider circuit part, 3 ... LPF part,
4 ... Timing adjustment circuit unit, 5 ... Timing adjustment circuit unit,
6 output clock (CLK) synthesis circuit section.

Claims (2)

In a duty ratio automatic adjustment device that receives a clock signal with a biased duty ratio from the outside and adjusts the ratio of the duty ratio of the clock signal equally,
A frequency dividing means for dividing the frequency of the clock signal from the outside by 1/2;
High-frequency component removing means for removing high-frequency components contained in the frequency-divided signal from the frequency dividing means;
In the High period of the frequency-divided signal, the DC component of the output waveform is adjusted so that the period in which the potential of the output waveform from the high-frequency component removing means is equal to or higher than the threshold is equal to the period in which the potential is lower than the threshold. First voltage control means to:
The DC component of the output waveform is adjusted so that the period in which the potential of the output waveform from the high-frequency component removing unit is equal to or higher than the threshold and the period in which the potential is lower than the threshold are equal during the Low period of the divided signal. Second voltage control means for
The duty ratio of the clock signal based on the intermediate timing signal in the High period of the divided signal from the first voltage control means and the intermediate timing signal in the Low period of the divided signal from the second voltage control means An automatic duty ratio adjusting device, comprising: a duty ratio adjusting means for equally adjusting the ratio of the duty ratio. The first voltage control means is
A noise component removing unit that removes a noise component included in the output waveform from the high-frequency component removing unit;
An adjustment DC component addition unit for adding an adjustment DC component to the output waveform from which the noise component has been removed;
An adjusted DC component that controls charge inflow / outflow according to the comparison result between the potential of the output waveform to which the control potential is added and a threshold value, and adjusts the current potential according to the time difference between the charge outflow time and the charge inflow time. And a DC component adjustment unit that feeds back the adjusted DC component to the control voltage adding unit,
The second voltage control means is
A noise component removing unit that removes a noise component included in the output waveform from the high-frequency component removing unit;
An adjustment DC component addition unit for adding an adjustment DC component to the output waveform from which the noise component has been removed;
An adjusted DC component that controls charge inflow / outflow according to the comparison result between the potential of the output waveform to which the control potential is added and a threshold value, and adjusts the current potential according to the time difference between the charge outflow time and the charge inflow time. The automatic duty ratio adjusting device according to claim 1, further comprising: a direct current component adjusting unit that generates a feedback direct current of the adjusted direct current component to the control voltage adding unit.

Images