JP2005006048A - Signal processor, signal processing method, and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute the signal processing requiring the data of the peripheral pixels for obtaining the data after processing target pixels, and at the same time, to reduce the circuit scale and the costs of a signal processor. <P>SOLUTION: A plurality of signal processing LSIs composed of a pre-stage processing part 20 corresponding to the high resolution, a pixel selector 31, a pixel selecting signal generator 32, and a post-stage processor 40 corresponding to the low resolution, are arranged in parallel to input image data as for the high resolution. The signal processing requiring the peripheral pixel data is executed at the pre-stage processor 20. The signal processing not requiring the peripheral pixel data is executed at the post-stage processor 40. A part of the pixel data in the output image data of the pre-stage processor 20 is periodically extracted at the pixel selector 31 of each signal processing LSI mutually complementarily. The pixel data are processed at the post-stage processor 40. After that, they are synthesized at the switching circuit 50. One signal processing LSI is used as for the low resolution. All the pixel data are extracted at its pixel selecting part 31. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing device and a signal processing method for processing image data, and an image display device including the signal processing device.
[0002]
[Prior art]
Currently, video signal sources are mainly SDTV (Standard Definition Television) broadcasting and HDTV (High Definition Television) broadcasting, and image processing devices such as CRT displays, liquid crystal displays, plasma displays, and other signal processing adapted to various resolutions. Is required.
[0003]
As an image pickup apparatus, Patent Document 1 (Japanese Patent Laid-Open No. 7-240869) discloses that in the normal moving image mode, the image pickup optical system and the image pickup element are not displaced, and signals of each color obtained through the complementary color filter are not interpolated. In the high-resolution still image mode, the image pickup optical system and the image pickup element are relatively displaced pixel by pixel, and each color signal obtained through the complementary color filter is interpolated and output. .
[0004]
However, signal processing such as horizontal or vertical sharpness (contour emphasis or contour correction), gain adjustment, and bias adjustment is performed on high-resolution or low-resolution image data obtained from a signal source by an image display device or the like. As a method, conventionally, a high resolution signal processing apparatus as shown in FIG. 8 and a low resolution signal processing apparatus as shown in FIG. 9 are separately prepared and incorporated in corresponding devices. It has been.
[0005]
The example of FIGS. 8 and 9 shows a case where the signal processing device is configured as an LSI (Large Scale Integrated circuit). The signal processing LSI 60 for high resolution includes an image memory 62 in the signal processing unit 61 as necessary. The low-resolution signal processing LSI 70 processes the low-resolution input image data by using the image memory 72 as necessary in the signal processing unit 71. To do.
[0006]
However, the method of separately preparing the signal processing device for high resolution and the signal processing device for low resolution in this manner and using them properly according to the equipment requires the development and manufacturing costs of the signal processing device, for example, the signal processing LSI. Increase.
[0007]
Since the signal processing device for high resolution (signal processing LSI) can also cope with low resolution data, only the signal processing device for high resolution (signal processing LSI) is manufactured without corresponding individually as described above. A method of incorporating this into a low-resolution device is also conceivable. However, the cost of a high-resolution signal processing device is higher than that of a low-resolution signal processing device, so incorporating it into a low-priced low-resolution device is not commensurate with the price of the device. become.
[0008]
Therefore, as shown in FIG. 10, a plurality of (for example, two) low-resolution signal processing LSIs 70 as shown in FIG. 9 are provided in parallel for the input image data to constitute a signal processing apparatus. It can be shared with compatible devices and high-resolution devices.
[0009]
Specifically, the signal processing apparatus of FIG. 10 includes two signal processing LSIs 70A and 70B for low resolution, a division processing unit 81, and a synthesis processing unit 85, respectively.
[0010]
Unlike the case shown in FIG. 10, when the input image data is low resolution data, the low resolution input image data is supplied as it is to the signal processing LSI 70A as the image data S1 through the division processing unit 81. Then, the processed image data is extracted as low-resolution output image data as image data S3 through the synthesis processing unit 85 as it is.
[0011]
On the other hand, when the input image data is high resolution data as shown in FIG. 10, the division processing unit 81 allows the high resolution input image data to be processed by the low resolution signal processing LSIs 70A and 70B. Divided into image data of odd pixels (odd number pixels) and image data of even pixels (even number pixels), or image data of odd lines (odd number lines) and even lines (even number lines) Divided into image data.
[0012]
The odd pixel or odd line image data S1 is processed by the signal processing LSI 70A, and the even pixel or even line image data S2 is processed by the signal processing LSI 70B.
[0013]
Then, in the synthesis processing unit 85, image data S3 of odd pixels or odd lines after processing in the signal processing LSI 70A and image data S4 of even pixels or even lines after processing in the signal processing LSI 70B are pixels. Alternatively, by selecting and switching line by line, the image data of all pixels and all lines is combined, and high-resolution output image data is obtained from the combining processing unit 85.
[0014]
According to this method, only a low-resolution signal processing LSI 70 as shown in FIG. 9 is manufactured as a signal processing LSI, and a plurality of the signal processing LSIs 70 are used, and a split processing unit 81 and a synthesis processing unit 85 having a simple switch configuration. As compared with the method in which the signal processing LSI 60 for high resolution as shown in FIG. 8 and the signal processing LSI 70 for low resolution as shown in FIG. Can be reduced.
[0015]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 7-240869.
[0016]
[Problems to be solved by the invention]
As image signal processing, (1) in order to obtain the processed data of the target pixel (the relevant pixel), the same frame (in the case of non-interlaced image data) or the same field (in the case of interlaced image data) Signal processing that requires data of peripheral pixels in the horizontal direction (left and right direction) or vertical direction (up and down direction), and (2) in the same frame or the same field to obtain the processed data of the target pixel There is signal processing that does not require data of peripheral pixels in the horizontal direction or the vertical direction.
[0017]
As signal processing of (1), (1a) peripheral pixel data is required but frame memory or field memory for storing and holding image data for one screen is not required, horizontal sharpness, vertical sharpness, resolution conversion, etc. And (1b) signal processing such as motion adaptive interlace / non-interlace conversion that requires peripheral pixel data and requires a frame memory or a field memory.
[0018]
The signal processing of (2) includes (2a) signal processing such as gain adjustment and bias adjustment, which is processed for each pixel, which does not require peripheral pixel data and frame memory or field memory, and (2b) There is signal processing such as frame rate conversion and frame double speed, which does not require peripheral pixel data but requires a frame memory or a field memory.
[0019]
However, in the method shown in FIG. 10, when the input image data is high resolution data as shown in FIG. 10, the division processing unit 81 converts the high resolution input image data into an image of odd pixels or odd lines. Since the data S1 and the even pixel or even line image data S2 are divided, the signal processing LSIs 70A and 70B cannot perform the signal processing (1), that is, the signal processing (1a) and (1b).
[0020]
Therefore, as a method capable of performing the signal processing (1) even when the input image data is high resolution data, a method as shown in FIG. 11 is conceivable.
[0021]
Specifically, the signal processing apparatus in FIG. 11 includes two low-resolution signal processing LSIs 70A and 70B as shown in FIG. 9, and a division processing unit 91 and a synthesis processing unit 95 using line memories, respectively. Is done.
[0022]
Unlike the case shown in FIG. 11, when the input image data is low resolution data, the low resolution input image data is supplied as it is to the signal processing LSI 70A as the image data S5 through the division processing unit 91. The processed image data is extracted as image data S7 as low-resolution output image data through the synthesis processing unit 95 as it is.
[0023]
On the other hand, when the input image data is high-resolution data as shown in FIG. 11, the high-resolution input image data Si is written into the line memory by the division processing unit 91 with a high-frequency clock for high resolution. An image portion obtained by adding the left end portion α in the right half of the screen to the left half of the screen by being read from the line memory by a low-frequency clock for low resolution (a clock having a frequency ½ of the high-frequency clock). Image data S5 and image data S6 of the image portion obtained by adding the right end portion β in the left half of the screen to the right half of the screen.
[0024]
In FIG. 11, the horizontal width of one square of the image data S5 and S6 is twice the horizontal width of one square of the input image data Si. The clock frequency is reduced to ½ as described above. It shows that.
[0025]
The image data S5 in the left half of the screen is mainly processed by the signal processing LSI 70A, and the image data S6 in the right half of the screen is mainly processed by the signal processing LSI 70B.
[0026]
Then, in the synthesis processing unit 95, the image data on the left half of the screen excluding the portion α in the image data S7 processed by the signal processing LSI 70A and the portion β in the image data S8 processed by the signal processing LSI 70B. The image data on the right half of the screen, except for, is written to the line memory by a low-frequency clock for low resolution, and the line memory by a high-frequency clock for high resolution (a clock having twice the frequency of the low-frequency clock). Are combined with the image data of the entire screen, and high-resolution output image data So is obtained from the composition processing unit 95.
[0027]
According to this method, when the input image data is high resolution data, as described above, the division processing unit 91 converts the high resolution input image data Si into mainly the image data S5 in the left half of the screen and mainly the screen right. By dividing the image data into half of the image data S6, the signal processing (1) that requires peripheral pixel data can be performed.
[0028]
However, this method requires a line memory for each of the division processing unit 91 and the synthesis processing unit 95, which increases the circuit scale and cost of the signal processing device.
[0029]
Therefore, the present invention can perform the signal processing that requires the data of the peripheral pixels in order to obtain the processed data of the target pixel of (1), and reduce the circuit scale and cost of the signal processing device. It is something that can be done.
[0030]
[Means for Solving the Problems]
The signal processing device of the first invention is
A pre-processing unit capable of performing a first type of signal processing that requires data of peripheral pixels to obtain data after processing of a target pixel with respect to input image data;
A pixel selection unit capable of selectively extracting part of the pixel data in the output image data of the pre-stage processing unit;
A post-stage processing unit capable of performing the second type of signal processing that does not require the data of the peripheral pixels to obtain the processed data of the target pixel for the output image data of the pixel selection unit;
Is provided.
[0031]
The signal processing device of the second invention is
A plurality of signal processing devices according to the first aspect of the present invention are provided in parallel with respect to input image data as signal processing device sections,
In the pixel selection unit of each signal processing unit, a part of the pixel data in the output image data of the pre-processing unit is periodically extracted in a complementary manner,
The output image data of the subsequent stage processing unit of each signal processing unit is switched and combined and extracted as output image data after signal processing.
[0032]
In the signal processing apparatus according to the first aspect of the invention, the front-end processing unit is high-resolution compatible with relatively high processing capability, and the post-processing unit is low-resolution compatible with relatively low processing capability. For the low resolution, the first stage processing unit executes the first type of signal processing on the low resolution input image data as necessary, and the pixel selection unit includes the output image data of the previous stage processing unit. All the pixel data is extracted, and the second-stage signal processing unit executes the second type of signal processing on the output image data of the previous-stage processing unit through the pixel selection unit as necessary.
[0033]
The signal processing device according to the second invention is for high resolution, and the first-stage processing unit of each signal processing device unit performs the first type of signal processing on the high resolution input image data as necessary. Executed.
[0034]
In each pixel processing unit of each signal processing unit, odd pixel data is extracted by one pixel selection unit, and even pixel data is extracted by another pixel selection unit. In addition, a part of the pixel data is periodically extracted from the output image data of the pre-processing unit of each signal processing unit.
[0035]
In the subsequent processing unit of each signal processing device unit, the second type of signal processing is performed on the output image data of the pixel selection unit of each signal processing device unit as necessary. Finally, the signal processing is performed. As the subsequent output image data, high-resolution image data obtained by switching and synthesizing the output image data of the subsequent processing unit of each signal processing unit is obtained.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment: FIGS. 1 and 2]
FIG. 1 shows a first embodiment of a signal processing apparatus according to the present invention, which is an example when used for low resolution.
[0037]
The signal processing apparatus of this example is constituted by a pre-processing unit 20, a pixel selection unit 31, a pixel selection signal generation unit 32, and a post-processing unit 40, and is integrated as a signal processing LSI 10.
[0038]
The pre-processing unit 20 is compatible with high resolution, has a relatively high processing capability (high processing speed), and needs the data of peripheral pixels to obtain the processed data of the pixel of interest in (1) above. The post-processing unit 40 is compatible with low resolution, has a relatively low processing capability (processing speed is slow), and the processing of the pixel of interest in (2) above. It is assumed that signal processing that does not require peripheral pixel data can be performed to obtain subsequent data.
[0039]
Furthermore, in this example, the pre-processing unit 20 is assumed to have an image memory (frame memory or field memory) 22 connected to the signal processing unit 21 so that the signal processing of (1b) can be performed. The post-processing unit 40 is configured such that the image memory 42 is connected to the signal processing unit 41 so that the signal processing of (2b) can be performed.
[0040]
The pixel selection unit 31 is a circuit unit that can selectively extract a part of the pixel data in the output image data of the pre-processing unit 20 based on the pixel selection signal from the pixel selection signal generation unit 32. The pixel selection signal The generation unit 32 is a circuit unit that generates a pixel selection signal based on a horizontal synchronization signal, a pixel clock, and a pixel selection setting signal supplied from the outside of the signal processing LSI 10 and sends the pixel selection signal to the pixel selection unit 31.
[0041]
The signal processing apparatus of this example, that is, the signal processing LSI 10 can be used alone for low resolution. In this case, the pixel selection setting signal instructs to extract all the pixel data, and the pixel selection unit 31 controls the signal processing LSI 10 so that all the pixel data is extracted.
[0042]
Specifically, the upstream processing unit 20 performs the signal processing of (1) on the low resolution input image data as necessary, and the pixel selection unit 31 outputs the output image data of the upstream processing unit 20. All the pixel data is extracted, and the post-processing unit 40 performs the signal processing of (2) above on the output image data of the pre-processing unit 20 through the pixel selection unit 31 as necessary. Thus, low-resolution output image data after signal processing is obtained from the post-processing unit 40.
[0043]
Since this signal processing apparatus supports only the pre-processing unit 20 with high resolution, it is particularly effective when the circuit scale of the pre-processing unit 20 is smaller than the circuit scale of the post-processing unit 40 as will be described later. .
[0044]
FIG. 2 shows an example in which the circuit scale of the pre-processing unit 20 is smaller than the circuit scale of the post-processing unit 40 in this way.
[0045]
This example is a case where the signal processing of (2b) is performed as the signal processing of (2), and the signal processing of (1b) is not performed as the signal processing of (1). The post-processing unit 40 includes the image memory 42, and the pre-processing unit 20 does not include the image memory.
[0046]
The image memories 22 and 42 are preferably configured in the signal processing LSI 10 as in the example of FIG. 1 or FIG. 2, but may be externally connected.
[0047]
[Second Embodiment: FIGS. 3 to 7]
FIG. 3 shows a second embodiment of the signal processing apparatus according to the present invention, which is an example when used for high resolution.
[0048]
In this example, the processing capability of the low-resolution compatible post-processing unit 40 is ½ of the processing capability of the high-resolution pre-processing unit 20, and the signal processing LSI 10 shown in FIG. 1 or FIG. As shown as signal processing LSIs 11 and 12, two are provided in parallel to the input image data, and a switching circuit 50 is provided on the output side of the signal processing LSIs 11 and 12.
[0049]
The signal processing apparatus of this example can be used for high resolution. In this case, the pixel selection setting signal for the signal processing LSI 11 is instructed to extract data of odd-numbered pixels (odd-numbered pixels) of each line, and the pixel selection setting signal for the signal processing LSI 12 is set to an even number of each line. As an instruction to extract pixel (even-numbered pixel) data, the pixel selection unit 31 of the signal processing LSI 11 extracts odd-numbered pixel data, and the pixel selection unit 31 of the signal processing LSI 12 extracts even-numbered pixel data. The signal processing device is controlled so that data is extracted.
[0050]
Specifically, in the pre-processing unit 20 of the signal processing LSIs 11 and 12, respectively, the high resolution input image data Si as schematically shown in FIG. Signal processing is performed. That is, the same signal processing is executed in the pre-processing unit 20 of the signal processing LSIs 11 and 12.
[0051]
Then, the pixel selection unit 31 of the signal processing LSI 11 uses the odd pixel selection signal Sp from the pixel selection signal generation unit 32 as shown in FIG. The odd-numbered pixel data Se as schematically shown in (B) is extracted, and the signal processing LSI 11 performs the signal processing of (2) on the odd-numbered pixel data Se as necessary in the subsequent processing unit 40. Is done.
[0052]
In parallel with this, in the pixel selection unit 31 of the signal processing LSI 12, the output image data Sb of the pre-processing unit 20 of the signal processing LSI 12 is received by the even pixel selection signal Sq as shown in FIG. 5 from the pixel selection signal generation unit 32. From FIG. 4C, even pixel data Sf as schematically shown in FIG. 4C is extracted, and the post-processing unit 40 of the signal processing LSI 12 performs the above processing of (2) on the even pixel data Sf as necessary. Signal processing is performed.
[0053]
Then, at the timing when the processed odd-numbered pixel data Sj is obtained from the post-processing unit 40 of the signal processing LSI 11, the switching circuit 50 is switched to the signal processing LSI 11 side, and the odd-numbered pixel data Sj is extracted from the switching circuit 50. At the timing when the processed even pixel data Sk is obtained from the subsequent processing unit 40 of the processing LSI 12, the switching circuit 50 is switched to the signal processing LSI 12 side, and the even pixel data Sk is extracted from the switching circuit 50.
[0054]
That is, the switching circuit 50 combines the odd-numbered pixel data Sj output from the signal processing LSI 11 and the even-numbered pixel data Sk output from the signal processing LSI 12, and the switching circuit 50 generates high-resolution output image data So after signal processing. can get.
[0055]
As described above, the signal processing apparatus in the example of FIG. 3 can be used for high resolution, and unlike the signal processing apparatus shown in FIG. 10, the pixel selection unit 31 of the signal processing LSIs 11 and 12 has an odd number. Prior to the division into the pixel data Se and the even-numbered pixel data Sf, the signal processing LSIs 11 and 12 can perform the signal processing (1) described above.
[0056]
Furthermore, the pixel selection unit 31, the pixel selection signal generation unit 32, and the switching circuit 50 of the signal processing LSIs 11 and 12 can be configured by simple switches, gates, or counters, and the signal processing apparatus shown in FIG. Unlike the processing unit 91 and the synthesis processing unit 95, since no line memory is required, according to the present invention, the circuit scale and cost of the signal processing device can be reduced.
[0057]
In this regard, when the signal processing device of FIG. 11 is used for low resolution and high resolution (hereinafter referred to as the old method), the signal processing device (signal processing LSI 10) of the example of FIG. Compared with the case where the signal processing apparatus of the example of FIG. 3 is used for high resolution (hereinafter referred to as a new method).
[0058]
For low resolution, the circuit scale for the signal processing of (1) is 1, and for the high resolution, the circuit scale for the signal processing of (1) is 2. The circuit scale for the signal processing is 2 and the circuit scale for the signal processing of (2) is 4.
[0059]
In the signal processing apparatus of FIG. 11, since the signal processing LSIs 70A and 70B are for low resolution and perform the signal processing of (1) and (2), the circuit scale of the signal processing LSIs 70A and 70B is as follows. 2 × (1 + 2) = 6. When the circuit scale of the division processing unit 91 is A and the circuit scale of the synthesis processing unit 95 is B, the circuit scale of the entire signal processing apparatus is (6 + A + B). When this signal processing apparatus is used for low resolution and high resolution, the circuit scale for low resolution and high resolution is 2 (6 + A + B) = 12 + 2A + 2B.
[0060]
On the other hand, in the signal processing apparatus (signal processing LSI 10) in the example of FIG. 1, the pre-processing unit 20 is compatible with high resolution and performs the signal processing of (1), so the circuit scale of the pre-processing unit 20 is high. Since the post-processing unit 40 is compatible with low resolution and performs the signal processing of (2) above, the circuit scale of the post-processing unit 40 is 2, and the pixel selection unit 31 and the pixel selection signal generation unit 32 are connected. When the combined circuit scale is X, the circuit scale of the entire signal processing device (signal processing LSI 10) is (4 + X).
[0061]
3 is provided with two signal processing devices (signal processing LSIs 10) of the example of FIG. 1 and a switching circuit 50 added thereto. Therefore, the circuit scale of the switching circuit 50 is represented by Y. Then, the circuit scale of the entire signal processing apparatus is 2 (4 + X) + Y = 8 + 2X + Y.
[0062]
Therefore, when the signal processing device (signal processing LSI 10) of the example of FIG. 1 is used for low resolution and the signal processing device of the example of FIG. 3 is used for high resolution, the low resolution and high resolution are combined. The circuit scale is (4 + X) + (8 + 2X + Y) = 12 + 3X + Y.
[0063]
Since X and Y are sufficiently smaller than A and B as described above, (2A + 2B)> (3X + Y), and the circuit scale for low resolution and high resolution in the new method is The circuit scale is smaller than the combination of the low resolution and the high resolution for the method.
[0064]
When the circuit scale of the pre-processing unit 20 is smaller than the circuit scale of the post-processing unit 40 as in the example of FIG. 2, the circuit scale combining the low resolution and the high resolution for the new method is small. Therefore, the effect of reducing the circuit scale and the cost in the case of the present invention becomes larger than the above (12 + 3X + Y).
[0065]
The example of FIG. 3 is a case where the processing capability of the post-processing unit 40 is ½ of the processing capability of the pre-processing unit 20, but the processing capability of the post-processing unit 40 is ¼ of the processing capability of the pre-processing unit 20. , 1/6, 1/8, etc., the present invention can also be applied.
[0066]
FIG. 6 shows an example in which high-resolution image data is divided into four parts by two in the horizontal direction and in the vertical direction.
[0067]
In this example, four signal processing LSIs 10 as shown in FIG. 1 or FIG. 2 are provided in parallel with respect to input image data as shown as signal processing LSIs 11 to 14, and are provided on the output side of the signal processing LSIs 11 to 14. The switching circuit 50 is provided, and the pixel selection unit 31 of the signal processing LSI 11 extracts the data of the odd pixels of the odd lines (odd number lines). The pixel selection unit 31 of the signal processing LSI 12 extracts the even pixels of the odd lines. The data is extracted, the pixel selection unit 31 of the signal processing LSI 13 extracts the data of the odd pixels of the even lines (even number lines), and the pixel selection unit 31 of the signal processing LSI 14 stores the data of the even pixels of the even lines. The signal processor is controlled to be extracted.
[0068]
Specifically, in the pre-processing unit 20 of the signal processing LSIs 11 to 14, the high resolution input image data Si as schematically shown in FIG. Signal processing is performed.
[0069]
Then, the pixel selection unit 31 of the signal processing LSI 11 is schematically shown in FIG. 7B from the output image data Sa of the previous stage processing unit 20 of the signal processing LSI 11 by the pixel selection signal from the pixel selection signal generation unit 32. Such odd-numbered pixel data Se of the odd-numbered line is extracted, and the signal processing LSI 11 performs the signal processing (2) on the data Se as necessary.
[0070]
In parallel with this, the pixel selection unit 31 of the signal processing LSI 12 uses the pixel selection signal from the pixel selection signal generation unit 32 to output the output image data Sb of the pre-processing unit 20 of the signal processing LSI 12 to FIG. Data Sf of even pixels of odd lines as schematically shown is extracted, and the signal processing LSI 12 performs the signal processing (2) on the data Sf as necessary in the subsequent processing unit 40. .
[0071]
In parallel with this, the pixel selection unit 31 of the signal processing LSI 13 uses the pixel selection signal from the pixel selection signal generation unit 32 to output the output image data Sc of the pre-processing unit 20 of the signal processing LSI 13 to FIG. 7D. The odd-numbered pixel odd-numbered pixel data Sg as shown schematically is extracted, and the signal processing LSI 13 performs the signal processing (2) on the data Sg as necessary. .
[0072]
In parallel with this, the pixel selection unit 31 of the signal processing LSI 14 uses the pixel selection signal from the pixel selection signal generation unit 32 to output the output image data Sd of the previous processing unit 20 of the signal processing LSI 14 to FIG. The even-numbered pixel data Sh of the even-numbered lines as schematically shown is extracted, and the signal processing LSI 14 performs the signal processing (2) as necessary on the data Sh in the post-processing unit 40 of the signal processing LSI 14. .
[0073]
Then, the switching circuit 50 combines the processed data Sj, Sk, Sl, and Sm of the output of the post-processing unit 40 of the signal processing LSIs 11 to 14, and outputs a high-resolution output image after the signal processing from the switching circuit 50. Data So is obtained.
[0074]
The signal processing apparatus as in the example of FIG. 3 or FIG. 6 can also be used for low resolution. For example, in a device that supports both high resolution and low resolution, it is preferable to incorporate a signal processing apparatus such as the example of FIG. 3 or FIG.
[0075]
In this case, when used for high resolution, the signal processing apparatus is controlled as described above, and when used for low resolution, one signal processing LSI 11 is used as a signal as shown in FIG. 1 or FIG. It operates in the same manner as the processing LSI 10 and controls the signal processing apparatus so that the output image data of the signal processing LSI 11 is extracted through the switching circuit 50 as low-resolution output image data after signal processing.
[0076]
The example of FIGS. 3 and 6 is a case where the signal processing device unit including the pre-processing unit 20, the pixel selecting unit 31, the pixel selection signal generating unit 32, and the post-processing unit 40 is configured as a signal processing LSI. The entire signal processing device including the plurality of signal processing device units and the switching circuit 50 may be configured in a one-chip LSI.
[0077]
【The invention's effect】
As described above, according to the present invention, it is possible to perform signal processing that requires peripheral pixel data in order to obtain processed data of the pixel of interest, and to reduce the circuit scale and cost of the signal processing device. be able to.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a signal processing apparatus according to the present invention.
FIG. 2 is a diagram illustrating an example of a signal processing apparatus according to the present invention.
FIG. 3 is a diagram showing an example of a signal processing apparatus according to the present invention.
4 is a diagram for explaining the signal processing apparatus of FIG. 3;
FIG. 5 is a diagram for explaining the signal processing apparatus of FIG. 3;
FIG. 6 is a diagram illustrating an example of a signal processing apparatus according to the present invention.
7 is a diagram for explaining the signal processing apparatus of FIG. 6;
FIG. 8 is a diagram showing a conventional high-resolution signal processing apparatus.
FIG. 9 is a diagram illustrating a conventional signal processing apparatus for low resolution.
FIG. 10 shows an example of a possible signal processing device.
FIG. 11 shows an example of a possible signal processing device.
[Explanation of symbols]
Since all the main parts are described in the figure, they are omitted here.

Claims (7)

A pre-processing unit capable of performing a first type of signal processing that requires data of peripheral pixels to obtain data after processing of a target pixel with respect to input image data;
A pixel selection unit capable of selectively extracting part of the pixel data in the output image data of the pre-stage processing unit;
A post-stage processing unit capable of performing the second type of signal processing that does not require the data of the peripheral pixels to obtain the processed data of the target pixel for the output image data of the pixel selection unit;
A signal processing apparatus comprising: The signal processing apparatus according to claim 1, configured as a semiconductor integrated circuit. A plurality of signal processing devices according to claim 1 or 2 as signal processing device sections, respectively, are provided in parallel with respect to input image data,
In the pixel selection unit of each signal processing unit, a part of the pixel data in the output image data of the pre-processing unit is periodically extracted in a complementary manner,
A signal processing device in which output image data of the subsequent processing unit of each signal processing device unit is combined by switching and is taken out as output image data after signal processing. A plurality of signal processing devices according to claim 1 or 2 as signal processing device sections, respectively, are provided in parallel with respect to input image data,
When the input image data is relatively low resolution image data, the pixel selection unit of any of the signal processing units extracts all the pixel data from the output image data of the pre-processing unit, The output image data of the subsequent processing unit of the signal processing device unit is extracted as output image data after signal processing,
When the input image data is relatively high-resolution image data, in the pixel selection unit of each signal processing device unit, a part of the pixel data in the output image data of the pre-processing unit is complementary to each other. A signal processing device that is periodically extracted and output image data of the subsequent processing unit of each signal processing device unit is switched and combined to be extracted as output image data after signal processing. An image display device comprising the signal processing device according to claim 1. A plurality of signal processing devices according to claim 1 or 2 are provided in parallel as input signal data respectively as signal processing device units,
In the pixel selection unit of each signal processing unit, a part of the pixel data in the output image data of the pre-processing unit is periodically extracted in a complementary manner,
A signal processing method for switching and synthesizing output image data of the subsequent processing unit of each signal processing device unit and extracting it as output image data after signal processing. A plurality of signal processing devices according to claim 1 or 2 are provided in parallel as input signal data respectively as signal processing device units,
When the input image data is relatively low resolution image data, the pixel selection unit of any one of the signal processing units extracts all the pixel data from the output image data of the preceding processing unit, The output image data of the subsequent processing unit of the signal processing device unit is extracted as output image data after signal processing,
When the input image data is relatively high-resolution image data, a part of the pixel data in the output image data of the pre-processing unit is complementarily complemented by the pixel selection unit of each signal processing unit. A signal processing method for periodically extracting, switching and synthesizing output image data of the subsequent processing unit of each signal processing device unit, and extracting it as output image data after signal processing.

Images