JP2005005757A - Synchronizing circuit and semiconductor chip employing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronizing circuit for quickly alleviating a power supply voltage drop caused in a power supply by using capacitors each with a comparatively small capacitance, and to provide a semiconductor chip employing the same. <P>SOLUTION: The synchronizing circuit is provided with the capacitors C1, C2 and transmission gates S1 to S3. Since the transmission gates S1, S2 are in a conductive state and the transmission gate S3 is in a cut-off state when a clock signal CLK 2 is at an L level, the capacitors C1, C2 respectively store electric charges VDD 1×C<SB>C1</SB>, VDD 1×C<SB>C2</SB>. Then when the clock signal CLK 2 changes to an H level, since the transmission gates S1, S2 are in a cut-off state and the transmission gate S3 is in a conductive state, the electric charges stored in the capacitors C1, C2 are both decreased to VDD 1×C<SB>C1</SB>×C<SB>C2</SB>/(C<SB>C1</SB>+C<SB>C2</SB>). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous circuit and a semiconductor chip using the same, and more particularly, to a technique for mitigating periodically generated power supply noise.
[0002]
[Prior art]
In the synchronous circuit, most of the circuits operate simultaneously in synchronization with the clock signal input. Therefore, a current that periodically exceeds the power supply capability flows, and a spike-like voltage drop occurs in the power supply voltage. For this reason, the voltage supplied to the circuit decreases, and the circuit performance temporarily deteriorates. In the conventional synchronous circuit, a decoupling capacitance is provided between the power supply node and the GND node, and a charge is supplied to the power supply node when the voltage drops. Examples of a synchronization circuit using a decoupling capacitor are disclosed in Patent Documents 1 and 2, for example.
[0003]
[Patent Document 1]
JP 2001-168223 A
[Patent Document 2]
Japanese Patent Laid-Open No. 2001-14848
[0004]
[Problems to be solved by the invention]
In the synchronous circuits disclosed in Patent Documents 1 and 2, the voltage applied to the decoupling capacitor when charging is smaller than the power supply voltage supplied to the circuit. Therefore, there is a problem that a relatively large capacity is required to accumulate a predetermined amount of charge. In addition, the synchronous circuit disclosed in Patent Document 1 has a problem in that a time difference occurs between the power supply voltage drop and the charge supply because the charge discharge occurs passively depending only on the voltage drop amount. It was.
[0005]
The present invention has been made to solve the above problems, and a synchronous circuit for quickly mitigating a power supply voltage drop generated in a power supply by using a relatively small capacity and a semiconductor chip using the same The purpose is to provide.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a synchronization circuit according to a first aspect of the present invention includes a processing circuit that performs predetermined processing based on a first clock signal having a predetermined period, and a predetermined size for the processing circuit. A first power supply line for supplying the first power supply voltage, a first capacitor with one pole connected to the first power supply line, one end connected to the other pole of the first capacitor and the other end A first switch element connected to a ground line; a second capacitor having one pole connected to the ground line; one end connected to the other pole of the second capacitor and the other end connected to the first power line and the first A second switch element connected to one pole of one capacitor, one end connected to the other pole of the first capacitor and one end of the first switch element, and the other end connected to the other pole of the second capacitor and the first A third switch element connected to one end of the two switch elements, the first to third switch elements, It operates based on a second clock signal having a constant period.
[0007]
According to a second aspect of the present invention, there is provided a synchronizing circuit, a processing circuit for performing predetermined processing based on a first clock signal having a predetermined cycle, and supplying a first power supply voltage having a predetermined magnitude to the processing circuit. A first power line, a first capacitor having one pole connected to the first power line, one end connected to the other pole of the first capacitor, and the other end connected to a ground line. One switch element, a second capacitor having one pole connected to a ground line, a second power supply line for supplying a second power supply voltage of a predetermined magnitude to the second capacitor, and one end of the second capacitor A second switch element connected to the other pole of the capacitor and having the other end connected to the second power supply line, and one end connected to the other pole of the first capacitor and one end of the first switch element. A third switch element connected to the other electrode of the second capacitor and one end of the second switch element; First through third switching element operates based on a second clock signal having a predetermined period.
[0008]
According to a third aspect of the present invention, there is provided a synchronizing circuit comprising: a processing circuit that performs a predetermined process based on a first clock signal having a predetermined clock period; and a first power supply voltage having a predetermined magnitude applied to the processing circuit. A first power supply line for supplying, a third power supply line for supplying a third power supply voltage greater than the first power supply voltage, a resistance element having one end connected to the first power supply line, A fourth switch element having one end connected to the other end of the resistance element and the other end connected to the third power supply line. The fourth switch element is based on a second clock signal having a predetermined period. Operate.
[0009]
According to a fourth aspect of the present invention, there is provided a synchronizing circuit comprising: a processing circuit that performs a predetermined process based on a first clock signal having a predetermined clock period; and a first power supply voltage having a predetermined magnitude applied to the processing circuit. A first power supply line for supplying; a third power supply line for supplying a third power supply voltage greater than the first power supply voltage; and a fifth switch element having one end connected to the first power supply line A sixth switch element having one end connected to the other end of the fifth switch element and the other end connected to the third power line, and one pole connected to a ground line and the other pole connected to the fifth switch element. And a third capacitor connected to one end of the sixth switch element, and the fifth to sixth switch elements operate based on a second clock signal having a predetermined period.
[0010]
According to a fifth aspect of the present invention, there is provided a synchronization circuit comprising: a processing circuit that performs a predetermined process based on a first clock signal having a predetermined clock period; and a first power supply voltage having a predetermined magnitude applied to the processing circuit. A first power line for supplying; a fourth capacitor having one pole connected to the first power line; an inverter having an output connected to the other pole of the fourth capacitor; and driving the inverter And a second clock signal having a predetermined cycle is applied to the input of the inverter.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
<Embodiment 1>
FIG. 1 shows a configuration of a synchronization circuit according to Embodiment 1 of the present invention. In this configuration, charge is supplied to the processing circuit 200 between the power supply line 1 (first power supply line) and the ground line of the processing circuit 200 of the synchronous circuit in a period (transition period) in which the charge is insufficient in the processing circuit 200. In the processing circuit 200, the relaxation circuit 100 that charges the charge from the processing circuit 200 is provided in a period (holding period) in which the charge is not insufficient. Here, the transition period is a period during which most of the processing circuit 200 operates in synchronization with the edge of the clock signal CLK1, and the holding period is a period other than the transition period. Hereinafter, this configuration will be described in detail.
[0012]
As shown in FIG. 1, the power supply line 1 is connected to the processing circuit 200 and supplies the processing circuit 200 with a power supply voltage VDD1 (first power supply voltage) having a predetermined magnitude. The processing circuit 200 is for performing predetermined processing based on a clock signal CLK1 (first clock signal) having a predetermined cycle. One pole of the capacitor C1 (first capacitor) is connected to the power line 1. The other pole of the capacitor C1 is connected to the drain of the transmission gate S1 at the contact N1. The source of the transmission gate S1 is connected to the ground line.
[0013]
The capacitor C2 (second capacitor) has one pole connected to the ground line and the other pole connected to the source of the transmission gate S2 at the contact N2. The drain of the transmission gate S2 is connected to the power line 1 and one pole of the capacitor C1 at the contact N3.
[0014]
The transmission gate S3 has a drain connected to the contact N1 and a source connected to the contact N2.
[0015]
In the transmission gates S1 and S2, a clock signal CLK2 (second clock signal) is input to the PMOS gate, and an inverted signal of the clock signal CLK2 is input to the NMOS gate. Further, in the transmission gate S3, the clock signal CLK2 is input to the NMOS gate, and the inverted signal of the clock signal CLK2 is input to the PMOS gate. That is, the transmission gates S1 to S3 function as first to third switch elements, respectively.
[0016]
Capacitances C1 and C2 are respectively capacitance values C _C1 , C _C2 It shall have.
[0017]
Next, the operation of the synchronization circuit shown in FIG. 1 will be described.
[0018]
First, FIG. 2A shows the clock signal CLK1 input to the processing circuit 200. FIG. FIG. 2B shows an example of a spike-like voltage drop of the power supply voltage VDD1 generated in synchronization with the clock signal CLK1. In FIG. 2B, a voltage drop occurs in synchronization with both rising and falling edges of the clock signal CLK1. As will be described below, when the clock signal CLK2 having a half period of the clock signal CLK1 as shown in FIG. 2C is input to the switch elements S1 to S3, the capacitors C1 and C2 have this voltage. It operates to supply charges to the power supply voltage VDD1 at a timing corresponding to the drop.
[0019]
First, the case where the processing circuit 200 is in the holding period, that is, the case where the clock signal CLK2 is at the L level will be described. At this time, the transmission gates S1 and S2 are turned on and the transmission gate S3 is cut off, so that the potential at the contact N1 is 0 and the potentials at the contacts N2 and N3 are VDD1. Therefore, since the potential difference value between the two electrodes of the capacitors C1 and C2 is both VDD1, the charges VDD1 × C _C1 , VDD1 × C _C2 Is stored separately. That is, the capacitors C1 and C2 are charged by the power supply voltage VDD1.
[0020]
Next, a case where the processing circuit 200 changes from this state during the transition period, that is, the clock signal CLK2 changes to the H level will be described. At this time, since the transmission gates S1 and S2 are cut off and the transmission gate S3 is in a conductive state, the potential of the contact N3 remains VDD1, but the potential of the contacts N1 and N2 is VDD1 × C. _C1 / (C _C1 + C _C2 ) Accordingly, the potential difference value between the electrodes of the capacitors C1 and C2 is VDD1 × C, respectively. _C2 / (C _C1 + C _C2 ), VDD1 × C _C1 / (C _C1 + C _C2 ), The charges stored in the capacitors C1 and C2 are both VDD1 × C _C1 × C _C2 / (C _C1 + C _C2 ). That is, the reduced amount of charge stored in the capacitors C1 and C2 is supplied to the power supply voltage VDD1.
[0021]
In the change from the L level to the H level of the clock signal CLK2, the potential of the contact N3 immediately after the change is 2VDD1, but the potential of the contact N3 decreases and settles to VDD1 as the charge moves. In other words, in this synchronous circuit, by applying a voltage higher than the power supply voltage VDD1 to the power supply voltage VDD1, charges are supplied to the power supply voltage VDD1.
[0022]
As described above, in this synchronous circuit, charging and discharging of the charges of the capacitors C1 and C2 are repeated corresponding to the transition period and the holding period of the processing circuit 200. Thereby, the voltage drop as shown in FIG. 2B can be reduced.
[0023]
FIG. 2D shows the power supply voltage VDD1 whose voltage drop is relaxed by the relaxation circuit 100. FIG. Although a voltage drop due to charging of the capacitors C1 and C2 occurs in synchronization with the falling edge of the clock signal CLK2, it occurs in synchronization with both rising and falling edges of the clock signal CLK1. The voltage drop is greatly mitigated.
[0024]
In a general synchronization circuit, the voltage drop is synchronized with both rising and falling edges of the clock signal CLK1, as shown in FIG. Here, when the voltage drop is synchronized only with the rising edge of the clock signal CLK1 as shown in FIG. 2E, the clock signal CLK1 is replaced with the clock signal CLK1 as shown in FIG. A clock signal CLK3 having the same period may be used. As the clock signal CLK3, the clock signal CLK1 may be used as it is.
[0025]
In FIGS. 2C and 2F, the clock signals CLK2 and CLK3 have the same phase as the clock signal CLK1, but for example, Δt as shown in FIGS. 2G and 2H. The phase may be advanced correspondingly. In this case, by adjusting the value of Δt, the amount of charge supplied from the capacitors C1 and C2 to the power supply voltage VDD1 at the moment when most of the processing circuit 200 starts to operate can be maximized.
[0026]
Thus, in the synchronous circuit according to the present embodiment, charges are actively supplied using a voltage equal to or higher than the power supply voltage VDD1 in accordance with the timing at which the processing circuit 200 consumes charges. Therefore, the voltage drop of the power supply voltage VDD1 during the transition period can be quickly alleviated using a relatively small capacity. Therefore, it is possible to suppress a decrease in the operation speed of the processing circuit 200 accompanying the above.
[0027]
In addition, since the synchronous circuit and the charge supply circuit coexist on one die, the influence of the parasitic resistance and inductance of the assembly wires and leads on the charge supply source can be reduced.
[0028]
In FIG. 1, two capacitors C1 and C2 are connected so as to be in series when power is supplied. However, the number of capacitors is not limited to two and may be three or more. FIG. 3 shows a configuration of a relaxation circuit 110 in which a capacitor C5 and transmission gates S7 to S9 are added to the relaxation circuit 100 shown in FIG.
[0029]
<Embodiment 2>
FIG. 4 shows the configuration of the synchronization circuit according to the second embodiment of the present invention. This configuration is characterized in that, in the first embodiment, the capacitor C1 and the capacitor C2 are connected to different power supply lines 1 and 2 (second power supply lines), respectively. Hereinafter, this configuration will be described in detail.
[0030]
The mitigation circuit 120 of FIG. 4 is the same as the mitigation circuit 100 of FIG. 1 according to the first embodiment, except that the power supply line 2 is connected to the drain of the transmission gate S2 instead of the power supply line 1, and A large power supply voltage VDD2 (second power supply voltage) is supplied. Here, it is assumed that the power supply voltage VDD2 is less loaded by the processing circuit 200 than the power supply voltage VDD1. 4, elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted here.
[0031]
In the synchronous circuit of FIG. 4, the power supply voltage VDD2 having a relatively large supply capacity charges the capacitor C2, so that the load of the power supply voltage VDD1 can be reduced correspondingly. Further, when VDD2> VDD1, more charges can be supplied compared to the synchronous circuit of FIG.
[0032]
As described above, in the synchronous circuit according to the present embodiment, in addition to the effect of the first embodiment, the load of the power supply voltage VDD1 can be reduced correspondingly, and more when VDD2> VDD1. This has the effect of being able to supply the electric charge.
[0033]
<Embodiment 3>
FIG. 5 shows the configuration of the synchronization circuit according to the third embodiment of the present invention. In this configuration, in the synchronous circuit having two power supply lines, the relaxation circuit 130 that supplies charges from the power supply line having the higher potential to the power supply line having the lower potential is provided in the transition period of the processing circuit 200. Features. Hereinafter, this configuration will be described in detail.
[0034]
In relaxation circuit 130, resistance element R1 has one end connected to power supply line 1 and the other end connected to the source of transmission gate S4. The drain of the transmission gate S4 is connected to the power supply line 3 (third power supply line). Here, the power supply line 3 is for supplying a power supply voltage VDDH (third power supply voltage) higher than the power supply voltage VDD1. In FIG. 5, elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted here.
[0035]
In the transmission gate S4, the clock signal CLK2 is input to the NMOS gate, and the inverted signal of the clock signal CLK2 is input to the PMOS gate via the inverter I1. That is, the transmission gate S4 functions as a fourth switch element.
[0036]
Next, the operation of the synchronization circuit shown in FIG. 5 will be described.
[0037]
First, the case where the processing circuit 200 is in the transition period, that is, the case where the clock signal CLK2 is at the H level will be described. At this time, since the transmission gate S4 is in a conducting state, electric charge is supplied from the power supply voltage VDDH to the power supply voltage VDD1 via the resistance element R1 for voltage drop. Thereby, when there is a margin in the supply capability of the power supply voltage VDDH having a high potential, a voltage drop of the power supply voltage VDD1 having a low potential can be suppressed.
[0038]
Next, the case where the processing circuit 200 changes from this state to the holding period, that is, the clock signal CLK2 changes to the L level will be described. At this time, the transmission gate S4 is cut off. Here, as the voltage value input to the PMOS gate of the transmission gate S4, a complete cutoff state can be created by using the power supply voltage VDDH having the larger voltage value.
[0039]
As described above, the synchronous circuit according to the present embodiment has an effect that the voltage drop of the low-potential power supply voltage VDD1 can be suppressed when the supply capability of the high-potential power supply voltage VDDH is sufficient.
[0040]
<Embodiment 4>
FIG. 6 shows a configuration of a synchronization circuit according to Embodiment 4 of the present invention.
[0041]
The relaxation circuit 140 of FIG. 6 is obtained by adding a pulse generation circuit P1 to the relaxation circuit 130 of FIG. 5 according to the third embodiment. The pulse generation circuit P1 converts the pulse width of the input clock signal CLK2 and outputs it to the transmission gate S4. 6, elements similar to those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0042]
In the pulse generation circuit P1, the supply amount of charges can be adjusted by changing and outputting the pulse width of the clock signal CLK2. As a result, the rise of the power supply voltage VDD1 can be controlled, so that a margin can be given to the withstand voltage of the circuit element to be used. Also, noise propagation due to the connection of the two power supply lines can be minimized.
[0043]
As described above, in the synchronous circuit according to the present embodiment, since the pulse generation circuit P1 adjusts the supply amount of electric charge, it is possible to control the rise of the power supply voltage VDD1, and to give a margin to the withstand voltage of the circuit elements to be used. It has the effect of being able to. Further, there is an effect that noise propagation due to the connection of the two power supply lines can be minimized.
[0044]
Further, not only the mitigation circuit 130 of FIG. 5 according to the third embodiment, but also mitigation circuits according to other embodiments have the same effect by changing the pulse width of the clock signal CLK2.
[0045]
<Embodiment 5>
FIG. 7 shows a configuration of a synchronization circuit according to the fifth embodiment of the present invention. In this configuration, in a synchronous circuit having two power supply lines, the charge charged from the power supply line having the higher potential during the holding period of the processing circuit 200 is supplied to the power supply line having the lower potential during the transition period of the processing circuit 200. The relaxation circuit 150 is provided. Hereinafter, this configuration will be described in detail.
[0046]
In the relaxation circuit 150, the transmission gate S5 has a source connected to the power supply line 1. Transmission gate S6 has a source connected to the drain of transmission gate S5 at contact N4 and a drain connected to power supply line 3. The capacitor C3 (third capacitor) has one pole connected to the ground line and the other pole connected to the contact N4. 7, elements similar to those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted here.
[0047]
In the transmission gate S5, the clock signal CLK2 is input to the NMOS gate, and the inverted signal of the clock signal CLK2 is input to the PMOS gate. Further, in the transmission gate S6, the clock signal CLK2 is input to the PMOS gate, and the inverted signal of the clock signal CLK2 is input to the NMOS gate. That is, the transmission gates S5 and S6 function as fifth to sixth switch elements, respectively.
[0048]
The capacitance C3 is a capacitance value C _C3 It shall have.
[0049]
Next, the operation of the synchronization circuit shown in FIG. 7 will be described.
[0050]
First, the case where the processing circuit 200 is in the holding period, that is, the case where the clock signal CLK2 is at the L level will be described. At this time, the transmission gate S5 is cut off and the transmission gate S6 is turned on, so that the potential of the contact N4, that is, the potential difference between both electrodes of the capacitor C3 becomes VDDH, and the charge VDDH × C _C3 Is saved. That is, the capacitor C3 is charged by the power supply voltage VDDH.
[0051]
Next, a case where the processing circuit 200 changes from this state during the transition period, that is, the clock signal CLK2 changes to the H level will be described. At this time, the transmission gate S5 is turned on and the transmission gate S6 is turned off, so that the potential difference at the contact N4, that is, the potential difference across the capacitor C3 is reduced to VDD1, so VDD1) x C _C3 To decrease. That is, the reduced amount of charge stored in the capacitor C3 is supplied to the power supply voltage VDD1.
[0052]
In the change from the L level to the H level of the clock signal CLK2, the potential of the contact N4 immediately after the change is VDDH. However, the potential of the contact N4 decreases and settles to VDD1 as the charge moves. That is, in this synchronous circuit, a charge higher than the power supply voltage VDD1 is applied to the power supply voltage VDD1 to supply charges to the power supply voltage VDD1.
[0053]
As described above, in this synchronous circuit, charging and discharging of the capacitor C3 are repeated in accordance with the transition period and the holding period of the processing circuit 200. Thereby, the voltage drop as shown in FIG. 2B can be reduced.
[0054]
In this synchronous circuit, since the two power supply lines are completely cut off as in the second embodiment, noise propagation due to the connection of the two power supply lines is suppressed as compared with the third and fourth embodiments. Can be minimized. In addition, since the timing of supplying the charge to the power supply voltage VDD1 and the timing of charging the charge from the power supply voltage VDDH are deviated, the potential of the power supply voltage VDDH is prevented from being lowered during the transition period of the processing circuit 200. Can do. Furthermore, the circuit configuration can be simplified as compared with relaxation circuits 100 and 120 in the first and second embodiments.
[0055]
Thus, in the synchronous circuit according to the present embodiment, since the two power supply lines are completely cut off, in addition to the effects of the third and fourth embodiments, noise propagation can be minimized. In addition, the power supply voltage VDDH can be prevented from being lowered during the transition period of the processing circuit 200. In addition, the circuit configuration can be simplified.
[0056]
<Embodiment 6>
FIG. 8 shows the configuration of the synchronization circuit according to the sixth embodiment of the present invention. This configuration is characterized in that, in a synchronous circuit having two power supply lines, a power supply voltage VDD1 and an inverter I2 operated by the power supply voltage VDD2 are attached to a capacitor C4 (fourth capacitor). Hereinafter, this configuration will be described in detail.
[0057]
In the relaxation circuit 160, the capacitor C4 has one pole connected to the power supply line 1. The drain of the P-type transistor PMOS is connected to the power supply line 2 for supplying the power supply voltage VDD2 having a predetermined magnitude to the capacitor C4. The source of the PMOS is connected to the other pole of the capacitor C4 at the contact N5. The N-type transistor NMOS has a drain connected to the contact N5 and a source connected to the ground line. 8, elements similar to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted here.
[0058]
A clock signal CLK2 is input to the PMOS gate, and an inverted signal of the clock signal CLK2 is input to the NMOS gate.
[0059]
The capacitance C4 is an electrostatic capacitance value C _C4 It shall have.
[0060]
Next, the operation of the synchronization circuit shown in FIG. 8 will be described.
[0061]
First, the case where the processing circuit 200 is in the holding period, that is, the case where the clock signal CLK2 is at the L level will be described. At this time, the PMOS is cut off and the NMOS is turned on, so that the potential of the contact N5 becomes zero. Accordingly, since the potential difference value between the two electrodes of the capacitor C4 is VDD1, the charge VDD1 × C is stored in the capacitor C4. _C4 Is saved. That is, the capacitor C4 is charged by the power supply VDD1.
[0062]
Next, the case where the processing circuit is in the transition period from this state, that is, the case where the clock signal CLK2 changes to H level will be described. At this time, the PMOS is turned on and the NMOS is turned off, so that the potential of the contact N5 is VDD2.
[0063]
Here, if VDD1> VDD2, the potential difference value between the two electrodes of the capacitor C4 decreases to (VDD1-VDD2), so the charge stored in the capacitor C4 is also (VDD2-VDD1) × C. _C4 To decrease. That is, the reduced amount of charge stored in the capacitor C4 is supplied to the power supply voltage VDD1.
[0064]
When the clock signal CLK2 changes from the L level to the H level, the potential of the contact N5 immediately after the change is VDD1, but the potential of the contact N5 decreases and settles to VDD2 as the charge moves.
[0065]
When VDD2> VDD1, the amount of charge to be charged / discharged is increased, so that more charge is supplied. That is, in the case of VDD2> VDD1, in this synchronous circuit, a voltage higher than the power supply voltage VDD1 is applied to the power supply voltage VDD1, thereby supplying a charge to the power supply voltage VDD1.
[0066]
As described above, in this synchronous circuit, charging and discharging of the charge of the capacitor C4 are repeated in accordance with the transition period and the holding period of the processing circuit 200. Thereby, the voltage drop as shown in FIG. 2B can be reduced.
[0067]
In the relaxation circuit 120 of FIG. 4 according to the second embodiment, the potential of the contact N1 is raised by charging the capacitor C2 using the power supply voltage VDD2. However, in the relaxation circuit 160 of FIG. The power supply voltage VDD2 is applied to the contact N5 as it is. Therefore, more charge can be supplied to the power supply voltage VDD1.
[0068]
As described above, the synchronous circuit according to the present embodiment has an effect that more charges can be supplied in addition to the effect of the second embodiment.
[0069]
<Embodiment 7>
FIG. 9 shows the configuration of the synchronization circuit according to the seventh embodiment of the present invention. In this configuration, a mitigation circuit (here, the mitigation circuit 100 is shown) included in the synchronization circuit shown in the first to sixth embodiments is installed for each processing circuit 200 and supplied to the processing circuit 200. A clock signal whose phase is slightly advanced from the clock signal is input to the relaxation circuit 100.
[0070]
In FIG. 9, clock signals CLKa to CLKc are input to the relaxation circuit 100 and the buffer B1, respectively. In the buffer B1, a delay amount Δt is given. The clock signals CLKa to CLKc given the delay amount Δt are output from the buffer B1 as clock signals CLKb to CLKd, respectively, and input to the processing circuit 200. That is, the clock signals CLKa to CLKc input to the buffer B1 have the same period as the clock signals CLKb to CLKd output from the buffer B1, and have a phase advanced by an amount corresponding to the delay amount Δt. That is, the clock signals CLKa to CLKc input to the buffer B1 correspond to the clock signal CLK2 in FIG. 1 and the like, and the clock signals CLKb to CLKd output from the buffer B1 correspond to the clock signal CLK1 in FIG. Yes. Thus, as described above in the first embodiment, by adjusting the delay amount Δt, the amount of charge supplied from the capacitor to the power supply voltage VDD1 is maximized at the moment when most of the processing circuit 200 starts to operate. be able to. The charge supplied to the power supply voltage VDD1 is supplied to the processing circuit 200.
[0071]
As described above, in the synchronous circuit according to the seventh embodiment of the present invention, the buffer signal B1 having the delay amount Δt is used as a relaxation circuit for the clock signal whose phase is slightly advanced from the clock signal supplied to the processing circuit 200. Let them enter. Therefore, at the moment when most of the processing circuit 200 starts to operate, the amount of charge supplied from the capacitor to the power supply voltage VDD1 can be maximized.
[0072]
<Eighth embodiment>
10 to 13 show a configuration of a semiconductor chip according to the eighth embodiment of the present invention. In this configuration, the relaxation circuit shown in the first to seventh embodiments is mounted in a space with a margin on the semiconductor chip.
[0073]
As shown in FIGS. 10 to 12, a semiconductor chip 300 such as a microcomputer has a configuration in which an input / output unit 320 for inputting and outputting signals and power supplies is arranged outside a core unit 310 containing a processing circuit. In the input / output unit 320, the area of the corner cell 330 located in the four corner spaces and the area of the power cell 340 used for power input / output are only provided with the metal of the wiring. There is room in space. Therefore, an increase in the area of the semiconductor chip 300 can be suppressed by mounting a relaxation circuit below these regions as shown in FIGS. FIG. 12 is a diagram specifically explaining the mounting of the relaxation circuit in the corner cell 330 and the power cell 340.
[0074]
Further, as shown in FIG. 13, the area of the power supply trunk line 350 arranged in the core part 310 is also arranged with only the metal of the wiring, and there is a relatively large space in the lower part thereof. Therefore, as shown in FIG. 13, an increase in the area of the semiconductor chip can be suppressed by mounting a relaxation circuit below these regions.
[0075]
As described above, in the semiconductor chip according to the eighth embodiment, the synchronization circuit is arranged in a portion having a relatively large space on the semiconductor chip 300. Accordingly, it is possible to suppress a decrease in the operation speed of the processing circuit while suppressing an increase in the area of the semiconductor chip.
[0076]
【The invention's effect】
As described above, the synchronization circuit according to the first aspect of the present invention includes a processing circuit that performs predetermined processing based on a first clock signal having a predetermined period, and a processing circuit that has a predetermined size. A first power supply line for supplying one power supply voltage; a first capacitor having one pole connected to the first power supply line; one end connected to the other pole of the first capacitor and the other end grounded A first switch element connected to the second capacitor, one pole connected to the ground line, one end connected to the other pole of the second capacitor and the other end connected to the first power line and the first capacitor A second switch element connected to one pole of the second capacitor, one end connected to the other pole of the first capacitor and one end of the first switch element, and the other end to the other pole of the second capacitor and the second switch. A third switch element connected to one end of the element, wherein the first to third switch elements are predetermined Since operates based on a second clock signal having a period, the voltage drop of the first power supply voltage in the transition period can be alleviated rapidly with a relatively small capacity. Therefore, it is possible to suppress a decrease in the operation speed of the processing circuit. Further, since the synchronous circuit and the charge supply circuit coexist on one die, the influence of the parasitic resistance and inductance of the wire and lead of the assembly on the charge supply source can be reduced.
[0077]
According to a second aspect of the present invention, there is provided a synchronizing circuit, a processing circuit for performing predetermined processing based on a first clock signal having a predetermined cycle, and supplying a first power supply voltage having a predetermined magnitude to the processing circuit. A first power line, a first capacitor having one pole connected to the first power line, one end connected to the other pole of the first capacitor, and the other end connected to a ground line. One switch element, a second capacitor having one pole connected to a ground line, a second power supply line for supplying a second power supply voltage of a predetermined magnitude to the second capacitor, and one end of the second capacitor A second switch element connected to the other pole of the capacitor and having the other end connected to the second power supply line, and one end connected to the other pole of the first capacitor and one end of the first switch element. A third switch element connected to the other electrode of the second capacitor and one end of the second switch element; Since the first to third switching elements operate based on the second clock signal having a predetermined period, in addition to the effect of the synchronous circuit according to the first aspect, the load of the first power supply voltage is increased accordingly. In addition, when the second power supply voltage is higher than the first power supply voltage, more charge can be supplied.
[0078]
According to a third aspect of the present invention, there is provided a synchronizing circuit comprising: a processing circuit that performs a predetermined process based on a first clock signal having a predetermined clock period; and a first power supply voltage having a predetermined magnitude applied to the processing circuit. A first power supply line for supplying, a third power supply line for supplying a third power supply voltage greater than the first power supply voltage, a resistance element having one end connected to the first power supply line, A fourth switch element having one end connected to the other end of the resistance element and the other end connected to the third power supply line. The fourth switch element is based on a second clock signal having a predetermined period. Since it operates, when there is a margin in the supply capability of the third power supply voltage, the voltage drop of the first power supply voltage can be suppressed.
[0079]
According to a fourth aspect of the present invention, there is provided a synchronizing circuit comprising: a processing circuit that performs predetermined processing based on a first clock signal having a predetermined clock period; and a first power supply voltage having a predetermined magnitude applied to the processing circuit. A first power supply line for supplying; a third power supply line for supplying a third power supply voltage greater than the first power supply voltage; and a fifth switch element having one end connected to the first power supply line A sixth switch element having one end connected to the other end of the fifth switch element and the other end connected to the third power line, and one pole connected to a ground line and the other pole connected to the fifth switch element. A third capacitor connected to the other end of the sixth switch element and one end of the sixth switch element, and the fifth to sixth switch elements operate based on a second clock signal having a predetermined period. The power line is completely cut off. Therefore, in addition to the effect of the synchronous circuit according to the third aspect of the invention, it is possible to minimize the propagation of noise and to prevent the third power supply voltage from being lowered during the transition period of the processing circuit. I can roll. In addition, the circuit configuration can be simplified.
[0080]
According to a fifth aspect of the present invention, there is provided a synchronization circuit comprising: a processing circuit that performs a predetermined process based on a first clock signal having a predetermined clock period; and a first power supply voltage having a predetermined magnitude applied to the processing circuit. A first power line for supplying; a fourth capacitor having one pole connected to the first power line; an inverter having an output connected to the other pole of the fourth capacitor; and driving the inverter In addition to the effect of the synchronous circuit according to the invention of claim 2, the input of the inverter is supplied with a second clock signal having a predetermined period. This has the effect of being able to supply the electric charge.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a synchronization circuit according to a first embodiment.
FIG. 2 is a diagram showing an input signal of the synchronization circuit according to the first embodiment.
FIG. 3 is a circuit diagram showing a synchronization circuit according to the first embodiment.
FIG. 4 is a circuit diagram showing a synchronization circuit according to the second embodiment.
FIG. 5 is a circuit diagram showing a synchronization circuit according to a third embodiment.
FIG. 6 is a circuit diagram showing a synchronization circuit according to the fourth embodiment.
FIG. 7 is a circuit diagram showing a synchronization circuit according to a fifth embodiment.
FIG. 8 is a circuit diagram showing a synchronization circuit according to a sixth embodiment.
FIG. 9 is a circuit diagram showing a synchronization circuit according to a seventh embodiment.
FIG. 10 is a configuration diagram showing a semiconductor chip according to an eighth embodiment.
FIG. 11 is a configuration diagram showing a semiconductor chip according to an eighth embodiment.
FIG. 12 is a configuration diagram showing a semiconductor chip according to an eighth embodiment.
FIG. 13 is a configuration diagram showing a semiconductor chip according to an eighth embodiment.
[Explanation of symbols]
1-3 power line, 100-160 relaxation circuit, 200 processing circuit, 300 semiconductor chip, 310 core part, 320 input / output part, 330 corner cell, 340 power cell, 350 power trunk, B1 buffer, C1-C5 capacity, I1 ˜I2 inverter, N1 to N5 contacts, S1 to S9 transmission gate, VDD1 to VDD2, VDDH power supply voltage, R1 resistance element, P1 pulse generation circuit.

Claims (12)

A processing circuit for performing predetermined processing based on a first clock signal having a predetermined cycle;
A first power supply line for supplying a first power supply voltage of a predetermined magnitude to the processing circuit;
A first capacitor having one pole connected to the first power line;
A first switch element having one end connected to the other electrode of the first capacitor and the other end connected to a ground line;
A second capacitor with one pole connected to the ground wire;
A second switch element having one end connected to the other pole of the second capacitor and the other end connected to the first power line and one pole of the first capacitor;
A third switch element having one end connected to the other pole of the first capacitor and one end of the first switch element and the other end connected to the other pole of the second capacitor and one end of the second switch element; Prepared,
The first to third switch elements are synchronous circuits that operate based on a second clock signal having a predetermined period. A processing circuit for performing predetermined processing based on a first clock signal having a predetermined cycle;
A first power supply line for supplying a first power supply voltage of a predetermined magnitude to the processing circuit;
A first capacitor having one pole connected to the first power line;
A first switch element having one end connected to the other electrode of the first capacitor and the other end connected to a ground line;
A second capacitor with one pole connected to the ground wire;
A second power supply line for supplying a second power supply voltage of a predetermined magnitude to the second capacitor;
A second switch element having one end connected to the other electrode of the second capacitor and the other end connected to the second power line;
A third switch element having one end connected to the other pole of the first capacitor and one end of the first switch element and the other end connected to the other pole of the second capacitor and one end of the second switch element; Prepared,
The first to third switch elements are synchronous circuits that operate based on a second clock signal having a predetermined period. A processing circuit for performing predetermined processing based on a first clock signal having a predetermined clock cycle;
A first power supply line for supplying a first power supply voltage of a predetermined magnitude to the processing circuit;
A third power supply line for supplying a third power supply voltage greater than the first power supply voltage;
A resistance element having one end connected to the first power line;
A fourth switch element having one end connected to the other end of the resistance element and the other end connected to the third power supply line;
The fourth switch element is a synchronization circuit that operates based on a second clock signal having a predetermined period. A processing circuit for performing predetermined processing based on a first clock signal having a predetermined clock cycle;
A first power supply line for supplying a first power supply voltage of a predetermined magnitude to the processing circuit;
A third power supply line for supplying a third power supply voltage greater than the first power supply voltage;
A fifth switch element having one end connected to the first power line;
A sixth switch element having one end connected to the other end of the fifth switch element and the other end connected to the third power supply line;
A third capacitor having one pole connected to a ground line and the other pole connected to the other end of the fifth switch element and one end of the sixth switch element;
The fifth to sixth switch elements are synchronous circuits that operate based on a second clock signal having a predetermined period. A processing circuit for performing predetermined processing based on a first clock signal having a predetermined clock cycle;
A first power supply line for supplying a first power supply voltage of a predetermined magnitude to the processing circuit;
A fourth capacitor having one pole connected to the first power line;
An inverter having an output connected to the other pole of the fourth capacitor;
A second power line for driving the inverter,
The input of the inverter is a synchronous circuit to which a second clock signal having a predetermined cycle is given. A synchronization circuit according to any one of claims 1 to 5,
The second clock signal is a synchronizing circuit having a half period of the first clock signal. A synchronization circuit according to any one of claims 1 to 5,
The second clock signal is a synchronization circuit having the same cycle as the first clock signal. A synchronization circuit according to any one of claims 1 to 7,
The synchronization circuit in which the phase of the second clock signal is more advanced than that of the first clock signal. A synchronization circuit according to any one of claims 1 to 8,
A synchronization circuit further comprising a pulse generation circuit that converts and outputs a pulse width of the second clock signal. A semiconductor chip comprising the synchronization circuit according to any one of claims 1 to 9,
A semiconductor chip in which the synchronization circuit is arranged in a corner cell region of an input / output unit. A semiconductor chip comprising the synchronization circuit according to any one of claims 1 to 9,
A semiconductor chip in which the synchronization circuit is disposed in a power cell region of an input / output unit. A semiconductor chip comprising the synchronization circuit according to any one of claims 1 to 9,
A semiconductor chip in which the synchronization circuit is arranged in a power supply trunk region.

Images