JP2005005678A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new method for making conductor paths and resistors on a semiconductor device. <P>SOLUTION: In this method, at least one of conductor path and/or at least one of resistor is formed by deeply oxidizing a conductive layer in a partial region to electrically isolate at least one area of the conductive layer from the other areas. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having at least one conductor layer, and at least a conductor path and / or at least one resistor formed in the at least one conductor layer. The present invention also relates to a method for manufacturing this type of semiconductor device.

  In order to form a conductor path and a resistor on a semiconductor element, usually, a conductive layer is first formed on the surface of the semiconductor element. This conductive layer can be a thin metal layer made of, for example, aluminum, nickel, platinum or gold, or a polycrystalline or monocrystalline silicon layer. From this conductive layer, the desired arrangement of conductor tracks and resistors is structured and extracted by photolithography and etching processes. The arrangement is then electrically insulated, for example by depositing an insulator such as silicon oxide SiO2.

  Furthermore, a technique for selectively oxidizing a silicon layer is known from experience. This LOCOS (local oxidation of silicon) method is used to form a field oxide region around a gate oxide when, for example, a microchip having a MOS transistor is manufactured.

  An object of the present invention is to provide a new means for forming a conductor path and a resistor in a semiconductor element.

  The object is to oxidize at least one region of the conductive layer by forming at least one conductor track and / or at least one resistance by subjecting the conductive layer to partial oxidation. This is solved by a manufacturing method characterized in that the region is electrically insulated from other regions of the conductive layer.

  The present invention provides a new means for forming a conductor path and a resistance path in a semiconductor element.

  According to the present invention, the conductive layer of the semiconductor element is deeply oxidized in a part of the region, so that at least one region of the conductive layer, that is, the arrangement of the conductor path and the resistor, is formed by the oxidized region. It is electrically isolated from other areas of the layer.

  In the present invention, it is recognized that the LOCOS method is also suitable for forming a conductor path and resistor arrangement in a conductive layer. This is because, in this method, the individual regions of the conductive layer are deeply oxidized as expected, so that they are electrically insulated from other regions of the conductive layer. It is particularly advantageous that conductor tracks and resistors can be formed on or in thin membranes with poor thermal conductivity, for example in order to realize heater structures and piezoresistors. In this case, the thick oxide region is advantageously used to stabilize the membrane. A thick oxide region provides particularly good thermal insulation.

  Basically, various means exist for realizing the semiconductor device according to the invention, in particular with regard to the properties of the conductive layer. What is important is that the material of the conductive layer is capable of deep oxidation and the resulting oxide forms a good electrical insulator.

  In an advantageous variant, a polycrystalline silicon layer is used as the conductive layer. The polycrystalline silicon layer can be formed very easily by a method known from semiconductor technology. In addition to the polycrystalline silicon layer, a monocrystalline silicon layer can alternatively be used as the conductive layer. In this variant, the component is advantageously realized by an SOI (silicon on insulator) wafer. An SOI wafer consists of a substrate on which at least one insulating layer is arranged. A thin single crystal silicon layer is provided on the insulating layer. By the method of the present invention, the arrangement of conductor paths and resistors is very simply configured in this single crystal silicon layer. Furthermore, the silicon layer is subjected to p-type and / or n-type doping at any doping substance concentration and doping substance depth before or after the selective oxidation. This is particularly advantageous when the resistance is electrically dimensioned. Here, the doping material is inserted into the silicon layer over the whole area or locally limited. In order to dope the silicon layer, a known technique such as implantation or thermal diffusion can be used.

  If the metal is capable of deep oxidation, a thin metal layer can be considered as the conductive layer. This metal is, for example, aluminum or titanium. In this case, the conductive metal and the arrangement of the resistors are electrically insulated from the other areas of the conductive layer by suitable metal oxides.

  How the conductor path and the resistor arrangement are formed in the conductive layer of the semiconductor element of the present invention does not depend only on the material and properties of the initial substrate, but the component structure to be formed or the function of the semiconductor element Also depends on. Correspondingly, numerous variants are conceivable for carrying out the method according to the invention. What is important is that the conductive layer is deeply oxidized in some regions, and at least one region of the conductive layer is electrically insulated from other regions of the conductive layer by the oxidized region. The definition of the arrangement of conductor tracks and resistors in the conductive layer is preferably implemented by means of a mask layer. The mask layer is formed and structured on the conductive layer. Here, the region to be oxidized of the conductive layer is exposed and deeply oxidized within the thermal oxidation frame.

  As already mentioned above, various means exist to advantageously construct and develop the idea of the present invention. These means are set forth in the claims set forth below in the independent claims and in the following description of several embodiments of the invention based on the drawings.

  An oxidized silicon wafer 1 was used as an initial substrate for manufacturing the semiconductor device shown in FIGS. A silicon nitride layer 3 is deposited on the silicon oxide layer 2, and a polysilicon layer 4 is deposited on the silicon nitride layer 3. The silicon nitride layer 3 and the polysilicon layer 4 form a conductive layer of each illustrated semiconductor device. The polysilicon layer 4 is doped p-type and / or n-type locally or entirely depending on the function of the semiconductor element. Furthermore, regions having different doping substances and different doping substance concentrations can be formed by implantation or diffusion. Any stresses that occur in the component structure can be adjusted by means of a suitable additional cover layer made of, for example, oxide, nitride, SiC or the like. This is not shown here.

However, the semiconductor element shown in FIGS. 1 to 4 can also be manufactured based on an SOI wafer. A single crystal silicon layer is provided on the SOI wafer. This single crystal silicon layer is insulated from the silicon substrate by the silicon nitride layer Si ₃ N ₄ and / or the silicon oxide layer SiO ₂ . When an SOI wafer is used, a single crystal silicon layer is used as a conductive layer. This single crystal silicon layer is handled in the same manner as the polysilicon layer 4. This is explained in more detail below.

A thin silicon oxide layer SiO ₂ 5 is formed on the polysilicon layer 4 by, for example, thermal oxidation. Thereafter, a silicon nitride layer Si ₃ N ₄ 6 is deposited on the silicon oxide layer SiO ₂ 5 as a mask layer. The mask layer 6 is structured according to the arrangement of the conductive paths and resistors to be formed. At that time, the region to be oxidized in the polysilicon layer 4 is exposed. This exposed region is surface oxidized within the frame of thermal oxidation. Here, the oxidation conditions, in particular the oxidation duration, are selected such that the polysilicon layer 4 is fully deep oxidized. The silicon nitride layer 3 is used here as an oxidation stop layer. In this oxidation step, a surface-oxidized region 7 is formed in the polysilicon layer 4, and the conductor path is electrically insulated from other regions of the polysilicon layer 4 by this region. The silicon oxide layer 5 is used primarily below the mask layer 6 for stress compensation and can be omitted depending on the processing requirements. An oxide layer 9 is also formed on the silicon nitride of the mask layer 6 during the oxidation step in which the polysilicon layer 4 is deeply oxidized in some regions. This oxide layer 9 is referred to as a Reox layer.

  The electrical connection between the aluminum bonding land 10 and the conductor path 8 formed in the polysilicon layer 4 is made through the contact hole 11 in the semiconductor element shown in FIG. This contact hole 11 is later formed in the Reox layer 9, the mask layer 6 and the silicon oxide layer 5. In the semiconductor element shown in FIG. 2, the contact hole 11 is formed in the silicon oxide layer 5 after the Reox layer 9 and the mask layer 6 are removed.

  Finally, the membrane 12 is exposed by forming the cavity 13 on the back surface of the wafer by etching, for example, with KOH. In this way, heat outflow is reduced in the region of the heating conductor structure. The silicon nitride layer 3 is used as an etching stop layer when the cavity 13 is etched. In this way, a membrane with a defined target thickness can be formed very well. Therefore, the silicon nitride layer 3 takes over both the function of the oxidation stop layer when locally oxidizing the polysilicon layer 4 and the function of the etching stop layer when etching the cavity 13. Further, the membrane stress is adjusted via the silicon nitride layer 3.

  The semiconductor element shown in FIGS. 1 and 2 can be configured for use in a gas sensor. This is illustrated in FIGS. 3 and 4. For this purpose, a platinum layer 15 is formed on the membrane 12. Another metal layer may be formed instead of the platinum layer. Individual Pt conductor paths 16 are structured and removed from the platinum layer 15 and placed on the heating conductor paths 8 of the membrane 12. An insulating layer 17 made of silicon oxide, silicon nitride and / or silicon oxynitride is deposited on the platinum layer 15, and this insulating layer 17 is partially on the Pt conductor path 16 in the region of the heating conductor structure. Has been removed. Instead, a gas sensing layer 18 is mounted on the heating conductor structure and the Pt conductor path 16. When gas is added, the electrical resistance of the gas sensitive layer 18 changes, which is detected by the Pt conductor path 16. By heating with the heating conductor structure, the reactivity of the gas sensitive layer is improved.

  FIG. 5 shows the semiconductor element from which the Reox layer and the oxidation mask have been removed. This semiconductor element is envisioned for use in a flow sensor. Again, the Pt conductor path 16 is formed on the surface layer oxidized region 7 in the membrane 12. The size of the region 7 to be surface oxidized can be arbitrarily selected. However, here, the insulating layer 17 extends over the entire area of the semiconductor element other than the contact hole 11. The Pt conductor track 16 is used here to generate a temperature in the membrane 12 and to measure the temperature distribution. Since the symmetry of the temperature distribution is changed by the gas flow on the membrane 12, the flow velocity and the flow direction can be predicted by detecting the temperature distribution.

  Finally, it should be noted that components having other functions, such as IR light sources, Fresnel lenses, microfilters, thermopiles, etc., can also be produced by the method of the present invention for selectively oxidizing a conductive layer.

The cross section of the semiconductor element of this invention in which the membrane which has a heating structure was formed is shown. 2 shows the semiconductor device shown in FIG. 1 after the mask layer has been removed. 2 shows the semiconductor element shown in FIG. 1 configured as a gas sensor element. 3 shows the semiconductor device shown in FIG. 2 configured as a gas sensor. 2 shows a cross section of a semiconductor element configured as a flow sensor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon wafer 2 Silicon oxide layer 3 Silicon nitride layer-Stop layer of oxidation and etching 4 Polysilicon layer 5 Silicon oxide layer 6 Silicon nitride layer-mask layer / oxidation mask 7 Surface oxidized region 8 Conductor path / heating conductor path / Heating conductor structure 9 Reox layer 10 Aluminum bonding land 11 Contact hole 12 Membrane 13 Cavity 14-
15 Platinum layer 16 Pt conductor track 17 Insulating layer 18 Gas sensitive layer

Claims (12)

A semiconductor element having at least one conductive layer (4),
In the type in which the at least one conductive layer (4) comprises at least one conductor track (8) and / or at least one resistor,
The conductor track (8) and / or the resistor is electrically insulated from other regions of the conductive layer (4) by the oxidized region (7) in the conductive layer (4). A featured semiconductor element. The conductive layer is made of a semiconductor material;
The semiconductor element according to claim 1, wherein the semiconductor material is, for example, germanium, SiGe, SiC, or diamond-like carbon.   The semiconductor element according to claim 1, wherein the conductive layer is made of single crystal silicon or polycrystalline silicon.   4. The semiconductor device according to claim 3, wherein the conductive layer (4) is p-type and / or n-type doped in at least a part of the region. The conductive layer is made of metal;
The semiconductor element according to claim 1, wherein the metal is, for example, aluminum or titanium.   6. The semiconductor device according to claim 1, wherein the conductor path and / or the resistance is at least partially protected by at least one insulating layer. A method for manufacturing a semiconductor device having at least one conductive layer (4), comprising:
In a method of the form of forming at least one conductor track (8) and / or at least one resistor in the at least one conductive layer (4),
Deep oxidation of the conductive layer (4) in a partial region forms at least one conductor track (8) and / or at least one resistor, so that at least one region of the conductive layer (4) A manufacturing method characterized in that the oxidized region (7) is electrically insulated from other regions of the conductive layer (4). Forming a mask layer (6) on the conductive layer (4);
The mask layer (6) is structured, in which case the region to be oxidized of the conductive layer (4) is exposed and the region of the conductive layer (4) is deep-oxidized within the frame of thermal oxidation. The manufacturing method according to claim 7. A conductive layer is formed by a monocrystalline silicon layer (4) or a polycrystalline silicon layer (4);
Using the silicon nitride layer _{(Si 3 N 4) (6} ) as a mask layer, The method of claim 8. A method of manufacturing a semiconductor component having a membrane (12),
The membrane (12) has a heating conductor structure (8);
The structure of the semiconductor component is configured as a silicon substrate (1), a metal substrate, a glass substrate, or a ceramic substrate,
The silicon substrate (1), metal substrate, glass substrate or ceramic substrate has an etching stop layer (2 and / or 3);
In a manufacturing method of a type that forms a conductive single crystal silicon layer or a polycrystalline silicon layer (4) on the etching stop layer (2 and / or 3),
A mask layer (6) is mounted on the conductive silicon layer (4),
The mask layer (6) is structured in accordance with the heating conductor structure (8) to be formed on the conductive silicon layer (4), in which case the surface of the conductive silicon layer (4) Exposing the area,
The conductive silicon layer (4) is deep-oxidized based on the exposed surface area to electrically connect the heating conductor structure (8) to other areas of the conductive silicon layer (4). A manufacturing method characterized by insulating. The component structure is configured on a silicon substrate (1),
A cavity (13) is formed in the silicon substrate (1) by etching in the region of the heating conductor structure (8) from the side of the silicon substrate (1) facing the conductive silicon layer (4), 11. The method according to claim 10, wherein the etching process is limited by an etching stop layer (2 and / or 3).   The manufacturing method according to claim 10, wherein a plurality of conductor paths and resistance layers are formed.

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