JP2005005282A - Process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance fabrication yield in a process for fabricating a semiconductor device having a back electrode. <P>SOLUTION: The process for fabricating a semiconductor device comprises a step for forming semiconductor elements vertically and horizontally on the major surface of a semiconductor wafer while arranging, a step for inspecting electrical characteristics of the semiconductor element by touching a probe to an inspection pad provided on the major surface of the semiconductor wafer, a step for making the semiconductor wafer thin by removing the backside thereof by a given thickness, a step for forming a back electrode on the backside of the semiconductor wafer, and a step for forming a semiconductor device including the semiconductor elements by dividing the semiconductor wafer vertically and horizontally. In the step for forming the semiconductor elements, the inspection pads are provided on the major surface of the semiconductor elements and a part of the inspection pads are provided in a region deviding the semiconductor wafer. Subsequently, inspection of characteristics using the probe, thinning of the semiconductor wafer and formation of the back electrode are performed sequentially before the semiconductor wafer is vertically and horizontally. A lateral diffused field effect transistor is built in the semiconductor element. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a plurality of electrode terminals on a main surface and a back electrode on a back surface.
[0002]
[Prior art]
In a wireless communication system such as cellular communication, a caller's mobile phone (mobile terminal) is connected to a base station in the vicinity of the telephone network, and then sequentially connected to a single or multiple base stations. This is a system in which a mobile terminal is called and then a call with a person to be called is possible. At this time, the base station amplifies and transfers the received signal. Such amplification is performed by a mobile phone base station transmission amplifier (base station high-frequency power amplifier). The transmission amplifier has a structure in which MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor), which is one of MIS (Metal Insulator Semiconductor) type transistors, is connected in multiple stages.
[0003]
The silicon high-frequency MOSFET incorporated in the base station high-frequency power amplifier has a higher operating voltage and a higher drain breakdown voltage than a high-frequency power MOSFET incorporated in a mobile phone. Also, operation at a frequency exceeding 1 GHz is required. As such a base station silicon high-frequency MOSFET (high-frequency power transistor), an LDMOS (Laterally Diffused MOS) having advantages such as simplification of a bias circuit and high power gain is used (for example, Non-Patent Document 1).
[0004]
[Non-Patent Document 1]
Microwave Workshop Digest (MWE'99 Microwave Workshop Digest (Pages 283-288, Figure 2, Figure 3))
[0005]
[Problems to be solved by the invention]
In order to prevent oscillation, the mobile phone base station transmission amplifier has a thin semiconductor substrate on which the LDMOS is formed to reduce parasitic resistance components and the like, and a back electrode that is set to the ground potential (ground potential) is provided on the back surface of the semiconductor substrate. Yes. Therefore, in the manufacture of semiconductor devices including LDMOS, semiconductor elements including LDMOS are aligned and formed on the main surface side of the semiconductor wafer, and then the back surface side of the semiconductor wafer is removed by a predetermined thickness to reduce the thickness of the wafer. After that, a back electrode is formed on the back surface of the semiconductor wafer, and then probe inspection is performed.
[0006]
On the other hand, in manufacturing a semiconductor device using a silicon substrate (semiconductor substrate), a semiconductor substrate having a large aperture is used. This semiconductor substrate is generally called a wafer (semiconductor wafer). In addition, a wafer having a large diameter and a thin thickness has been used in recent years. For example, a wafer having a thickness of 550 μm and a diameter of 300 mm is used. In a state where probe inspection is performed, the thickness of the wafer is further reduced to about 280 μm. At such a thickness, the wafer is likely to warp and break easily. For this reason, in the manufacture of semiconductor devices including LDMOS, there is a disagreement that the yield decreases.
[0007]
FIG. 11 is a flowchart showing a conventional method for manufacturing a semiconductor device. As shown in this flowchart, semiconductor element formation (S301), wafer thinning (S302), backside electrode formation (S303), wafer run (RUN) and measurement (S304), probe inspection (S305), and chip formation (S306) ) Manufactures a semiconductor device.
[0008]
In the semiconductor element formation (S301), as shown in FIG. 12, the semiconductor elements 71 are formed in alignment on the main surface (upper surface) of the semiconductor wafer 70 vertically and horizontally. One edge of the semiconductor wafer 70 is provided with a linearly cut orientation flat surface (OFF) 72, which serves as a reference for wafer direction identification. The semiconductor elements 71 are arranged and formed in a matrix along the OFF 72 and along the direction orthogonal to the OFF 72.
[0009]
A predetermined region (D) is provided between the semiconductor element 71 and the semiconductor element 71 for cutting (dicing) or dividing (scribing) the wafer. This area is generally called a dicing area or a scribe line.
[0010]
In the case of a semiconductor element including an LDMOS, as shown in FIG. 13A, a probe inspection is performed after a back electrode 75 is formed on the back surface of the semiconductor wafer. At this stage, the wafer is thinned as described above, and the semiconductor wafer 70 is thinned. As shown in FIG. 13A, the probe inspection is performed in a state where the back surface electrode 75 on the back surface of the semiconductor wafer 70 is placed on the wafer chuck 76 which is set to the ground potential. Then, the probe inspection is performed by bringing the tip of the probe 77 into contact with the inspection pad on the main surface of the semiconductor wafer 70 from above. At this time, as shown in FIG. 13B, if the warped semiconductor wafer 70 is held by a plurality of probes 77, the semiconductor wafer 70 may be cracked depending on the warped state. FIG. 13 shows a probe inspection state of a single semiconductor element 71 portion, and shows that the semiconductor element 71 portion is broken by thinning of the semiconductor wafer 70.
[0011]
An object of the present invention is to improve manufacturing yield in a method for manufacturing a semiconductor device having a back electrode.
[0012]
Another object of the present invention is to improve the manufacturing yield in a method for manufacturing a semiconductor device including an LDMOS.
[0013]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0014]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0015]
(1) A manufacturing method of a semiconductor device of the present invention includes:
A step of arranging and arranging semiconductor elements vertically and horizontally on the main surface of the semiconductor wafer;
A characteristic inspection step of inspecting electrical characteristics of the semiconductor element by bringing a probe into contact with an inspection pad provided on a main surface of the semiconductor wafer;
A thinning process for removing the thickness of the back surface of the semiconductor wafer by a predetermined thickness; and
Forming a back electrode on the back surface of the semiconductor wafer; and
Dividing the semiconductor wafer vertically and horizontally, forming a semiconductor device including the semiconductor element, and a method of manufacturing a semiconductor device,
In the step of forming the semiconductor element, a test pad is provided on the main surface of the semiconductor element and a part of the test pad is provided in a dividing region for dividing the semiconductor wafer,
Thereafter, characteristic inspection with the probe, thinning of the semiconductor wafer, and formation of the back electrode are sequentially performed, and then the semiconductor wafer is divided vertically and horizontally.
[0016]
The test pad provided in the dividing region is a ground electrode test pad that is a ground potential, or a ground electrode test pad and a control electrode test pad that is a potential different from the ground potential. The dividing area is a dicing area cut and removed by a dicing blade, and the inspection pad is formed in the dicing area. The semiconductor element includes at least one lateral diffusion field effect transistor (LDMOS).
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.
[0018]
(Embodiment 1)
1 to 8 are diagrams relating to a method of manufacturing a semiconductor device according to an embodiment (Embodiment 1) of the present invention. FIG. 1 is a schematic diagram showing a probe inspection state in a semiconductor device manufacturing method, FIG. 2 is a flowchart showing a semiconductor device manufacturing method, FIG. 3 is a schematic plan view of the manufactured semiconductor device, and FIG. 4 is a manufactured semiconductor. FIG. 5 is a schematic cross-sectional view of an LDMOS showing a part of a semiconductor device, FIG. 6 is a schematic plan view of a part of a wafer on which a semiconductor element is formed, and FIG. 7 is a probe inspection state. FIG. 8 is a schematic sectional view showing a probe inspection state.
[0019]
In the first embodiment, an example in which the present invention is applied to a method for manufacturing a semiconductor device incorporated in a high frequency power amplifier (high frequency power MOSFET device) for a base station will be described. The semiconductor device according to the first embodiment has two types of GSM (Global System for Mobile Communication) and DCS (Digital Cellular System) systems in which three stages of transistors are connected in series with the first stage, the next stage, and the last stage (output stage), respectively. The communication system includes a first stage and a next stage, a control IC (Integrated Circuit), and a matching circuit.
[0020]
That is, FIG. 3 is a schematic diagram of the semiconductor device 1 and shows a layout of transistors (LDMOS: LD-MOS) 2 to 5 and a control IC (control IC unit) 6. LDMOSs 2 to 5 are arranged at the four corners of the semiconductor device 1, and a control IC 6 for controlling these is located at the center. In this figure, a matching circuit and the like disposed between the control IC 6 and the LDMOSs 2 to 5 are omitted. In addition, an electrode pad for connecting a wire or the like is provided around the semiconductor device 1, which is also omitted.
[0021]
The LDMOS 2 in the upper left corner of the semiconductor device 1 constitutes a GSM first-stage amplifier, and the LDMOS 3 in the upper right corner constitutes a GSM next-stage amplifier. The LDMOS 4 in the lower left corner constitutes a DCS first-stage amplifier, and the LDMOS 5 in the lower right corner constitutes a DCS next-stage amplifier.
[0022]
FIG. 4 is a schematic cross-sectional view showing active elements and passive elements formed in the semiconductor device 1. For convenience of explanation, in this figure, from left to right, protection diodes, LDMOS, resistors, capacitors, NMOS, and PMOS are shown. The semiconductor device 1 shown in FIG. 3 is formed by combining these elements.
[0023]
The semiconductor device 1 includes a semiconductor region of a desired conductivity type on a surface layer portion of a P-type epitaxial layer 11 formed on a main surface (upper surface) of a semiconductor substrate 10 made of P-type (p ⁺ -type) silicon (Si). The predetermined element is formed. In the epitaxial layer 11, an isolation region 12 is provided at a necessary portion for forming each element, and a predetermined region is an electrically isolated and independent region. The capacitance and resistance are formed using a dielectric (insulator) or a conductive layer provided on the semiconductor substrate. The surface of the semiconductor device 1 is covered with an insulating protective film (final passivation film) 30, and a back electrode 31 is formed on the back surface. Although not shown, a part of the final passivation film 30 is removed, and the surface of the conductor layer is exposed at the opening due to the removal. The exposed portion of the conductor layer becomes the electrode pad described above. The thickness of the semiconductor substrate 10 of the semiconductor device 1 is as thin as 280 μm, for example.
[0024]
Although description of the structure of each element in the semiconductor device 1 is omitted, an LDMOS that requires a thin semiconductor substrate (semiconductor wafer) will be described with reference to FIG.
[0025]
FIG. 5 is a schematic cross-sectional view showing the structure of the LDMOS. A P-type epitaxial layer 11 is provided on the main surface of the semiconductor substrate 10 made of low-resistance P-type silicon. P-type P-well regions (PW) 15 and 16 are provided on the surface layer portion of the epitaxial layer 11 so as to be separated from each other by a predetermined distance. This layer acts as a punch-through stopper layer.
[0026]
A surface layer portion of the epitaxial layer 11 between the pair of P well regions 15 and 16 is an N-type drain offset region 17. An N-type drain region 18 is provided in an N-type drain offset region 17 portion between the pair of P-well regions 15 and 16. The bottom of the drain region 18 passes through the N-type drain offset region 17 and extends to a midway depth of the epitaxial layer 11.
[0027]
On the other hand, on the outside of the pair of P-well regions 15 and 16 with the ^{P +} -type region 19 to reach the middle depth of the semiconductor substrate 10 so as to surround the like P-well regions 15 and 16 are provided, the ^{P +} -type A P ⁺ -type P-type contact region 20 whose surface is exposed is provided on the region 19. Further, an N-type source region 21 is provided in the surface layer portion of the pair of P-well regions 15 and 16 at a predetermined distance from the end of the N-type drain offset region 17.
[0028]
A well region portion between the N-type drain offset region 17 and the source region 21 becomes a channel layer. A gate electrode 23 is formed on the channel layer via a gate insulating film (oxide film) 22.
[0029]
A predetermined number of insulating films are formed on the main surface side of the semiconductor substrate 10, and contact holes and the like are provided in the predetermined insulating films. The contact hole is filled with a conductor, and this conductor is connected to a wiring layer, a source electrode, a drain electrode, and a gate electrode formed on the insulating film. Although schematically shown in FIG. 5, the P-type contact region 20 and the source region 21 are electrically connected via the conductor 25 and the source wiring 26. Accordingly, the source region 21 is electrically connected to the semiconductor substrate 10 and is electrically connected to a back electrode 31 (not shown) formed on the back surface of the semiconductor substrate 10. Since the source region is electrically guided to the back surface electrode 31 on the back surface of the semiconductor substrate 10 by the P ⁺ type region 19 extending so as to penetrate the epitaxial layer 11 vertically, the parasitic resistance component (ON resistance) is reduced. It becomes difficult to oscillate when used in a high frequency range.
[0030]
The drain region 18 is electrically connected to the drain electrode 27 through the conductor 25. Thus, the LDMOS is a lateral diffusion type field effect transistor.
[0031]
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. As shown in the flowchart of FIG. 2, the semiconductor device 1 having the structure shown in FIG. 3 to FIG. 5 includes semiconductor element formation (S101), wafer run (RUN) / measurement (S102), probe inspection (S103), and wafer thinness. It is manufactured through each step of forming (S104), forming a back electrode (S105), and forming a chip (S106).
[0032]
In the formation of semiconductor elements, semiconductor elements are aligned and formed vertically and horizontally on the main surface of a semiconductor wafer made of P-type silicon. As shown in FIG. 3, each semiconductor element has a control IC and four LDMOSs. For example, a semiconductor wafer having a thickness of 550 μm is used.
[0033]
FIG. 6 is a plan view schematically showing a part of a semiconductor wafer 40 made of P-type silicon. FIG. 6 shows four semiconductor elements 41 arranged in alignment. In the final stage of manufacturing the semiconductor device, the semiconductor wafer 40 is cut into a plurality of semiconductor devices 1 in the vertical and horizontal directions. For this cutting, the semiconductor element 41 is provided with a region called a dicing region or a scribe line in a lattice shape between adjacent semiconductor elements 41. In FIG. 6, the line drawn between the semiconductor elements 41 is the scribe line 42.
[0034]
Scribing is a cutting method that uses the cleavage property (cleavage plane) of silicon crystal to cleave, but the cleavage is not necessarily a straight line. For this reason, it is designed to have a predetermined width on both sides of the scribe line so that cracks and the like do not extend in the semiconductor element 41.
[0035]
There is also a method in which the semiconductor wafer 40 is cut by a rotating blade (dicing blade). In this case, since the cutting margin is cut with a width slightly wider than the width of the blade, the width of the dicing area is also slightly wider than the width of the scribe line. In FIG. 6, for example, a region having a certain width along the scribe line 42, that is, a hatched region is a dicing region 43. The dicing area 43 is not cut entirely, but is set wider than the cutting width of the blade, and is set to a size that prevents fine cracks generated by dicing from reaching the semiconductor element 41.
[0036]
In the first embodiment, this is one of the features of the present invention, but the inspection pad 45 is disposed on the scribe line 42. The inspection pad 45 has a size smaller than the width of the dicing region 43 and is located in a region that is removed by dicing. The test pad 45 is a ground electrode that becomes a ground potential, and is electrically connected to the ground electrode of each element that requires the above-described source region 21 (see FIG. 8).
[0037]
In addition, as shown in FIG. 6, a plurality of electrode pads 46 are provided along the periphery of each semiconductor element 41. Accordingly, in the probe inspection, it is possible to perform a predetermined electrical property inspection by selecting the predetermined electrode pad 46 and the inspection pad 45 and bringing the tip of the probe into contact with these pads. That is, the probe inspection can be performed even when the back electrode is not formed on the back surface of the semiconductor wafer 40. In other words, probe inspection can be performed even when the semiconductor wafer 40 is not thinned.
[0038]
In the first embodiment, although not particularly limited, for example, the width of the dicing region 43 is 60 μm, and both the inspection pad 45 and the electrode pad 46 are squares each having a side of 45 μm. The inspection pad 45 is provided in the center of the dicing area 43. Further, as shown in FIG. 6, the inspection pad 45 is displayed as a black-filled square.
[0039]
FIG. 7 is a diagram showing a state in which the probe inspection is performed by bringing the probe 47 into contact with the inspection pad 45 in a state where the semiconductor wafer 40 is not thinned. This figure schematically shows a part of one semiconductor element 41. The semiconductor wafer 40 without warp, in other words, the semiconductor element 41 without warp is placed on the wafer chuck 50, and the inspection pad 45 is shown. FIG. 6 is a view showing a state in which a probe 47 is in contact with an electrode pad 46.
[0040]
FIG. 1 schematically shows the probe inspection state. FIG. 1 is a diagram schematically showing a part of a semiconductor wafer 40. In the figure, a probe 47 is brought into contact with a test pad 45 provided in the left dicing region 43 of the semiconductor element 41 and a right electrode pad 46 provided on the surface (main surface) of the semiconductor element 41. .
[0041]
FIG. 8 is a diagram schematically showing a part of the semiconductor element 41. This figure shows a state in which the test pad 45 is arranged in the dicing area 43 indicated by the rightmost arrow. The test pad 45 is electrically connected to a P-type semiconductor substrate 10 that is at a ground potential. In this way, probe inspection is performed.
[0042]
In the first embodiment, as shown in FIG. 7, since the semiconductor substrate portion of the semiconductor wafer 40 is as thick as 550 μm, there is no warpage of the semiconductor wafer 40, and therefore there is no warpage of the semiconductor element 41, and a plurality of probes 47 are provided. Even if it is brought into contact with the inspection pad 45 or the electrode pad 46, the semiconductor wafer 40 is not cracked. Even if the semiconductor wafer 40 is warped, the warp is small. Further, since the semiconductor wafer 40 is thick, the warpage is extremely small in one semiconductor element 41 portion (measured semiconductor element portion). Therefore, even when the semiconductor element portion to be measured is pressed against the wafer chuck 50 by the probe 47, the semiconductor element portion to be measured is hardly cracked or cracked.
The method for manufacturing a semiconductor device according to the first embodiment has the following effects.
[0043]
(1) Since the inspection pad 45 is disposed and formed in the divided region (dicing region 43) of the wafer 40 at the stage of forming the semiconductor element 41 on the semiconductor wafer 40, the back electrode is formed by using the inspection pad 45. Probe inspection can be performed even in a state of not performing. Accordingly, since the probe inspection is performed in a relatively thick wafer state before the thinning of the wafer 40, the wafer 40 is hardly warped, and the wafer is not cracked or cracked by contact of the probe in the probe inspection. Improvements can be made. Moreover, since generation | occurrence | production of a crack can also be suppressed, the semiconductor device 1 with favorable quality can be manufactured.
[0044]
(2) According to the above (1), the semiconductor device 1 can be manufactured at a high yield even in the manufacture of the LDMOS in which the semiconductor substrate portion is thinned in order to reduce the parasitic resistance and the like, and the manufacturing cost of the semiconductor device 1 can be reduced. Can be achieved.
[0045]
(3) If a pad (inspection pad 45) used only for inspection that is not required after manufacturing is provided in the dicing region 43, the chip area can be reduced correspondingly, and the semiconductor device 1 can be reduced in size. Is also possible. As a result, the number of chips obtained from one wafer 40, that is, the number of semiconductor devices 1, increases, and the cost of the semiconductor devices 1 can be reduced.
[0046]
(Embodiment 2)
9 and 10 are diagrams relating to a method for manufacturing a semiconductor device according to another embodiment (Embodiment 2) of the present invention. FIG. 9 is a schematic plan view showing a single semiconductor element 41 portion in the semiconductor wafer 40.
[0047]
In the second embodiment, as shown in FIG. 9, the control electrode inspection pad 55 is arranged in the dicing area 43 in addition to the inspection pad 45. FIG. 10 is a schematic diagram schematically showing an electrical connection relationship between the control electrode test pad 55 and the test pad 45 and the control IC 6 and the LDMOS 3 in the semiconductor element 41. The inspection pad 45 provided in the dicing region 43 (dividing region) is a ground electrode inspection pad that is at the ground potential.
[0048]
On the other hand, the control electrode test pad 55 is a test pad having a potential different from the ground potential. In the present embodiment, for example, the threshold value of the LDMOS can be measured. That is, since the LDMOS of the output section (next stage amplifier) controls the gate terminal by the control IC 6, the Vth (threshold value) of the LDMOS alone cannot be measured by the probe inspection. However, by providing the control electrode inspection pad 55 for Vth measurement in the dicing region 43 in this way, Vth measurement can be easily measured. In the present applicant, one of the electrode pads 46 provided on the semiconductor element 41 is used as a probe inspection pad. This pad is connected to the gate electrode. This makes it possible to measure the Vth of the next-stage amplifier, but there is a problem that the number of electrode pads 46 on the surface of the semiconductor element 41 increases.
[0049]
By providing such a control electrode inspection pad 55 in the dicing region 43, a part of the electrode pads 46 of the semiconductor element 41 are not used as inspection pads, and the semiconductor element 41 can be downsized accordingly. Can do. It is possible to increase the number of semiconductor devices 1 acquired from a single wafer. The control electrode test pad 55 can also be provided as a test pad for measuring electrical characteristics of other elements.
[0050]
Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the invention. Nor.
[0051]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0052]
(1) The production yield of a semiconductor device having a back electrode can be improved.
(2) The manufacturing yield of semiconductor devices including LDMOS can be improved. For example, the production yield of the high frequency power amplifier for base stations can be improved.
(3) More semiconductor devices having backside electrodes can be manufactured from one wafer.
(4) Cost reduction can be achieved by increasing the manufacturing quantity of semiconductor devices and improving yield.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a probe inspection state in a semiconductor device manufacturing method according to an embodiment (Embodiment 1) of the present invention.
FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment.
FIG. 3 is a schematic plan view of a semiconductor device manufactured by the semiconductor device manufacturing method of Embodiment 1. FIG.
4 is a schematic cross-sectional view of a semiconductor device manufactured by the semiconductor device manufacturing method of Embodiment 1. FIG.
FIG. 5 is a schematic cross-sectional view of an LDMOS showing a part of the semiconductor device.
6 is a schematic plan view of a part of a wafer on which a semiconductor element is formed in the semiconductor device manufacturing method of Embodiment 1. FIG.
7 is a schematic view showing a probe inspection state in the semiconductor device manufacturing method of Embodiment 1. FIG.
8 is a schematic cross-sectional view showing a probe inspection state in the semiconductor device manufacturing method of Embodiment 1. FIG.
FIG. 9 is a schematic plan view showing a single semiconductor element portion in a wafer state in a semiconductor device manufacturing method according to another embodiment (Embodiment 2) of the present invention.
FIG. 10 is a schematic diagram showing an electrical connection relationship between a test pad provided in a dividing region of a wafer and a semiconductor element in the semiconductor device manufacturing method according to the second embodiment.
FIG. 11 is a flowchart of a conventional method for manufacturing a semiconductor device.
FIG. 12 is a schematic plan view of a wafer in a conventional semiconductor device manufacturing method.
FIG. 13 is a schematic view showing a probe inspection state in a conventional semiconductor device manufacturing method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2-5 ... LDMOS, 6 ... Control IC, 10 ... Semiconductor substrate, 11 ... Epitaxial layer, 12 ... Isolation region, 15, 16 ... P well region, 17 ... Drain offset region, 18 ... Drain region , 19 ... P ⁺ type region, 20 ... P type contact region, 21 ... source region, 22 ... gate insulating film (oxide film), 23 ... gate electrode, 25 ... conductor, 26 ... source wiring, 27 ... drain electrode, 30 DESCRIPTION OF SYMBOLS ... Protective film (final passivation film), 31 ... Back electrode, 40 ... Semiconductor wafer, 41 ... Semiconductor element, 42 ... Scribe line, 43 ... Dicing area, 45 ... Inspection pad, 46 ... Electrode pad, 47 ... Probe, 50 ... Wafer chuck, 55 ... control electrode inspection pad, 70 ... semiconductor wafer, 71 ... semiconductor element, 72 ... orientation Flat surface (OFF), 75 ... Back electrode, 76 ... Wafer chuck, 77 ... Probe.

Claims (5)

A step of arranging and arranging semiconductor elements vertically and horizontally on the main surface of the semiconductor wafer;
A characteristic inspection step of inspecting electrical characteristics of the semiconductor element by bringing a probe into contact with an inspection pad provided on a main surface of the semiconductor wafer;
A thinning process for removing the thickness of the back surface of the semiconductor wafer by a predetermined thickness; and
Forming a back electrode on the back surface of the semiconductor wafer; and
Dividing the semiconductor wafer vertically and horizontally, forming a semiconductor device including the semiconductor element, and a method of manufacturing a semiconductor device,
In the step of forming the semiconductor element, a test pad is provided on the main surface of the semiconductor element and a part of the test pad is provided in a dividing region for dividing the semiconductor wafer,
Thereafter, a characteristic inspection using the probe, thinning of the semiconductor wafer, and formation of the back electrode are sequentially performed, and then the semiconductor wafer is divided vertically and horizontally. The method of manufacturing a semiconductor device according to claim 1, wherein the inspection pad provided in the dividing region is a ground electrode inspection pad having a ground potential. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the test pads provided in the dividing region are a ground electrode test pad that is a ground potential and a control electrode test pad that is a potential different from the ground potential. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the divided region is a dicing region cut and removed by a dicing blade, and the inspection pad is formed in the dicing region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein at least one lateral diffusion field effect transistor is formed in the semiconductor element.

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