JP2005004698A - Optical module and host system equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily switch possible/impossible of data writing to a ROM built in an optical module from an external system equipment side by adding a circuit consisting of a gate element (inverter) and a resistor in the optical module. <P>SOLUTION: The optical module 10 is connectable with a system equipment 20 and has a gate circuit 4 consisting of an EEPROM 3b for storing the data, a writing protection terminal WP, the gate element 4b and the resistor 4a for setting writable/unwritable of data to the EEPROM 3b. The gate circuit 4 outputs "High" to the WP in the case that an input level from the system equipment 20 is "Low" and outputs "Low" to the WP in the case that the input level from the system equipment 20 is "High". The EEPROM 3b becomes to be unwritable when "High" is output to the WP and becomes to be writable when "Low" is output to the WP. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an optical module and a host system device, and more particularly, to an optical module applicable to an SFP (Small Form Factor Pluggable) type optical transceiver and the like, and a host system device incorporating the optical module.
[0002]
[Prior art]
There is an increasing demand for optical transceivers that transmit and receive optical signals to and from optical fibers. An MSA (Multi Source Agreement) that determines the electrical specifications, appearance specifications, etc. is concluded for a full duplex optical transceiver that can exchange optical signals simultaneously with a two-core optical fiber (transmission / reception). An optical transceiver based on the MSA standard has been manufactured (for example, see Patent Document 1 and Patent Document 2).
[0003]
FIG. 6 is a perspective view showing an example of the appearance of an optical transceiver based on the MSA standard. In FIG. 6, 30 is an optical transceiver, and the optical transceiver 30 has an optical receptacle 31 for inserting an optical connector.
Since the optical transceiver before the MSA standard is several centimeters wide, it was assumed that the transceiver would be used as a single unit. As shown in FIG. 6, for example, when an elongated product having a width of about 1 cm is mounted on a system device, it is used side by side in the horizontal direction (that is, the width direction of the system device). An LC connector is used as the optical connector. Moreover, the said width | variety is the same dimension as the connector based on specifications, such as 10-BASE-T and 100-BASE-T which are specifications about a copper Ethernet (R) cable. In other words, the communication around the LAN, which has been performed with the conventional copper cable, is intended to be performed with the optical cable.
[0004]
For the above-described elongated optical transceiver, two types of standards are defined by the MSA. They are called SFF (Small Form Factor) type and SFP (Small Form Factor Pluggable) type, respectively. The former (SFF type) has the structure shown in FIG. 6 and is fixed directly to the mother board by a method such as soldering, exposing only the optical connector portion from the face panel of the system device, and inserting and removing the optical connector from the outside. Of the form.
[0005]
FIG. 7 is a diagram illustrating an example of a state in which the SFP optical transceiver is attached to the substrate of the evaluation jig. FIG. 7A is a perspective view showing a state in which the SFP type optical transceiver is attached to the substrate of the evaluation jig, and FIG. 7B is a front view showing a state in which the SFP type optical transceiver is attached to the substrate of the evaluation jig. In the figure, reference numeral 40 denotes an SFP optical transceiver, and the SFP optical transceiver 40 has an optical receptacle 41 for inserting an optical connector.
As shown in FIGS. 7A and 7B, in the latter (SFP type), a cage 42 (made of metal in this example) surrounding the main body is fixed to a substrate (motherboard) 43 of an evaluation jig by soldering or the like. The SFP optical transceiver 40 (made of resin in this example) is inserted into the cage 42 and used.
[0006]
FIG. 8 is a perspective view showing a state in which the SFF type optical transceiver 30 or the SFP type optical transceiver 40 is mounted on the system equipment. In FIG. 8, 50 is a system equipment, and the system equipment 50 is the SFF type optical transceiver 30 or SFP. A plurality of type optical transceivers 40 are mounted. As shown in FIG. 8, when both optical transceivers (SFF type and SFP type) are attached to the system device 50, the attachment state of both is substantially the same, but in the case of the SFP type optical transceiver 40, the electrical signal is the main body. Even when input / output is performed from the rear side, that is, from the opposite side of the optical receptacle 41 into which the optical connector is inserted (commonly referred to as the rear / butt side of the main body), that is, even when the electricity is “on”. This means that the SFP optical transceiver 40 main body can be inserted and removed from the system device 50. Thus, it is called Pluggable (Plug + able) because it can be inserted and removed even when the electricity is “on”.
[0007]
Here, in the MSA standard, it is obliged to write manufacturing information in a ROM (referred to as an EEPROM in this example) mounted on the SFP optical transceiver 40. At this time, in order to prevent rewriting or erasure of data by a third party, it is desirable to protect the manufacturing information written in the EEPROM. For this reason, most EEPROMs are provided with a write protect (WP) function. Normally, writing to the ROM is permitted when the voltage at the WP input terminal is “Low”, and writing to the EEPROM is prohibited when the voltage is “High”.
[0008]
Therefore, in the manufacturing information writing process to the EEPROM, it is necessary to release the WP, while at the shipping stage, it is necessary to apply the WP to prevent alteration of the written manufacturing information. That is, the input voltage (High / Low) to the WP terminal is switched in order to enable / disable writing to the EEPROM. Therefore, it is necessary to supply a voltage to the WP terminal from the outside of the SFP type optical transceiver. However, in the SFP optical transceiver, the role of the edge connector terminal that is exposed to the outside is determined in advance, and signals cannot be input from the external terminal. Further, since the SFP type optical transceiver is covered with a metal cover or the like, a voltage cannot be directly applied to the inside.
[0009]
FIG. 9 is a block diagram for explaining a data write enable / disable setting method in the conventional SFP type transceiver 40. 9A, a system device 50 includes a PLD / PAL (Programmable Logic Device / Programmable Array Logic) unit 51, a power supply line 52, and a resistor 53. In FIG. 9B, the SFP optical transceiver 40 is EEPROM 40a provided with a write protect (WP) terminal. FIG. 9C is a block diagram showing a state in which the SFP optical transceiver 40 is connected to the system device 50. The PLD / PAL unit 51 communicates a control signal from a Host CPU (not shown) included in the system device 50 with the SFP optical transceiver 40. ² It is a kind of gate array for converting to the C protocol and plays the role of a sub CPU (this I ² For details on C, see, for example, Patent Document 3).
[0010]
Here, among MOD_DEF (0) to (2) used for control among pins (terminals) of the SFP optical transceiver 40, MOD_DEF (1) and MOD_DEF (2) are respectively for 1-bit data and clock. However, as shown in FIG. 9B, MOD_DEF (0) in the SFP optical transceiver 40 is grounded through a resistor of about 100Ω, for example.
[0011]
On the system equipment 50 side that drives the SFP optical transceiver 40, the signal line corresponding to MOD_DEF (0) is connected to the power line 52 by a resistor 53 of 3.3 kΩ to 4.7 kΩ, for example (pulled up). In other words, the gate input for receiving the MOD_DEF (0) signal is held at “High” in the circuit in the PLD / PAL unit 51 on the system device 50 side. Next, when the SFP optical transceiver 40 is normally inserted into the cage of the system equipment 50, as shown in FIG. 9C, the MOD_DEF (0) signal line on the system equipment 50 side and the inside of the SFP optical transceiver 40 Since the MOD_DEF (0) signal line of the MOD_DEF (0) signal is connected, the level of the MOD_DEF (0) signal is set to the pull-up resistor 53 (3.3 kΩ to 4.7 kΩ in this example) and the SFP optical transceiver 40 side. The level is divided by 100Ω, that is, set to the “Low” level.
[0012]
As a result, the MOD_DEF (0) signal input to the gate in the PLD / PAL unit 51 changes from “High” to “Low”, in this example, from +3.3 V to 0 V. In response to this change, the system device 50 recognizes that the main body of the SFP optical transceiver 40 has been inserted into the corresponding SFP cage, and as long as the signal continues to be in the “Low” state, the SFP optical transceiver is in the cage. 40 can be confirmed.
[0013]
In the SFP type optical transceiver 40 as described above, data is written into the EEPROM 40a built in at the time of factory shipment. At this time, the WP (write protect) of the EEPROM 40a is removed (that is, the WP terminal is set to “Low”).
[0014]
Conventionally, the WP terminal is always set to “Low” (enable). That is, it was dropped to the GND pattern. Since the WP terminal function is not involved in reading from the EEPROM 40a, even if the WP terminal is dropped to GND, there is no problem in terms of Read / Write functions. However, since it is enabled, that is, in a writable state when actually used, there is a possibility that data in the EEPROM 40a is rewritten due to misuse by the user, which is not appropriate.
[0015]
Therefore, in order to write-protect the EEPROM 40a, after writing data to the EEPROM 40a in the write-protection OFF state, data write enable / disable the data protection by adding a chip component (jumper) on the board. There is an impossible setting method. In the case of the small-sized SFP type optical transceiver 40, since there is no space for mounting a switch for switching ON / OFF of the write protection, it is the actual situation to cope with this by adding a jumper. However, according to the data writable / impossible setting method, the chip component mounting process is increased by one, and the component mounting is performed in the final process of the product, so that the package mechanism design is also restricted. .
[0016]
[Patent Document 1]
US Pat. No. 6,149,465
[Patent Document 2]
JP 2001-298217 A
[Patent Document 3]
U.S. Pat. No. 4,689,740
[0017]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and by adding a circuit composed of a gate element (inverter) and a resistor inside the optical module, data can be written to a ROM built in the optical module. This is for the purpose of enabling easy switching from the external system device side.
[0018]
[Means for Solving the Problems]
The present invention is an optical module for transmitting / receiving optical signals to / from an optical fiber, which can be connected to a host system device, a memory for storing data, and data writable / impossible to the memory. It has a write protection terminal for setting and a circuit composed of a gate element and a resistor, and the circuit outputs “High” or “Low” to the write protection terminal according to the input level from the host system device. It is characterized by doing.
[0019]
The present invention also relates to a host system device incorporating an optical module for transmitting and receiving an optical signal to and from an optical fiber. The optical module includes a memory for storing data and data writing to the memory. It has a write protection terminal for setting enable / disable and a circuit composed of a gate element and a resistor, and the circuit has “High” or “high” at the write protection terminal according to the input level from the host system device. Low 'is output.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an example of an internal circuit of an SFP optical transceiver according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an SFP optical transceiver (hereinafter often referred to as an SFP optical module). The optical transceiver 10 includes a light emitting element unit 1 (hereinafter referred to as a Tx unit 1), a light receiving element unit 2 (hereinafter referred to as an Rx unit 2), and a control unit 3. As described above, the inside of the SFP optical transceiver 10 of the present embodiment is roughly divided into the Tx part 1, the Rx part 2, and the control part 3. The Tx unit 1 receives TD from a system device (not shown). ⁺ , TD ⁻ In response to this signal, the semiconductor laser 1a (hereinafter referred to as LD1a) is driven to generate signal light to the optical fiber.
[0021]
In the Tx unit 1, two signals of TxDisable and TxFault are set as information signals from the outside or information signals to the outside. The TxDisable is a signal for forcibly turning off the light emission of the LD1a, and the TxFault is feedback controlled (APC: Auto Power Control) so that the integrated value of the light emission intensity of the LD1a is constant. However, this is a signal for informing the outside that an error has occurred in the LD 1a itself or a circuit for monitoring the light emission from the LD 1a and this APC control loop is not functioning normally.
[0022]
The Rx unit 2 receives a signal from an optical fiber by a photodiode 2a (Photo Diode, hereinafter referred to as PD2a), regenerates a normal data signal from the received signal, and outputs it. ⁺ , RD ⁻ Furthermore, in the Rx unit 2, as an information signal from the outside or an information signal to the outside, an RxRate signal indicating how much the signal speed of the currently received data is, and the received signal is too weak and the data signal is normally transmitted. There are two types of signals: an RxLOS (Loss Of Signal) signal indicating that reproduction is not possible.
[0023]
The control unit 3 includes a CPU 3a and a ROM 3b. ₁ ROM3b ₂ ,... (Hereinafter represented by ROM 3b). The CPU 3a is a control CPU and generally uses a 1-bit type. This is because the SFF type and SFP type optical transceivers cannot be equipped with a high-performance CPU due to the small housing volume or area of the internal circuit board. This results in a 1-bit CPU. In accordance with this, the ROM 3b is generally a 1-bit ROM.
[0024]
For the RAM (not shown), the internal register of the CPU 3a is used as the RAM. The communication between the CPU 3a and the outside (system equipment) is I ² This is performed via the C bus (for details, see, for example, Patent Document 3). This I ² The C bus is called a two-wire bus system. One is used as a data line and the other is used as a clock line. All devices connected to the bus are W-ORed.
[0025]
In the ROM 3b, control information of the Tx part 1 and the Rx part 2 is written. When viewed on the Tx portion 1 side, for example, the value of the bias current for obtaining a predetermined optical output of the LD 1a includes a change state with respect to the temperature and a change state of the modulation current, and on the Rx portion 2 side. For example, the state of temperature change of the data threshold is included.
[0026]
FIG. 2 is a diagram illustrating an example of a terminal arrangement state in the actual SFP type optical module 10. In the SFP optical module 10 shown in the present embodiment, each signal described above is assigned to a 20-pin terminal. That is, for the three parts consisting of the Tx part 1, the Rx part 2 and the control part 3, the Tx part 1 is assigned 8 pins, the Rx part 2 is 9 pins, and the control part 3 is 3 pins. Communicate with.
Here, in the figure, the power sources VeeT and VeeR are GND (0 V), and a power source voltage of, for example, 3.3 V is supplied to VccT and VccR. The reason why the power sources VeeT, VeeR, VccT, and VccR are separated is to prevent interference between the Tx portion 1 and the Rx portion 2.
[0027]
FIG. 3 is a block diagram showing an example of an internal circuit for explaining the communication state between the SFP type optical module 10 and the system equipment. In FIG. 3, 11 is a Ser / Des-IC unit, and 12 is a PLD / PAL unit. The SFP optical module 10 is communicably connected to the host CPU 13 on the system equipment side. Further, the system device shown in the present embodiment includes a Host CPU 13, a RAM 14, a ROM 15, and a data bus 16.
[0028]
A signal from the data in the system device to the optical fiber 17 or a signal from the optical fiber 18 is input to the Ser / Des-IC unit 11. The Ser / Des-IC unit 11 is, for example, an IC for converting an 8-bit parallel signal into a 1-bit serial, or conversely, converting a 1-bit serial signal into an 8-bit parallel signal. Naturally, a 1-bit serial signal is a signal that is at least 8 times faster than an 8-bit parallel signal. The Ser / Des-IC unit 11 is in one-to-one correspondence with the SFP optical transceiver 10. That is, an 8-bit parallel signal (for example, transmission speed 140 Mbps) is input to the Ser / Des-IC unit 11 and converted into a 1-bit serial (for example, transmission speed 1120 Mbps) complementary signal. The signal is input to the Tx unit 1 of the SFP optical transceiver 10 and is converted into a corresponding optical signal by driving the LD 1 a of the Tx unit 1, and the optical signal propagates through the optical fiber 17.
[0029]
On the other hand, for example, an optical signal having a transmission speed of 1120 Mbps that has propagated through the optical fiber 18 is received by the Rx unit 2, converted into an electric signal and amplified to become a complementary signal, and then the Ser / Des-IC The data is input to the unit 11 and output, for example, as an 8-bit parallel signal with a transmission rate of 140 Mbps on the data bus 16.
[0030]
At least one Host CPU 13 is mounted on a system device, and this Host CPU 13 is capable of parallel processing of 16 to 32 bits, for example, unlike the CPU mounted inside the SFP optical module 10 (that is, the CPU 3a described above). High performance. Since it is multi-bit parallel processing, at least one system device is sufficient. However, when the signal speed increases or when the number of installed SFP modules 10 increases and the CPU performance becomes insufficient, a plurality of CPUs can be operated in parallel.
[0031]
The host CPU 13 controls the SFP optical transceiver 10 as follows.
The Host CPU 13 is accompanied by a RAM 14 and a ROM 15. A program for operating the Host CPU 13 and various constants are written in the ROM 15, and temporary data is written in the RAM 14. The Tx side TxDisable and TxFault signals of the SFP optical transceiver 10 and the RxRate and RxLOS signals on the Rx side are directly communicated with the Host CPU 13.
[0032]
On the other hand, the control signals of MOD_DEF (0) to (2) are communicated with the SFP optical transceiver 10 after being mediated by the PLD / PAL unit 12 which is one end. In FIG. 3, a portion surrounded by a dotted line is a circuit corresponding to one SFP type optical transceiver 10 on the system equipment side. Note that the PLD / PAL unit 12 is connected to the SFP type optical transceiver 10 in order to communicate a control signal from the Host CPU 13. ² It is a kind of gate array for converting to the C protocol and plays the role of a sub CPU.
[0033]
In the SFP optical transceiver 10 described above, data is written to a ROM (ROM 3b shown in FIG. 1 in this example) built in at the time of factory shipment. The ROM 3b being used is selected by an address (the address specified here is not an address for a corresponding bit in the ROM 3b but an address of the ROM 3b itself, and generally corresponds to a chip select signal). First, an address signal of 7 to 8 bits (address signal corresponding to the corresponding bit in the ROM 3b) is transmitted to one ROM as a 1-bit serial signal, and then 8-bit parallel data to be written at the address selected here is 1 Send and write as a bit serial signal. At this time, the WP (write protect) of the ROM 3b is removed (that is, the WP terminal is set to “Low”).
[0034]
As described above, conventionally, the WP terminal is always set to “Low” (enable). That is, it was dropped to the GND pattern. Since the WP terminal function is not involved in the reading of the ROM 3b, even if the WP terminal is dropped to GND, there is no problem in terms of Read / Write functions. However, since it is enabled, that is, in a writable state when actually used, the possibility of rewriting ROM data due to misuse by the user remains unsuitable.
[0035]
In order to solve the above problems, the present invention adds a gate circuit as shown in FIGS. 4 and 5 below to the inside of the SFP type transceiver 10. In the following description, an SFP type transceiver will be described as a representative example, but the present invention can be similarly applied to an SFF type transceiver.
[0036]
FIG. 4 is a diagram showing an example of a gate circuit added to the SFP type optical transceiver 10 according to the present invention. In the figure, 4 is a gate circuit, and the gate circuit 4 includes a resistor 4a and a gate element (inverter) 4b. Have. The WP terminal of the ROM 3b shown in FIG. 1 is connected to MOD_DEF (0) through the gate circuit 4 and grounded through the resistor 4a. In the present embodiment, the resistance value of the resistor 4a is assumed to be 100Ω, for example.
FIG. 5 is a block diagram for explaining a data write enable / disable setting method in the SFP optical transceiver 10 according to the present invention. 5A, the system device 20 includes a PLD / PAL unit 12, a power supply line 12a, and a resistor 12b. In FIG. 5B, the SFP optical transceiver 10 includes a write protect (WP) terminal. ROM 3b (in this example, EEPROM 3b) and gate circuit 4 are provided. FIG. 5C is a block diagram illustrating a state where the SFP optical transceiver 10 is connected to the system device 20.
[0037]
Here, as described above with reference to FIG. 9, the MOD_DEF (0) signal is a signal for representing a DC level for confirming whether or not the SFP optical transceiver 10 is in the cage. In the present invention, write protection of the EEPROM 3b in the SFP optical transceiver 10 is performed by using the MOD_DEF (0) signal connected to the gate circuit 4 built in the SFP optical transceiver 10. The signal line corresponding to the MOD_DEF (0) signal is used to allow the SFP optical transceiver 10 to be detachably inserted and removed while the system device 20 side is powered on. That's it.
[0038]
That is, in the SFP optical transceiver 10, the WP terminal of the EEPROM 3b is connected to MOD_DEF (0) via the gate circuit 4 (resistor 4a and gate element 4b) and grounded via the resistor 4a. In the state where the power is input to the SFP optical transceiver 10 independently of the cage, the input of the newly inserted gate element 4b is grounded via, for example, 100Ω (resistor 4a). The input of the element 4b becomes “Low”, and as a result, the output of the gate element 4b becomes “High”, and the input of the WP terminal also becomes “High”, and write protection is performed.
[0039]
The above state is the same when the SFP optical transceiver 10 is inserted into an appropriate cage and connected to the system device 20. Therefore, as shown in FIG. 5C, since the MOD_DEF (0) line of the system device 20 is pulled up by a resistor 12b of 3.3 kΩ to 4.7 kΩ, for example, a newly installed gate element The input of 4b remains the “Low” level (0V in this example) (that is, the level divided by several kΩ and 100Ω becomes the input). Accordingly, the normal operation of the SFP optical transceiver 10 is not affected at all.
[0040]
Further, when data is written to the EEPROM 3b, as shown in FIG. 5B, the pull-up resistor 12b is changed to, for example, 0Ω, so that the input of the gate element 4b becomes “High” (this example). As a result, the output of the gate element 4b is “Low” (0 V in this example), that is, the input voltage to the WP terminal of the SFP optical transceiver 10 is “Low”. Thereby, data can be written to the EEPROM 3b.
[0041]
On the other hand, in FIG. 5B, when the evaluation jig as shown in FIG. 7 is used, the MOD_DEF (0) signal is pulled up on the circuit board of the evaluation jig corresponding to the system device 20. Because it is not, it is in an open state. Therefore, by connecting this MOD_DEF (0) signal directly to the power supply of the evaluation jig, the input level of the newly installed gate element 4b can be set to “High” (in this example, +3.3 V). As a result, the output of the gate element 4b becomes “Low” (0 V in this example), so that the input voltage to the WP terminal of the SFP optical transceiver 10 becomes “Low”, and data can be written to the EEPROM 3b. . In this way, not only the system device on which the SFP optical transceiver 10 is mounted, it is also possible to set whether or not data can be written to the ROM using an evaluation jig corresponding to the system device.
[0042]
As described above, by setting the input level to the gate element 4b to “High”, the output of the gate element 4b can be set to “Low”, that is, the input to the WP terminal can be set to “Low” (enable). It will be possible to easily rewrite the data for. The gate element 4b newly provided in the SFP type optical transceiver 10 can preferably use a general MOS gate, for example.
[0043]
According to the present invention, when the SFP type optical transceiver is mounted on either the system device or the evaluation jig, the resistance value such as the pull-up resistor on the external device side is changed, so that the ROM in the optical transceiver is changed. Thus, it is possible to easily set whether data can be written.
[0044]
In the above description, the ROM write protection (WP) terminal has been described as having “Low Enable”, but the same thing can be performed for “High Enable”. In this case, a WP signal of “High Enable” can be generated from the MOD_DEF (0) signal simply by connecting the gate elements 4b in two stages in series. In this case, writing to the ROM becomes possible when the output signal to the WP terminal becomes “High” (that is, writing to the ROM when the output signal to the WP terminal becomes “Low”). Is not possible).
[0045]
Also, depending on the SFP type optical transceiver, the MOD_DEF (0) signal is set to “High” in the optical transceiver, the same line of the host system (system equipment side) is “Low”, and the optical transceiver is the host system. It can be assumed that the MOD_DEF (0) line changes from 'Low' to 'High' by being plugged in, but in that case, the number of gate elements in the optical transceiver is set to an odd number, A similar function can be realized by appropriately selecting whether the number is even.
[0046]
That is, the SFP optical transceiver of the present invention outputs 'High' or 'Low' to the WP terminal according to the input level ('High' or 'Low') input from the system equipment side. The correspondence between the input and the output can be arbitrarily set according to the number of gate elements.
[0047]
【The invention's effect】
According to the present invention, by adding a circuit composed of a gate element (inverter) and a resistor inside the optical module, data writing to / from the ROM built in the optical module is easily switched from the external system device side. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of an internal circuit of an SFP optical transceiver according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a terminal arrangement state in an actual SFP type optical module.
FIG. 3 is a block diagram showing an example of an internal circuit for explaining a communication state between an SFP type optical module and a system device.
FIG. 4 is a diagram showing an example of a gate circuit added to an SFP type optical transceiver according to the present invention.
FIG. 5 is a block diagram for explaining a data write enable / disable setting method in the SFP optical transceiver according to the present invention.
FIG. 6 is a perspective view showing an example of the appearance of an optical transceiver based on the MSA standard.
FIG. 7 is a diagram showing an example of a state in which an SFP type optical transceiver is attached to a substrate of an evaluation jig.
FIG. 8 is a perspective view showing a state in which an SFF type optical transceiver or an SFP type optical transceiver is mounted on a system device.
FIG. 9 is a block diagram for explaining a data write enable / disable setting method in a conventional SFP type transceiver;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Light emitting element (Tx) part, 1a ... Semiconductor laser (LD), 2 ... Light receiving element (Rx) part, 2a ... Photodiode (PD), 3 ... Control part, 3a ... CPU, 3b, 40a ... ROM (EEPROM) 4) Gate circuit, 4a, 12b, 53 ... Resistor, 4b ... Gate element (inverter), 10, 40 ... SFP type optical transceiver, 11 ... Ser / Des-IC part, 12, 51 ... PLD / PAL part, 12a, 52 ... Power line, 13 ... Host CPU, 14 ... RAM, 15 ... ROM, 16 ... Data bus, 17, 18 ... Optical fiber, 20, 50 ... System equipment, 30 ... SFF type optical transceiver, 31, 41 ... Optical Receptacle, 42 ... cage, 43 ... substrate.

Claims (9)

An optical module for transmitting and receiving optical signals to and from an optical fiber. The optical module is connectable to a host system device and is used to set a memory for storing data and whether data can be written to the memory. A write protection terminal; and a circuit including a gate element and a resistor. The circuit outputs 'High' or 'Low' to the write protection terminal according to an input level from the host system device. And optical module. The circuit outputs “High” to the write protection terminal when the input level from the host system device is “Low”, and the write when the input level from the host system device is “High”. The optical module according to claim 1, wherein “Low” is output to the protection terminal. A signal line for detachably connecting to the host system device, the signal line being connected to the write protection terminal via the gate element and grounded via the resistor; The optical module according to claim 1, wherein the optical module is characterized in that: 4. The optical module according to claim 1, wherein write enable / disable of data to the memory is set based on a signal of the signal line. 5. 5. The memory according to claim 1, wherein data is set to be writable or not writable when “High” or “Low” is output to the write protection terminal. 6. The optical module as described in. A host system device incorporating an optical module for transmitting / receiving optical signals to / from an optical fiber, wherein the optical module sets a memory for storing data and whether or not data can be written to the memory A write protection terminal and a circuit composed of a gate element and a resistor, and the circuit outputs 'High' or 'Low' to the write protection terminal according to an input level from the host system device. A host system device characterized by that. The circuit outputs “High” to the write protection terminal when the input level from the host system device is “Low”, and the write when the input level from the host system device is “High”. The host system device according to claim 6, wherein 'Low' is output to the protection terminal. A system-side signal line for connecting to a signal line provided in the optical module; and a pull-up resistor for pulling up the signal level of the system-side signal line; 8. The host system device according to claim 6, wherein the input level to the circuit is set to “High” or “Low” by changing the level. 9. The host system device according to claim 6, wherein the optical module is an SFP (Small Form Factor Pluggable) type optical transceiver.

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