JP2004527960A - Dynamic complexity prediction and adjustment of MPEG2 decoding process in media processor - Google Patents

Abstract

A method and system for adjusting the computational load of an MPEG decoder in a video processing system is provided. The video processing system processes header information of a compressed video data stream including a plurality of macroblocks with a motion vector associated therewith. The calculation load of each functional block of the MPEG decoder is adjusted according to a predetermined standard. This avoids substantial computational overhead.

Description

[0001]
[Background of the Invention]
[1. TECHNICAL FIELD OF THE INVENTION]
The present invention relates to video processing of compressed video information, and more particularly, to a method and apparatus for adjusting a calculation load of an MPEG decoder.
[0002]
[2. Description of Related Technology]
Typically, video information is compressed to save storage space and decompressed in a bitstream for display. Therefore, it is highly desirable to decode compressed video information quickly and efficiently in order to provide video images. One of the standard compression methods widely used for compression and decompression of video information is the Moving Pictures Expert Group (MPEG) standard. The MPEG standard is based on the international standard ISO / IEC 11172-1 "Information Technology-Coding of moving pictures and associated audio for digital strategies, three-to-one, first-to-second, first-to-second, first-, second-, third-, third-, and third-thirds. -1. Please refer to the above document for the entire contents.
[0003]
In general, many video systems aim to decode compressed video information quickly and efficiently in order to provide moving picture video. Currently, the computational load required to process one frame is not affected by the decoding algorithm in the MPEG2 decode processor. However, due to the irregular calculation load operation of the MPEG2 decoding process, the peak of the frame calculation load may exceed the maximum load of the CPU of the media processor, which may cause a frame drop or an unexpected result. For this reason, when the technician executes the MPEG2 decoding process in the media processor, a performance margin exceeding the average calculation load for the decoding process by 40 to 50% is provided so that a smooth operation is performed at the peak of the calculation load. You need to choose a processor. Such an implementation is uneconomical and wastes resources, since the peak in computational load does not occur frequently. Without predicting or estimating the complexity of the computational load of frames, slices, and macroblocks, it would be impossible for a video system engineer to adjust the peak of the computational demands of an MPEG bitstream. is there.
[0004]
Therefore, there is a need to provide a complexity prediction algorithm for an MPEG2 decoder running on a media processor.
[0005]
[Summary of the Invention]
The present invention relates to a method and system for improving the decoding efficiency of an MPEG digital video decoder system by scaling the decoding of an encoded digital video signal.
[0006]
The present invention provides a method for adjusting a calculation load of an MPEG decoder in a video processing system. The method according to the invention comprises the step of extracting, in the compressed video data stream, header information of macroblocks whose motion vector is greater than a predetermined threshold. Also, the method according to the invention comprises the step of selectively adjusting the computational load of each functional block of the MPEG decoder according to predetermined criteria. Thereby, substantial computational overhead can be avoided.
[0007]
The present invention relates to a programmable video decoding system, wherein the video decoding system receives and decodes a block-based data packet and outputs a quantized data from the decoded data packet. VLD), extracting header information from the block-based data packet, a complexity estimator configured to execute a video complexity algorithm based on the header information, receiving quantized data from the VLD, An inverse quantizer connected to inverse quantize the quantized data, an inverse discrete cosine transform connected to an output of the inverse quantizer to transform the inversely quantized data from a frequency domain to a spatial domain An apparatus (IDCT) for receiving motion vector data from the quantized data and generating a reference signal As configured motion compensator (MC), and receives from the reference signal and the IDCT spatial domain data, and an adder for forming a motion-compensated video.
[0008]
A more complete understanding of the method and system according to the present invention may be made by reference to the following detailed description in conjunction with the accompanying drawings.
[0009]
[Detailed description of embodiments]
In the following description, for purposes of explanation and not limitation, specific architecture, interfaces, techniques, etc., are provided for a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these details. For simplicity, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
[0010]
FIG. 1 shows the main components of an MPEG video decoder 10 capable of restoring decoded video samples according to an embodiment of the present invention. Here, the compression of the input data is executed before the input to the decoder 10. The compression of the video data is performed by various known methods such as deletion of information that cannot be sensed by the human naked eye, for example, in accordance with the standards in the MPEG2 encoding process. MPEG2 is a second generation compression standard that can encode video programs at 6 Mbits / sec and packetize a large number of 6 Mbits / sec channel streams into a single, faster signal transfer stream. The video element is converted from spatial information into frequency domain information to be processed.
[0011]
The video information includes three types of frames defined by the MPEG standard, namely, intra-frame coding (I frame), forward prediction coding (P frame), and bidirectional prediction coding (B frame). . The I frame or actual video reference frame is periodically encoded, for example, one reference frame out of every 15 frames. The prediction is generated from the synthesis of a video frame located in the forward direction by a specific number of frames and before the next reference frame, that is, a P frame. The B frame is predicted between the I frame and the predicted P frame or by interpolating (averaging) a macroblock of a past reference frame with a macroblock of a future reference frame. Also, a motion vector that specifies the relative position of the macroblock in the reference frame with respect to the macroblock in the current frame is encoded.
[0012]
The frame is encoded using a discrete cosine transform (DCT) encoding scheme. In this coding scheme, the coefficients are coded as the amplitude of a particular cosine basis function. The DCT coefficients are quantized and further encoded using variable length coding. Variable length coding (VLC) 12 is a statistical coding technique that assigns codewords to values to be coded. A short code word is assigned to a value with a high appearance frequency, and a long code word is assigned to a value with a low appearance frequency. In general, short code words with a high frequency of occurrence will occupy a larger number, and thus the code sequence will be shorter than the original data.
[0013]
Thus, upon receiving a coded frame that has been compressed as described above, the decoder 10 performs the motion compensation with the motion vector applied to the corresponding macroblock of the past reference frame, thereby obtaining the macroblock of the current P frame. To decode. The decoder 10 also decodes the macroblock of the B frame by performing motion compensation using a motion vector applied to each of the past and future reference frames. Motion compensation is one of the most computationally intensive methods of many video decompression methods. When pixels change between video frames, this change is often due to a predictable camera or subject movement. Thus, macroblocks of pixels in one frame can be obtained by transforming macroblocks of pixels in previous or subsequent frames. This conversion amount is called a motion vector. Since an I-frame is encoded as a single image without referring to past or future frames, motion processing is not required for I-frame decoding.
[0014]
When the video system cannot handle the computational load required for the decompression, often the entire frame is dropped. This phenomenon is observed as a temporary freeze of the video during video playback, after which the video becomes discontinuous or rattles (jerkiness). As a countermeasure, the embodiment shown in FIG. 1 provides complexity estimation to reduce the processing requirements of the decompression method while maintaining the quality of the reproduced video.
[0015]
Referring to FIG. 1, an MPEG video decoder 10 for scaling a decoding process according to the present invention includes a variable length decoder (VLC) 12, an inverse scanning / quantization circuit 14, a scalable switch 15, an inverse discrete cosine transform ( IDCT) circuit 16, adder 18, frame buffer 20, complexity evaluation device 22, and motion compensation module 24. In the operating mode, the decoder 10 receives a stream of compressed video information, which is provided to a VLC decoder 12. The VLC decoder 12 decodes the variable length coded portion of the compressed signal and supplies the decoded signal to the reverse scanning (or zigzag) / quantization circuit 14 as a variable length decoded signal. The reverse scanning (or zigzag) / quantization circuit 14 decodes this variable length decode signal and outputs a zigzag decode signal. The inverse zigzag quantization process compensates for the fact that the compressed video signal is compressed in a zig-zag run-length code format. This zigzag decode signal is supplied to the IDCT circuit 16. The IDCT circuit 16 performs an inverse discrete cosine transform on the zigzag decoded video signal for each block, and outputs a decompressed pixel value or a decompression error term. The decompressed pixel value is supplied to the adder 18.
[0016]
On the other hand, the motion compensation module 24 receives the motion information and supplies a motion compensation pixel to the adder 18 for each macroblock. More specifically, the pixels of the past image are converted using the forward motion vector, and the pixels of the future image are converted using the backward motion vector. This information is then compensated for by the decompression error term provided by the inverse DCT circuit 16. The motion compensation circuit 24 accesses past image information and future image information from the frame buffer 20. Thereafter, the past image information is subjected to forward motion compensation by the motion compensation circuit 24, and is output as a forward motion compensation pixel macroblock. The future image information is subjected to backward motion compensation by the motion compensation circuit 24, and is output as a backward motion compensated pixel macroblock. By averaging these two macroblocks, a bidirectional motion compensation macroblock is generated. Next, the adder 18 receives the decompressed video information and the motion compensation pixel until one frame is completed, and supplies the decompressed pixel to the buffer 20. If the block does not belong to the predicted macroblock (for example, if it is an I macroblock), these pixel values are output to the frame buffer 20 as they are. On the other hand, if the macroblock is a predicted macroblock (for example, a B macroblock or a P macroblock), the adder 18 adds a decompression error to the forward motion compensation and the backward motion compensation output from the motion compensation circuit 24 and adds a decompression error to the frame buffer 20. Generate a pixel value to be output to.
[0017]
The configuration and operation of the present embodiment described above is a known technique except that the decoder 10 according to the present invention further includes a complexity estimating device 22. The complexity estimator 22 provided in the decoder 10 according to the present invention can provide an evaluation on the computational load of frames, slices and macroblocks in the decoder 10. Therefore, the complexity estimating apparatus 22 has a function of estimating the calculation load of the current frame, slice, and macroblock before actually executing the MPEG2 decoding block (excluding the VLD operation). Such a prediction allows the configuration of a complexity control mechanism that guarantees a smooth operation of the multimedia system implemented in the media processor. That is, the decoder according to the present invention provides scalability by enabling a trade-off between available computational resources, ie, IDCT 16 and MC 24.
[0018]
FIG. 2 shows the basic operating steps that can estimate and adjust the computation load of the IDCT 16 and MC 24. The present invention utilizes macroblock type information to predict possible computational overhead and adaptively control the computational complexity of IDCT 26 and / or MC 24. As a result, a smaller calculation load is applied to the decoder 10. A measure of complexity is defined by the total number of machine cycles required to execute the software on a particular coprocessor. Therefore, in block 30, the header information of the macroblock is extracted from the input signal to the decoder 10. At block 40, the extracted header information is analyzed to predict the required computational load on IDCT 16 and / or MC 24. Generally, tasks are given to the components of the decoder 10 according to the type of information to be processed. When processing is performed with less tasks and load, scaling the computational load on the IDCT 16 and / or MC 24 reduces the computational load on the decoder.
[0019]
The means for predicting the computational load, supporting dynamic prediction and scaling the decoding process according to the present invention are described in detail. The flowchart of FIG. 3 shows the operation of the embodiment by software of the complexity estimation device. This flowchart is also generally applicable to hardware embodiments.
[0020]
As shown in FIG. 3, in step 100, a stream of compressed video information is received by a decoder 12 according to the present invention. In step 110, the header information of the current macroblock is extracted before performing the MPEG2 decoding operation. The format relating to the type information of the macroblock is shown in FIGS. Upon receiving the header information, at step 120, the complexity estimator 22 determines the performance capabilities of the decoder 12. That is, the performance of the IDCT 16 and the MC 24 is evaluated based on the header information and the available calculation resources of the decoder 10. To estimate the complexity, four parameters are extracted from the VLD header. These four parameters are individually analyzed for variable computational weight assignments as described below.
[0021]
In step 130, a different computation weight (C _type ) is assigned to the inverse DCT 16 depending on the type of macroblock received by the decoder 10. Referring to FIG. 4, if the macroblock type is intra, only the intra-coded macroblock needs to be calculated by IDCT 16 without going through the macroblock type, so the corresponding calculation weight is assigned to zero. If the current macroblock is motion-compensated and coded, the corresponding computations since referencing the previous block and copying it to the current block require less computation than motion compensation. Weight is W. If the macroblock is currently motion compensated but not coded, the corresponding calculation weight is 2W. If the current macroblock is interpolated motion compensated and coded, the corresponding weight is 3W since the computational load is higher than in other cases due to the need to extract the forward and backward vectors. .
[0022]
In step 140, the motion vector amount derived from the header information is compared with a preset threshold value to determine whether a different grade (C _mv ) of the performance of the IDCT 16 and the MC 24 is required. In other words, for a large motion vector, the memory access time and memory write time from the previous block to the current block will be longer than for the short motion vector. Therefore, if greater than the threshold the motion vector amount, computational load corresponds to W _1, otherwise, the computational load is assigned zero. This results in significant computational resource savings by providing the IDCT 16 or MC 24 for macroblocks whose motion vector amount is above a predetermined threshold level and scaling the CPU load of the IDCT 16 and / or MC 24 during optimal performance maintenance. Becomes possible.
[0023]
In step 150, the motion vector count extracted from the header information is examined to determine whether different grades (C _mvc ) of the performance of IDCT 16 and MC ₂₄ are required. Here, in the two-vector MC, different decoding weights are assigned because the decoding algorithm needs to access two different storage areas instead of the one-vector MC. That is, if the motion vector is a field type vector, its estimated complexity will be higher than that of the frame type vector. This is because the frame type vector count is 1 while the field type vector count is 2. Therefore, calculated weights W ₂ is increased in proportion to the number of counts detected in the header information.
[0024]
In step 160, the number of non-zero DCT coefficients from the header information and the number of blocks in the coded block pattern (CBP) are analyzed to determine whether different grades (C _BN / C _CBP ) of performance of the IDCT 16 and MC 24 are necessary. Is done. That is, depending on the sparseness of the DCT coefficients, the MPEG decoder according to the present invention can minimize the computational load of the IDCT. Therefore, based on the number of non-zero DCT coefficients detected from the header information, the computational load W ₃ is calculated. Further, in proportion to the CBP count, calculation load W ₄ may be utilized. The CBP count indicates the number of encoded blocks.
[0025]
After extracting these parameters from the stream and assigning appropriate weights, the calculation load required for macroblock decoding can be accurately estimated. In step 170, the results of the calculation weights are summed and the average minimum calculation load ( _Cbase ) is added. Thereafter, based on the estimated load (C _est ), the complexity estimator 22 performs the IDCT calculation and / or increases / decreases the motion compensation load. In step 180, depending on the level of performance prediction detected from the macroblock header, if the performance of the processor is determined to be relatively high, the computational load of the IDCT circuit 16 or the motion compensation circuit 24 is relatively low. Set to a higher level. Conversely, if the performance of the processor is determined to be relatively low, the computation load is set to a relatively low level. That is, if the computational load estimated at step 180 based on the cumulative weighting factor corresponds to 120 [megacycles / second] and the available processing power of the decoder 10 is limited to 100 [megacycles / second] , The ratio of the two values (ie, 100/120 = 80%) is used as a scale factor for the calculation of IDCT 16 and / or the calculation of MC 24. Therefore, for example, only 80% of the CPU load of the IDCT 16 can be used for processing input data to the decoder 10. In this manner, the IDCT 16 and / or the MC 24 are selectively adjusted to reduce the computational load to avoid frame dropping and unexpected results resulting from exceeding the maximum CPU load of the decoder 10. The amount of scaling of the CPU load of the components of the decoder 10 varies according to a predetermined reference (or weight coefficient) set by the operator and the available processing power of the decoder.
[0026]
As described above, as tasks are loaded into the system and subsequently released from the tasks, the computational load changes dynamically with current system performance fluctuations. Further, it is necessary to add a macroblock calculation estimation at the slice or frame level. Therefore, the same calculation or motion compensation can be realized at the frame or slice level by calculating the overall scale factor of the calculation estimation of the macroblock type information in one frame or one slice.
[0027]
The results of estimating the complexity of the video sequence (Molens.codbitstream) are shown in FIGS. 6 (a) and 6 (b). As shown in the two figures, the upper graph represents the actual TriMedia (Philips ^™ ) MPEG2 decoder performance and the lower graph represents the estimated load according to the present invention. FIG. 6A shows a comparison between the actual CPU cycle of the decoding process of the Molens sequence in the TriMedia 1300 and the estimated CPU cycle according to the present invention, and FIG. 6B shows the non-DCC (dynamic complexity control) MPEG2 of the Molens sequence. 4 shows a comparison between a CPU cycle of a decoding process and a DCC (dynamic complexity control) decoding process according to the present invention. It was found that there was a correlation coefficient of about 0.97 between them.
[0028]
Thus, a method for selectively performing IDCT calculation or motion compensation in a video decoder has been disclosed. With the disclosed method, the amount of processing required for thawing can be reduced. As a result, the decompression efficiency can be increased without significant deterioration of the final image quality. Also, while preferred embodiments of the present invention have been illustrated and described, various changes and modifications can be made without departing from the scope of the present invention, and components of the present invention are replaced with equivalents. be able to. Accordingly, the present invention is not limited to the embodiments disclosed as the best mode contemplated for their implementation, but includes any embodiment falling within the scope of the appended claims.
[Brief description of the drawings]
[0029]
FIG. 1 illustrates an example processor that adjusts the computational load in decompressing video information.
FIG. 2 is a flowchart showing operation steps in the processor of FIG. 1;
FIG. 3 is a flowchart showing an estimation of a calculation load of a processor according to the present invention.
FIG. 4A shows a format of macroblock type information.
FIG. 4B shows a format of macroblock type information.
FIG. 4C shows a format of macroblock type information.
FIG. 5 shows a table of computational weights assigned to various types of header information according to the present invention.
FIG. 6 (a) shows an actual simulation of the estimation of the complexity of a video sequence according to the invention.
FIG. 6 (b) shows an actual simulation of the estimation of the complexity of a video sequence according to the invention.

Claims (30)

An MPEG decoder for improving decoding efficiency by scaling the decoding of an encoded digital video signal, comprising:
Means for decoding a compressed video data stream comprising a plurality of macroblocks, the means for decoding operative to output quantized data from the decoded data stream;
Means for performing an inverse quantization process on the quantized data;
Means for performing an inverse discrete cosine transform (IDCT) of the output from the means for performing the inverse quantization;
Means for extracting header information from the quantized data from the decoding means and executing a prediction process according to a predetermined criterion;
Means for generating a motion compensation reference value based on the quantized data from the decoding means; and output from the means for executing the IDCT and the means for generating the motion compensation reference value to form a motion compensated image. Means for adding;
An MPEG decoder comprising: 2. The MPEG decoder according to claim 1, further comprising means for storing an output of said adding means. 2. The MPEG decoder according to claim 1, wherein said extracting means executes said prediction processing according to extracted header information of said plurality of macroblocks. 2. The MPEG decoder according to claim 1, wherein the prediction process determines a calculation load of a unit that executes the IDCT and a unit that generates the motion compensation reference value. 2. The MPEG decoder according to claim 1, wherein a calculation load of the MPEG decoder is selectively adjusted by scaling a means for performing the IDCT and a means for generating the motion compensation reference value based on the prediction processing. MPEG decoder. 2. The MPEG decoder according to claim 1, wherein the extracted header information is a macroblock type, a motion vector amount, a motion vector count, a non-zero discrete cosine transform (DCT) from the decoded block-based data packet. An MPEG decoder comprising coefficients and a number of coding block patterns (CBP). 2. The MPEG decoder according to claim 1, wherein the prediction processing is executed using a processing unit and software for controlling an operation of the processing unit. A variable length decoder (VLD) configured to receive and decode a stream of block-based data packets and output quantized data from the decoded data packets;
A complexity estimator configured to extract header information from the block-based data packet and execute a video complexity algorithm based on the extracted header information;
An inverse quantization device connected to receive the quantized data from the variable length decoder and inversely quantize the quantized data;
An inverse discrete cosine transform (IDCT) that receives the inversely quantized data from the inverse quantizer and transforms the inversely quantized data from a frequency domain to a spatial domain;
A motion compensator (MC) configured to receive motion vector data from the quantized data and generate a reference signal; and receive the reference signal and the spatial domain data from the IDCT to form a motion compensated image. Adder;
A programmable video decoding system, comprising: The video decoding system according to claim 8, further comprising a buffer configured to store an output of the adder. 9. The video decoding system according to claim 8, wherein the complexity estimating apparatus executes the video complexity algorithm according to header information of the decoded block-based data packet, and a calculation load of the decoding system is: A system wherein the system is adjusted by scaling the IDCT and the MC based on a video complexity algorithm. The video decoding system according to claim 10, wherein the computational load of the IDCT and the MC is selectively adjusted according to the video complexity algorithm. 9. The video decoding system according to claim 8, wherein the extracted header information is a macroblock type, a motion vector amount, a motion vector count, a non-zero discrete cosine transform (DCT) from the decoded block-based data packet. A) a system comprising coefficients and a number of coded block patterns (CBP); The video decoding system according to claim 1, wherein the video complexity algorithm is executed using a processing unit and software for controlling the operation of the processing unit. Encoded data video using an MPEG digital video decoder consisting of a variable length code (VLC) decoder, inverse quantizer (IQ), inverse discrete cosine transform (IDCT), motion compensator (MC) and estimator A method for improving the decoding efficiency of a signal, comprising:
Receiving a compressed video data stream by the VLC decoder and generating decoded data from the compressed video data stream;
Extracting header information from the decoded data;
Calculating a total calculation load (C _est ) of the IDCT and the MC based on the classification of the header information by the estimating device;
Inversely quantizing the decoded data using the inverse quantization device (IQ) to generate inversely quantized decoded data;
Converting the dequantized decoded data from the frequency domain to the spatial domain using the IDCT based on the total calculation load (C _est ), and generating difference data;
Generating reference data of the encoded digital video signal using the MC based on the calculation load; and combining the reference data and the difference data to form a motion-compensated image;
A method characterized by comprising: The method of claim 14, further comprising transmitting the total computational load (C _est ) to the IDCT and the MC. The method of claim 14, wherein calculating the total computational load (C _est ) further comprises:
Determining a first calculation load (C _type ) based on the extracted macroblock of the header information;
Determining a second calculation load (C _mv ) based on the amount of movement of the extracted header information;
Determining a third calculation load (C _mvc ) based on the motion vector amount of the extracted header information;
Determining a fourth computational load (C _BN ) based on a number of non-zero DCT coefficients of the extracted header information;
Determining a fifth calculation load (C _CBP ) based on the number of coded block patterns (CBP) of the extracted header information; and determining the first, second, third, fourth and fifth calculation loads. Combining the average computational load (C _base ) to generate the total computational load (C _est );
A method characterized by comprising: 17. The method of claim 16, wherein determining the first computational load ( _Ctype ) further comprises:
Setting C _type = 0 if the extracted header information gives a set of intra-coded coefficients;
When the extracted header information provides a set of coding coefficients and non-motion compensation coefficients, setting C _type = W;
If the extracted header information provides a set of motion compensation coefficients and uncoded coefficients, C _type = 2W; and if the extracted header information provides a set of motion compensation coefficients and coded coefficients, Steps for setting C _type = 3W;
A method characterized by comprising: 17. The method of claim 16, wherein the step of determining the second computational load ( _Cmv ) further comprises: if the extracted header information provides a motion vector amount greater than a predetermined threshold, _Cmv = W. A method comprising: setting ₁ ; otherwise, setting C _mv = 0. _17. The method of claim 16, wherein the step of determining the third computational load ( _Cmvc ) further comprises: if the extracted header information provides the motion vector count (MV-Count), _Cmvc = A method comprising the step of: W ₂ × MV-Count. And 17. The method of claim 16, determining the fourth calculation load (C _BN) further, if the extracted header information gives the number of blocks _{(BN), C BN = W} 3 × BN A method comprising the steps of: 17. The method of claim 16, wherein the step of determining a fifth computational load (C _CBP ) further comprises: if the extracted header information provides the non-zero coefficient, C _CBP = W ₄ × (N The number of zero coefficients). Encoded data using an MPEG digital video decoding system consisting of a variable length code (VLC) decoder, inverse quantizer (IQ), inverse discrete cosine transform (IDCT), motion compensator (MC), and estimator A prediction method for improving decoding efficiency of a video signal, comprising:
Decoding a compressed bitstream including a plurality of macroblocks and obtaining a corresponding decoded macroblock;
Obtaining a header classification criterion from header information of the decoded macroblock;
Estimating a total computation load (C _est ) using the estimator according to header information from the decoded macroblock, and transferring the total computation load (C _est ) to the IDCT and the MC; and Adjusting the computational load of the IDCT and the MC according to the load (C _est );
A method characterized by comprising: 23. The prediction method according to claim 22, further comprising the step of decoding the decoded macroblock according to the total computation load (C _est ) together with the motion vector information received in the compressed bit stream. Method. 23. The prediction method according to claim 22, wherein the header classification criterion is defined by a macroblock type, a motion vector amount, a motion vector count, a non-zero discrete cosine transform (DCT) coefficient, and a coded block pattern (CBP) number. A method characterized by being performed. 23. The prediction method according to claim 22, wherein the step of predicting the total calculation load (C _est ) further comprises:
Determining a first calculation load (C _type ) based on the macroblock in the header information of the decoded macroblock;
Determining a second calculation load (C _mv ) based on a motion amount of header information of the decoded macroblock;
Determining a third calculation load (C _mvc ) based on a motion vector amount of header information of the decoded macroblock;
Determining a fourth computational load (C _BN ) based on a number of non-zero DCT coefficients in header information of the decoded macroblock;
Determining a fifth calculation load (C _CBP ) based on the number of coded block patterns (CBP) in the header information of the decoded macroblock; and the first, second, third, fourth, and fifth calculation loads. the average combined computational load (C _base), to generate the total computational load (C _est) step;
A method characterized by comprising: 26. The prediction method according to claim 25, wherein the step of determining the first computational load (C _type ) further comprises:
Setting C _type = 0 if the header information of the decoded macroblock gives a set of intra-coded coefficients;
When the header information of the decoded macroblock gives a set of coding coefficients and non-motion compensation coefficients, setting C _type = W;
If the header information of the decoded macroblock provides a set of motion compensation coefficients and non-coding coefficients, setting C _type = 2W; and the header information of the decoded macroblock provides a set of motion compensation coefficients and coding coefficients. If C _type = 3W;
A method characterized by comprising: A 25. predicting method, wherein the step of determining said second computation load (C _mv) further, if the header information of the decoded macroblock has a great motion vector amount than a predetermined threshold value, C _mv = W ₁ , otherwise C _mv = 0. 26. The prediction method according to claim 25, wherein the step of determining the third calculation load (C _mvc ) further comprises: C if the header information of the decoded macroblock gives the motion vector count (MV-Count). _mvc = W ₂ × MV-Count. 26. The prediction method according to claim 25, wherein the step of determining the fourth calculation load (C _BN ) further comprises: if the header information of the decoded macroblock gives the number of blocks (BN), C _BN = W ₃ A method comprising the steps of: xBN. 26. The prediction method according to claim 25, wherein the step of determining the fifth computational load (C _CBP ) further comprises: if header information of the decoded macroblock gives the non-zero coefficient, C _CBP = W ₄ ×. (The number of non-zero coefficients).

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