JP2004507006A - Compact high-density memory system - Google Patents

Abstract

The present invention provides a small, high-density electronic package for high-speed, high-performance semiconductors such as memory devices. The small high-density electronic package comprises a plurality of modules having high-speed impedance controlled transmission line buses with short interconnections between the modules, and optionally one of the driver line terminations to maintain high electrical performance. A vessel is incorporated. Suitable applications include microprocessor data buses and memory buses, such as RAMBUS and DDR. The module can be formed on a conventional printed circuit card having unpacked or packed memory chips mounted directly on the memory module. With a thermal control structure, the high density module can be maintained within a reliable operating temperature range.

Description

[0001]
(Related patent application)
This application is a U.S. Patent No. 6,172,895 issued to Brown et al., HIGH CAPACITY MEMORY MODULE WITH BUILT-IN HIGH SPEED BUS TERMINATIONS, and December 1999, all of which are incorporated herein by reference. Co-pending U.S. Patent Application Serial No. 09 / 457,776, filed on December 9, 1999, and co-pending U.S. Patent Application No. 09 / 461,065, filed December 14, 1999, and all co-pending applications filed August 24, 2000. U.S. patent applications Ser. Nos. 09 / 645,860, 60 / 227,689, 09 / 645,859, 09 / 645,858, and co-pending U.S. patent application Ser. No. 09 / 772,641.
[0002]
(Field of the Invention)
The present invention relates to high-density miniature electronic packages, and more particularly to high-density electronic packages having an impedance-controlled transmission line bus and optionally incorporating a driver line terminator in the module to maintain high electrical performance. The present invention relates to high-density compact packaging of high-performance high-density memory modules.
[0003]
(Background of the Invention)
The recent trend in electronic package design for use in high-speed electronic systems is the high electrical performance, high density, and high reliability between various circuit devices that form an important part of high-speed electronic systems. Is to provide interconnection. These high-speed electronic systems are computers, telecommunications network devices, handheld "personal digital assistants", medical equipment, or any other electronic device.
[0004]
High reliability for such connections is essential, as potential failures in the end product can cause catastrophic misconnections. It is also very important that the interconnections be as dense as possible while occupying as little area as possible on the printed circuit board and minimizing the effect on the wiring on the printed circuit board. In some cases, such as in laptop computers and handheld devices, it is extremely important that the height of the connectors and auxiliary circuitry be as low as possible.
[0005]
As the density and performance of systems have increased dramatically, so have the specifications for interconnects. One way to prove high electrical performance is to improve signal integrity. Improved signal integrity can be achieved by providing the interconnect with a shield that promotes a closer match of the interconnect to the required system impedance. These requirements, especially in conjunction with the requirement for field isolation, have led to a variety of possible connector solutions.
[0006]
Also, the connections may be reworked at the factory to ensure efficient repair, upgrade and / or replacement of various system components (eg, connectors, cards, chips, boards, modules, etc.). desirable. In some cases, it is even more desirable that such a connection be separable inside the final product and be reconnectable on site. Such a feature is also desirable, for example, to facilitate testing during manufacturing.
[0007]
A land grid array (LGA) is an example of such a connection, where each of two essentially parallel circuit elements to be connected has a plurality of contacts arranged in a linear or two-dimensional array. ing. An array of interconnect elements, known as an interposer, is placed between the two arrays to be connected, providing an electrical connection between the contacts or pads. Even in the case of higher-density interconnects, a three-dimensional package can be created by stacking additional parallel circuit elements and making electrical connections through additional LGA connectors. In each case, there is no inherent retention force as in pin-and-socket interconnections, so that during engagement, each contact member is pressed with the appropriate force to provide the necessary interconnection to the circuit elements. Requires a clamping mechanism that generates the necessary force to reliably form the. Although the LGA interposer has been implemented in many different ways, the most interesting embodiments are those described in the aforementioned co-pending US patent application.
[0008]
For applications such as high-speed memory buses for use in modern high-speed digital computers, highly complex software running on those computers requires a large amount of volatile, constantly increasing buses and faster clock speeds. Sex random access memory (RAM) is required. Extremely short, sharp rising pulses are used to guarantee fast memory cycle times. The electrical drive requirements useful for a very large number of memory devices are much more stringent than in the era when slower memories were used.
[0009]
The maximum operating speed of a memory system is largely determined by the electrical interconnection between the memory controller and the memory elements or bus. As the data transfer rate increases, the signal propagation time through the interconnect cannot be ignored with respect to the signal change time. At high bus speeds, these interconnects behave as transmission line networks. Thus, the response characteristics of such a transmission line network determine the maximum effective speed of the memory bus.
[0010]
In modern small memory packaging technology, the amount of memory physically available on a system depends on the capacity of the memory element (chip) itself, the number of physical electrical connections on each card or module, and the amount of additional memory. It is determined by the amount of space available to support the card. The number of cards or modules that can be daisy chained is also limited by the capacity of the line driver or receiver.
[0011]
In a conventional random access memory system, only one bit can be present on the bus during a given time interval, so the bus speed is determined primarily by the signal setup time of the bus. Have been. As a result, the currently achievable maximum data rate for such a bus in a PC memory system is 266 Mbit / sec. Normally, there is no need for impedance matching terminations, and such conventional RAM devices do not provide impedance matching terminations.
[0012]
At first glance, it appears that some of the devices of US Pat. No. 5,963,464 issued to Dell et al. For STACKABLE MEMORY CARD are similar to devices of various embodiments of the present invention. However, further investigation has shown significant differences. The embodiment of DELL shown in FIGS. 1-3 is a stackable memory card design. Embodiments show stackable memory cards with a connector socket attached to the top surface and a connector pin attached to the bottom surface of each card. An engagement socket is included on the motherboard. While this packaging technique is appropriate when memory bus technology is slow, the electrical discontinuity of the unshielded inductive connector pins is large, which creates significant reflections and electrical noise. I have. An unused socket on the top surface of the top card also acts as an antenna, picking up stray RF. From a reliability / manufacturing point of view, the pin-and-socket approach leaves the possibility of damaging the module, even if one pin or one socket is bent or damaged. In such a case, the card must be reworked or discarded.
[0013]
A RAMBUS®-based memory module has been selected for disclosure, but other high-speed memory modules, such as Double Data Rate (DDR) SDRAM, as well as those requiring high speed and high performance, Although taught by the present invention, a wide variety of electronic packaging structures for microprocessor based, digital signal processor based, and many other applications including telecommunications based applications and subsystems. It will be clear that the principles applied can be applied.
[0014]
In order to realize higher bus speeds and at the same time to enable a larger storage capacity, it is necessary to adopt an impedance control type bus. For example, RAMBUS technology, created by Rambus of Mountain View, California, has memory elements located on up to three RAMBUS Inline Memory Module (RIMM) cards, all interconnected on a motherboard by a high-speed data bus. (Packaged) memory configuration. One or more termination components are located on the motherboard at the physical end of the bus.
[0015]
In operation, the address / data line exiting the driver circuit on the motherboard is connected to the first RIMM card in the memory chain. These same address / data lines must exit the RIMM via a complete second set of connections. This path continues through the second and possibly a third RIMM module before the driver line reaches its end. This memory / bus configuration allows very high speed transit signals to be transferred over a relatively long bus between the memory controller and the data storage elements. These buses allow multiple bits to propagate on each line of the bus simultaneously, thereby providing an access data transfer rate of 800 Mbit / s. Higher bus speeds will be possible in the future.
[0016]
One of the most important features of such a bus is that the effective impedance of the signal propagation path is well controlled to maintain signal fidelity and signal integrity, and that one end of the bus is Is terminated by impedance.
[0017]
In a system employing such a bus, the amplitude of the drive signal is generally much smaller than the amplitude of a conventional digital signal. This is due to limitations on the drive strength (dv / dt) of the device.
[0018]
All of the above factors make reliable operation significantly dependent on controlling the impedance of the interconnect along the bus. Any impedance mismatch along the signal transmission path will degrade the signal and, consequently, cause errors in data transmission. At the same time, maintaining reliable timing between all signal bits and clocks is extremely important for reliable data transmission. Therefore, in such a bus, minimizing the signal-clock delay difference (data-clock skew) is also an important requirement. The factors that contribute to the skew include the factors listed below.
a) Difference in conductor length
b) Deviation from nominal impedance of the printed circuit board and / or board printed circuit traces
c) the number of times the signal has to pass through the connector
d) Length of unshielded part of connector
[0019]
Connector impedance mismatches cause reflections, forward crosstalk, and reverse crosstalk, all of which act as standing waves that contribute to timing jitter and make skew minimization more difficult. The latter is very important.
[0020]
Prior art small memory system designs generally consist of a memory controller, a clock driver, and a bus termination, all mounted on a motherboard with up to three memory slots between the controller and the termination. I have. The data signal must pass through all modules before reaching the termination, and through a total of up to six edge connectors. Due to their design, current edge connectors result in impedance mismatches and crosstalk that degrade signal quality, thereby limiting signal channel performance.
[0021]
Termination of the memory module itself has improved some types of performance. Because there is only one set of connector pins that must be used (i.e., there is no need to have a bus line exiting the terminating module), the additional connector pin capability is increased over a single card or module. It can be dedicated to addressing large amounts of memory. As a result, since two channels of memory can be integrated in the memory package, the bandwidth can be increased and the storage capacity can be doubled. Also, since the required connector pins are essentially reduced by half, the mounting area is saved and more chips can be packaged on the module.
[0022]
The overall length of the bus path is significantly reduced because the physical spacing between the memory and the driver circuits is much closer than previously possible and more memory is placed on a single card. Also, the performance is further improved because the extra passage of the signal passing through the outlet contact is eliminated. In addition, the portion of the bus path between the memory module and the prior art external termination resistor has been eliminated.
[0023]
If all memory modules must be the same module (eg, all unterminated), a separate module can be created for termination only. This case will be described later in the embodiments in the present specification. For this case, or for the case of already disclosed on-module termination, the design of the present invention reduces the complexity and manufacturing cost of the memory module and motherboard design. In the case of a memory system having one to three memory modules, the use of terminated or terminated modules as final modules facilitates achieving maximum system performance.
[0024]
By combining the small memory module according to the present invention, optionally a self-terminating memory module, with innovative land grid array interconnect technology, much higher densities than previously possible are achieved. This allows much more memory to be packaged in height-limited applications. More storage capacity can be placed closer to the line driver / receiver, thereby reducing the path length, especially if the memory module is self-terminated. By providing the thermal management structure, the temperature can be lowered and the reliability can be improved.
[0025]
Accordingly, it is an object of the present invention to provide a small high density memory package.
[0026]
It is an additional object of the present invention to provide a small high density memory package utilizing a novel high density connector technology.
[0027]
It is another object of the present invention to provide a small, high density memory module having an optional bus termination on the memory module itself.
[0028]
Yet another object of the present invention is to provide a small high-density memory package that can effectively reduce the length of the data path, thereby helping to reduce high speed digital computer or similar driver electrical requirements. That is.
[0029]
It is yet another object of the present invention to provide a small high-density memory package that supports both single and double bus channels.
[0030]
(Summary of the Invention)
The present invention provides a small, high-density electronic package for high-speed, high-performance semiconductors such as memory devices. The small high-density electronic package comprises a plurality of modules having high-speed impedance controlled transmission line buses with short interconnections between the modules, and optionally one of the driver line terminations to maintain high electrical performance. A vessel is incorporated. Suitable applications include microprocessor data buses and memory buses, such as RAMBUS and DDR, among others. The module can be formed on a conventional printed circuit card having unpacked or packed memory chips mounted directly on the memory module. Using a memory module with bus terminations mounted directly on the module improves signal quality and integrity, and thus improves system performance. Such a design also eliminates the need for a bus exit connection, thereby allowing the use of free-up connection capability to address additional storage capacity on the module. With a thermal control structure, the high density module can be maintained within a reliable operating temperature range.
[0031]
The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:
[0032]
(Detailed description of preferred embodiments)
In general, the invention is a small, high-density electronic package for high-speed, high-performance semiconductors, such as memory devices made of either bare memory chips or conventional memory chip packages. The small high-density electronic package comprises a plurality of modules having a high-speed impedance controlled transmission line bus with a short LGA interconnect between the module and the motherboard, and optionally one of the modules to maintain high electrical performance. And a driver line terminator is incorporated. With a thermal control structure, the high density module can be maintained within a reliable operating temperature range.
[0033]
Referring first to FIG. 1a, a schematic diagram of a multiple card (two card) memory system 10 according to the prior art is shown. Conventional two-slot and three-slot boards must terminate on the motherboard 12, even if all slots are unused. The signal quality is proportionally degraded by electrically noisy standard card-on-board connectors 22 and 36, which provide a signal path between RIMM cards 24 and 38 and circuitry on motherboard 12.
[0034]
A RAMBUS-based memory subsystem has been selected for disclosure, but requires high-speed and high-performance, as well as other high-speed memory subsystems such as Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). A wide variety of electronic packaging structures for microprocessor-based, digital signal processor-based, and many other applications, including telecommunications-based applications and subsystems, among others It will be apparent that the principles taught by the present invention can be applied.
[0035]
As shown, a portion of the motherboard 12 has the necessary support circuitry to implement a RAMBUS memory system. A master device 16 including a Direct RAMBUS Clock Generator (DRCG) circuit 14 and a Direct RAMBUS ASIC Cell (DRAC) 18 is implemented on the motherboard 12. RAMBUS channel segment 20 connects DRAC 18 to a first connector 22 that is physically connected to motherboard 12. Typically, RAMBUS channel segments 20 are connected by internal printed wiring traces (not shown). First connector 22 typically has a plurality of spring-loaded contacts designed to engage mating contact pads on first RIMM card 24.
[0036]
In the case of the RAMBUS architecture, typically 184 contacts are provided on each memory module. The RAMBUS channel segment 20 enters the first RIMM card 24 at the bus entry area 26 and is connected via a device connection segment 30 to a number of individual memory elements 28 attached to the RIMM card 24. The RAMBUS channel then exits the RIMM card 24 via the RAMBUS channel exit area 32 before returning to the motherboard 12 from the first RIMM card 24. An additional printed wiring trace connects the RAMBUS channel segment 34 to a second connector 36, also on the motherboard 12. The second connector 36 holds a second RIMM card 38.
[0037]
A RAMBUS channel entry portion 40, a series of memory elements 28, a series of device connection segments 42, and a RAMBUS channel exit portion 44 constitute a second RIMM card 38. After passing the printed circuit traces, at the end of the detour bus, the RAMBUS channel segment 46 eventually reaches the termination 48.
[0038]
Terminating components 48 such as resistors, blocking capacitors and / or decoupling capacitors are also provided on the motherboard 12. All RAMBUS channel signals must pass through the two connectors 22 and 36 and traverse the two RIMM cards 24 and 38 before reaching the termination 48. The signal degrades along the path of the RAMBUS channel, especially at the connectors 22 and 36. Also, valuable "mounting area" is expended on the motherboard 12 itself.
[0039]
Typically, the structure of the RIMM cards 24 and 38 is a printed circuit structure, made of a material based on epoxy glass (ie, FR4) and including one or more conductive (ie, signal, power and / or ground) layers. I have. Due to the tight electrical specifications of RAMBUS, signal traces must match the impedance of the system within 10%.
[0040]
The connectors shown in the following FIGS. 1b and 1c are physical representations of the schematic connectors 22 and 36 of FIG. 1a, respectively, vertically and horizontally. Usually, connectors 22 and 36 are the same connector, so only connector 22 is shown in FIGS. 1b and 1c.
[0041]
Referring to FIG. 1b, there is shown an enlarged cross-sectional view of the vertical plated through-hole attach connector and the prior art memory card shown in FIG. 1a. The spring-loaded contacts 23 'of the connector 22' provide an electrical connection between the motherboard 12 and the contact pads 29 on the RIMM card 24. This type of connector 22 'can be used with either plated-through hole mounting or surface mount mounting on a structure like the motherboard 12 (FIG. 1a). The plated through-hole attach type is less commonly used, but is more commonly used. In each case, the spring-loaded contacts 23 'of the connector 22' cause significant electrical discontinuities, especially at today's high bus speeds. This impedance discontinuity has been demonstrated in the form of increased electrical noise and increased delay due to reflections. Also, this vertical connector cannot be used for small applications.
[0042]
Referring now to FIG. 1c, there is shown an enlarged cross-sectional view of the miniature connector and the prior art RIMM card shown in FIG. 1a. Spring-loaded contacts 23 "of connector 22" provide an electrical connection between motherboard 12 and contact pads 29 on RIMM card 24. This type of connector 22 "is mainly surface mount mounted to a structure such as the motherboard 12 (FIG. 1a). Again, the spring-loaded contacts 23", especially at today's high bus speeds. Creating significant electrical discontinuities. This horizontal connector 22 "actually has a very low profile, which allows it to be used in small applications, but for multi-card applications, it requires a large amount of motherboard and footprint. A two-level stacked version is available, but the connection to the spring contact is longer, which further exacerbates the electrical discontinuity and thus the electrical noise.
[0043]
The particular arrangement and location of the memory elements 28 on the modules 24 and 38 may vary depending on the particular application, and may vary with respect to the prior art and to the invention disclosed below. The number of memory elements is subject to the specifications and limitations of RAMBUS.
[0044]
In accordance with different embodiments of the present invention, three embodiments of a small memory array are disclosed below. The main difference is that the embodiment of FIGS. 2a and 2b shows bus termination 48 on motherboard 12, the embodiment of FIGS. 3a and 3b shows bus termination 48 on final card 82, and FIGS. Is an illustration of the bus termination 48 on the individual termination card 92.
[0045]
Referring to FIG. 2a, there is shown a schematic diagram of a small memory card system 50 according to the present invention. A portion of the motherboard 12 is again provided with the necessary support circuits for implementing a RAMBUS memory system. The DRCG circuit 14 and the master device 16 including the DRAC 18 are implemented on the motherboard 12 in the same manner as the prior art memory card embodiment shown in FIG. 1a and discussed above.
[0046]
RAMBUS channel segment 20 connects DRAC 18 to LGA connector 52. Again, the RAMBUS channel segments 20 are typically connected by printed wiring traces (not shown) on one or more layers (not shown) of the motherboard 12. LGA connector 52 is located between motherboard 12 and first card 54 and provides electrical interconnection therebetween. Typically, LGA connectors 52 and 64 have a plurality of resilient short contact members 53 (FIG. 2b) designed to engage with mating contact pads 51 on motherboard 12 and first card 54. are doing. The same applies to the first card 54 to the second card 66. The housing / carrier 49 of the LGA connectors 52 and 64 preferably has a coefficient of thermal expansion that closely matches the coefficient of thermal expansion (CTE) of the peripheral cards 54 and 66.
[0047]
The structure and composition of contact member 53 is in accordance with the teachings of one of the above-referenced co-pending U.S. patent applications, and is further enhanced electrically and mechanically by the teachings of the other two co-pending U.S. patent applications. Is preferred. Compared to prior art pin-and-socket LGA connectors, connectors 52 and 64 according to the present invention have improved performance, higher density, lower height, and better matching with surrounding structures. It has a CTE. Also, because the force per contact required for connectors 52 and 64 is small, the number of contacts allowed for a given amount of holding force has increased significantly.
[0048]
The RAMBUS channel segment 20 enters the first card 54 at a bus entry area 56 and is connected to a number of individual memory elements 28 attached to the card 54 via a device connection segment 58. The RAMBUS channel then exits the card 54 via the RAMBUS channel exit area 60, and instead of returning to the motherboard 12, the RAMBUS channel segment 62 connects the first card 54 to the second card 54 via the LGA connector 64. It goes directly to 66.
[0049]
The RAMBUS channel entry section 68, the series of memory elements 28, the series of device connection segments 70, and the RAMBUS channel exit section 72 constitute a second card 66. The RAMBUS channel segment 74 travels a short distance back through the other contact members 53 of the connectors 64 and 52 before reaching the termination 48. As in the prior art, termination components 48 such as resistors, blocking capacitors and / or decoupling capacitors are again provided on the motherboard 12.
[0050]
Typically, the structure of the cards 54 and 66 (FIG. 2b) is a printed circuit structure, made of an epoxy glass based material (ie, FR4) and having one or more conductive (ie, signal, power and / or ground) layers. include. Although other materials can be used for various reasons, including electrical performance, wiring and thermal performance, epoxy glass based materials are cost effective and require a motherboard 12 and LGA. It has a CTE that matches the CTE of connectors 52 and 64. Even in this case, the signal specifications must match the impedance of the system within 10% due to the tight electrical specifications of the RAMBUS.
[0051]
3a and 3b, there is shown a schematic diagram of a small memory card system 80 according to the present invention. A portion of the motherboard 12 is again provided with the necessary support circuits for implementing a RAMBUS memory system. The DRCG circuit 14 and the master device 16 including the DRAC 18 are implemented on the motherboard 12 in the same manner as the embodiment shown in FIG. 2a and discussed above. The first card 54 has not been changed. The second card 82 includes a RAMBUS channel entry portion 84, a series of memory elements 28, and a series of device connection segments 86. However, unlike the embodiment of FIGS. 2a and 2b, the termination 48 is mounted directly on the card 82, thus eliminating the need for the exit portion of the RAMBUS channel 72 (FIG. 2a) and the RAMBUS channel segment 74. . Thus, since a complete additional set of contacts is removed, they can be used to address additional storage capacity or the like, and the card 82 can be simplified and reduced in cost. In some cases, the printed circuit board has been reduced from eight layers to six layers. Another advantage of providing terminations 48 on card 82 is that less noise is coupled into motherboard 12, potentially improving overall system performance.
[0052]
4a and 4b, there is shown a schematic diagram of a small memory card system 90 according to the present invention. A portion of the motherboard 12 is again provided with the necessary support circuits for implementing a RAMBUS memory system. The DRCG circuit 14 and the master device 16 including the DRAC 18 are implemented on the motherboard 12 in the same manner as the embodiments shown in FIGS. 2a and 3a and discussed above. However, for best adaptation to certain applications, this embodiment incorporates both of the previous embodiments. While the benefits of on-card termination are well understood and highly desirable for all of the above reasons, it is equally desirable from a manufacturing and procurement standpoint that the memory cards be essentially identical. One way to accomplish this is to start with the two cards 54 and 66 of FIGS. 2 a and 2 b, but the terminations 48 are mounted on separate termination cards 92. The termination card 92 further includes a RAMBUS channel entrance portion 94 and is connected via a connector 96.
[0053]
In the present invention, since there is no inherent retention force as in the case of pin-and-socket interconnections, during engagement, the clamping mechanism causes the respective contact members 53 of the connectors 52, 64 and 96 to have the appropriate Pressing with force produces the necessary force to ensure that the necessary interconnections to the circuit elements are formed. The clamping mechanism does not require any mounting holes in the motherboard 12, provides a controlled and uniform displacement force across the array of contact members 53, avoids CTE mismatch problems, and Preferably, on-site separation is possible to facilitate repairs and upgrades by end users.
[0054]
The means for centering the motherboard 12 with the cards 54, 66 and 82 are not specifically shown in this embodiment, but many possible ways are readily apparent to those skilled in the art. Will.
[0055]
Due to the lack of an effective heat transfer medium from the die or package of the memory element 28 to the atmosphere and the lack of short air channels in the direction of air flow (ie, parallel to the motherboard 12), a small memory card system. The natural cooling efficiencies of 50, 80 and 90 are poor. Natural cooling efficiency is further exacerbated by the relatively large size of today's memory elements 28 and their proximity to other heat generating memory elements 28 in such high density packages. The provision of a thermal management structure (not shown) in the system according to the present invention optimizes heat transfer and radiation, and maximizes circuit density without causing heat build-up that degrades the performance and reliability of the memory device 28. can do.
[0056]
The thermal management structure is intended to dissipate heat from the memory element 28 and can be implemented in many ways. The thermal management structure can simply consist of a layer of a thermally conductive material, such as aluminum, attached or held to the memory element 28 by a heat-enhancing compound or clamp. The thermal management structure can be more complex, with elements such as fins, and more powerful cooling. Other methods include the use of a conformal pouch of liquid heat transfer material, thin heat pipes and thermoelectric devices. Still other methods for solving the thermal problem will be apparent to those skilled in the art.
[0057]
Although three embodiments, each having two memory element cards, have been disclosed for disclosure purposes, parameters such as quantity, specific shape, dimensions, and material of the card, as well as the memory element, may be specified, depending on the specific requirements. It will be apparent to those skilled in the art that the number and packaging can be varied. These various variants are definitely within the scope of the present invention.
[0058]
In the following, the following are benefits and advantages that exist in all embodiments of the present invention.
[0059]
For prior art RIMM cards 24 and 38 (all contacts must be located along a single edge), cards 54, 66 and 82 all have optimally arranged contact pads in a number of ways, Parameters such as contact density, wiring properties, reliability, electrical and mechanical performance can be enhanced. By optimally arranging the contact pads, the motherboard 12 can be optimized.
[0060]
An example of how the present invention provides a way to optimize the electrical properties of the signal connections on cards 54, 66 and 82 over the prior art (FIG. 5a) is seen below through FIG. 5b. be able to. FIG. 5a shows a typical wiring of a memory element 28 to contact pads 29 on RIMM cards 24 and 38. Since all signals enter and exit the RIMM cards 22 and 36 through the same edge 31, the length of the signal connection 25 for connection of the memory element 28 to the device contact pad 27 must be at least the length of the memory element 28. Varies depending on the length "L" of. This results in a difference in the delay times, and noise is coupled into each of the signal connections. In the case of the present invention (FIG. 5b), the judicious placement of the contact pads 55 on the cards 54, 66 and 82 allows the length to be minimized and equal so that all signal connections on the cards 54, 66 and 82 57 electrical performance is optimized.
[0061]
An additional benefit of the optimization method shown in FIG. 5b is that the amount of mounting area saved is significant. In some cases, the size of cards 54, 66 and 82 (FIGS. 2b and 3b) can be reduced and / or complexity can be reduced. Also, in some cases, additional footprint may be used to improve the electrical performance of the small memory card systems 50, 80 and 90 (FIGS. 2b, 3b and 4b). In one embodiment, the electrical performance of critical nets, such as clock lines, can be improved by separating / isolating these nets / lines from noisy nets.
[0062]
The signal degrades along the path of all RAMBUS channels, especially at the connector. It can be seen that for the conventional RAMBUS-based memory subsystem shown in FIGS. 1a to 1c, the total bus path length and therefore the total delay time of the memory subsystem according to the invention is significantly reduced. As the bus length is reduced, whatever the requirements, the driver requirements for the devices on the bus are reduced, thereby reducing costs and increasing reliability.
[0063]
In general, higher memory access speeds can be obtained by improving the quality of the RAMBUS channel (ie, reducing its length, channel delay, crosstalk, etc.). By reducing the path length and eliminating the connector between the memory card and the termination, electrical integrity is significantly improved. In one embodiment, prior art connectors 22 'and 22 "have a 0.150 inch length of electrically unshielded spring-loaded contacts 23' and 23", while in the present case, The length of the contact member 53 of the connectors 52 and 64 is only 0.060 inches. Electrical contact is minimized when the contact members 53 are packaged in a shielded housing, as taught in one of the co-pending US patent applications referenced above. For signals traversing from the first card 54 to the second card 66, 82 in the present invention, two long, unshielded, electrically noisy connectors 22 and 36 and the RAMBUS channel segment 34 (FIG. Signal degradation on passing 1a) has been eliminated, again simplifying the wiring of the motherboard 12 and / or reducing costs.
[0064]
Eliminating and shortening the connectors improves electromagnetic interference (EMI) susceptibility and reduces radiated radio frequency (RF) emissions from the motherboard 12 and cards 54, 66 and 82.
[0065]
For prior art circuit RIMM cards 24 and 38 (FIGS. 1a and 1b) where only a certain number (eg 8 or 16) of memory elements 28 are allowed, according to the invention another division of the memory elements 28 is provided. By allowing, all of the available mounting area on cards 54, 66 and 82, which cannot otherwise be utilized, can be fully utilized to maximize density.
[0066]
Other modifications and changes that may be made to adapt to particular operating requirements and circumstances will be apparent to those skilled in the art, and thus the present invention is limited to the embodiments selected for this disclosure. It is intended to cover all modifications and alterations that do not depart from the true spirit and scope of the present invention.
[0067]
Although the present invention has been described above, what is expected to be protected by a patent certificate is described in the appended claims.
[Brief description of the drawings]
FIG. 1a
1 is a schematic diagram illustrating a prior art multi-card memory array having a bus termination on a motherboard.
FIG. 1b
1b is an enlarged cross-sectional view of the vertical plated through-hole attach connector and the prior art memory card shown in FIG. 1a.
FIG. 1c
1b is an enlarged cross-sectional view of the miniature connector and the prior art memory card shown in FIG. 1a.
FIG. 2a
1 is a schematic diagram illustrating a small memory array of a first embodiment of the present invention having a bus termination on a motherboard.
FIG. 2b
FIG. 2b is an enlarged cross-sectional view of the small memory package according to the present invention shown in FIG. 2a.
FIG. 3a
5 is a schematic diagram illustrating a small memory array of a second embodiment of the present invention having a bus termination on a final memory card.
FIG. 3b
FIG. 3b is an enlarged cross-sectional view of the small memory package according to the present invention shown in FIG. 3a.
FIG. 4a
5 is a schematic diagram illustrating a small memory array of a third embodiment of the present invention having a bus termination on a discrete termination card.
FIG. 4b
FIG. 4b is an enlarged cross-sectional view of the small memory package according to the present invention shown in FIG. 4a.
FIG. 5a
FIG. 3 is a diagram showing a memory element and contact pads on a prior art RIMM card, and wiring between the memory element and the contact pads.
FIG. 5b
FIG. 5b illustrates a technique for improving the electrical performance inherent in the disclosed embodiment of the present invention over the prior art shown in FIG. 5a.

Claims (54)

An electronic package for a high-frequency semiconductor device,
a) a plurality of circuit members each having a first surface and a second surface, wherein a plurality of contact pads are disposed on said first surface, at least one of which is for connection to an external data bus; ,
b) a contact operatively connected to at least one of said conductive pads on said first surface of at least one of said circuit members forming an extension of said external data bus, for providing an electrical interconnect; First electrical connection means comprising a member;
c) at least one semiconductor device provided on at least one of said surfaces of said plurality of circuit members and selectively connected to said data bus extension;
d) a plurality of contact pads disposed on at least one second surface of the circuit member, at least one of which further extends the external data bus;
e) clamping means mounted on at least one of said circuit members for pressing said contact member of said first electrical connection means;
f) an electronic package for high frequency semiconductor devices comprising: bus termination means operatively connected to said data bus extension. 2. The electronic package for a high frequency semiconductor device according to claim 1, wherein said external data bus has a characteristic impedance, and an impedance of said bus terminating means substantially matches said characteristic impedance. 2. The electronic package for a high frequency semiconductor device according to claim 1, further comprising a centering means operatively connected to at least one of said circuit members for centering said first electrical connection means. A second conductive member disposed intermediate the two circuit members and operatively connected to at least one conductive pad on the first surface and at least one conductive pad on the at least one second surface of the circuit member; The electronic package for a high-frequency semiconductor device according to claim 1, further comprising two electrical connection means. 5. The electronic package for a high frequency semiconductor device according to claim 4, further comprising a centering means for centering said second electrical connection means operatively connected to at least one of said circuit members. 3. The electronic package for high frequency semiconductor devices according to claim 2, wherein said bus termination means comprises at least one electrical component of a group of a resistor, a capacitor and an inductor. 7. The electronic package for a high-frequency semiconductor device according to claim 6, wherein the resistor comprises a discrete resistor. The electronic package for a high-frequency semiconductor device according to claim 6, wherein the resistor comprises a resistor pack. 7. The electronic package for a high-frequency semiconductor device according to claim 6, wherein the resistor comprises a solid-state resistance device. The electronic package for a high-frequency semiconductor device according to claim 2, wherein the bus terminating means is provided outside the electronic package. 3. The electronic package for a high-frequency semiconductor device according to claim 2, wherein said bus terminating means is provided on one of said circuit members. The electronic package for a high-frequency semiconductor device according to claim 2, further comprising a termination module, wherein the bus termination means is provided on the termination module. 2. The electronic package for a high frequency semiconductor device according to claim 1, wherein said first electrical connection means is a land grid array connector. 14. The electronic package for high frequency semiconductor devices according to claim 13, wherein the land grid array connector is a Superbuton (TM) based connector manufactured by High Connection Density. The electronic package for a high-frequency semiconductor device according to claim 1, wherein at least one of the semiconductor devices is a memory element. 2. The high-frequency semiconductor device according to claim 1, wherein the circuit member includes wiring means for connecting at least one of the contact pads on the first surface to at least one of the contact pads on the second surface. Electronic package for. The electronic package for a high frequency semiconductor device according to claim 1, wherein the circuit member comprises a multilayer printed circuit card. At least one of the semiconductor devices comprises at least one of the group of a bare chip, a thin small outline package (TSOP), a chip scale package (CSP), and a chip on board (COB). Item 2. An electronic package for a high-frequency semiconductor device according to item 1. The electronic package for a high frequency semiconductor device according to claim 1, wherein the plurality of circuit members are substantially parallel to each other. 20. The electronic package for a high frequency semiconductor device according to claim 19, further comprising an external printed circuit structure, wherein the plurality of circuit members are substantially parallel to the external printed circuit structure. The electronic package for a high frequency semiconductor device according to claim 1, further comprising a thermal management structure. 22. The electronic package for a high frequency semiconductor device according to claim 21, wherein the thermal management structure comprises a heat conducting fin in thermal contact with the at least one semiconductor device. The external data bus comprises at least two external data buses, the extension of the external data bus comprises at least two extensions of the two data buses, and the semiconductor device comprises at least one external data bus. The electronic package for high frequency semiconductor devices according to claim 1, comprising two groups of semiconductor devices, each group individually connected to one of the two data bus extensions. The electronic package for a high frequency semiconductor device according to claim 1, wherein the at least one semiconductor device comprises a pattern of contact pads on a first surface of the at least one semiconductor device. At least some of the plurality of contact pads on one surface of the plurality of circuit members are arranged in a pattern substantially the same as the contact pad pattern on the first surface of the at least one semiconductor device. An electronic package for a high-frequency semiconductor device according to claim 24. The electronic package for a high frequency semiconductor device according to claim 25, further comprising an interconnect between the contact pad pattern on the plurality of circuit members and the contact pad pattern on the at least one semiconductor device. 27. The high frequency semiconductor device for a high frequency semiconductor device according to claim 26, wherein the lengths of the interconnects are substantially equal, the lengths are shortened and adjusted for alignment, and the lengths of the interconnects are minimized. Electronic package. 28. The high frequency semiconductor device of claim 27, wherein the propagation delays of the interconnects are substantially equal, the propagation delays are reduced and the propagation delays are adjusted for matching, and the propagation delays of the interconnects are minimized. Electronic package. An electronic package for a high-frequency semiconductor device,
a) a plurality of circuit members each having a first surface and a second surface, wherein a plurality of contact pads are disposed on said first surface, at least one of which is for connection to an external data bus; ,
b) a contact operatively connected to at least one of said conductive pads on said first surface of at least one of said circuit members forming an extension of said external data bus, for providing an electrical interconnect; First electrical connection means comprising a member;
c) a first pattern of contact pads on a first surface of the plurality of circuit members provided on at least one of the surfaces and selectively connected to the data bus extension; At least one semiconductor device comprising:
d) a plurality of contact pads disposed on at least one second surface of the circuit member, at least one of which further extends the external data bus;
e) clamping means mounted on at least one of said circuit members for pressing said contact member of said first electrical connection means;
f) bus terminating means operatively connected to said data bus extension, wherein at least a portion of said plurality of contact pads on one surface of said plurality of circuit members comprises at least a portion of said at least one semiconductor device. An electronic package for a high frequency semiconductor device arranged in a second pattern of substantially the same pattern as the first contact pad pattern on the first surface. At least one of the plurality of circuit members extends from a plurality of engagement pads and the first pattern of contact pads on the at least one semiconductor device to the second pattern of contact pads on the plurality of circuit members. 30. The electronic package for a high frequency semiconductor device according to claim 29, further comprising an interconnect. 31. The high frequency semiconductor device for a high frequency semiconductor device according to claim 30, wherein the lengths of the interconnects are substantially equal, the lengths are shortened and adjusted for alignment, and the lengths of the interconnects are minimized. Electronic package. 32. The high frequency semiconductor device according to claim 31, wherein the propagation delays of the interconnects are substantially equal, the propagation delays are reduced and the propagation delays are adjusted to achieve matching, and the propagation delays of the interconnects are minimized. Electronic package. 30. The electronic package for a high frequency semiconductor device according to claim 29, wherein the external data bus has a characteristic impedance, and an impedance of the bus termination means substantially matches the characteristic impedance. 30. The electronic package for a high frequency semiconductor device according to claim 29, further comprising centering means operatively connected to at least one of said circuit members for centering said first electrical connection means. A second conductive member disposed intermediate the two circuit members and operatively connected to at least one conductive pad on the first surface and at least one conductive pad on the at least one second surface of the circuit member; 30. The electronic package for a high frequency semiconductor device according to claim 29, further comprising two electrical connection means. 36. The electronic package for a high frequency semiconductor device according to claim 35, further comprising a centering means operatively connected to at least one of said circuit members for centering said second electrical connection means. The electronic package for a high frequency semiconductor device according to claim 33, wherein said bus terminating means comprises at least one electrical component of a group of a resistor, a capacitor, and an inductor. 38. The electronic package for a high frequency semiconductor device according to claim 37, wherein said resistor comprises a discrete resistor. 38. The electronic package for a high frequency semiconductor device according to claim 37, wherein the resistor comprises a resistor pack. 38. The electronic package for a high frequency semiconductor device according to claim 37, wherein said resistor comprises a solid state resistance device. The electronic package for a high-frequency semiconductor device according to claim 33, wherein the bus terminating means is provided outside the electronic package. The electronic package for a high frequency semiconductor device according to claim 33, wherein the bus terminating means is provided on one of the circuit members. The electronic package for a high frequency semiconductor device according to claim 33, further comprising a termination module, wherein the bus termination means is provided on the termination module. 30. The electronic package for high frequency semiconductor devices according to claim 29, wherein said first electrical connection means is a land grid array connector. 45. The electronic package for a high frequency semiconductor device according to claim 44, wherein the land grid array connector is a Superbuton (TM) based connector manufactured by High Connection Density. 30. The electronic package for a high frequency semiconductor device according to claim 29, wherein at least one of said semiconductor devices is a memory element. 30. The high-frequency semiconductor device according to claim 29, wherein the circuit member includes wiring means for connecting at least one of the contact pads on the first surface to at least one of the contact pads on the second surface. Electronic package for. 30. The electronic package for a high frequency semiconductor device according to claim 29, wherein said circuit member comprises a multilayer printed circuit card. At least one of the semiconductor devices comprises at least one of the group of a bare chip, a thin small outline package (TSOP), a chip scale package (CSP), and a chip on board (COB). Item 30. An electronic package for a high-frequency semiconductor device according to item 29. 30. The electronic package for a high frequency semiconductor device according to claim 29, wherein the plurality of circuit members are substantially parallel to each other. The electronic package for a high frequency semiconductor device according to claim 50, further comprising an external printed circuit structure, wherein the plurality of circuit members are substantially parallel to the external printed circuit structure. 30. The electronic package for a high frequency semiconductor device according to claim 29, further comprising a thermal management structure. 53. The electronic package for a high frequency semiconductor device according to claim 52, wherein said thermal management structure comprises heat conducting fins in thermal contact with said at least one semiconductor device. The external data bus comprises at least two external data buses, the extension of the external data bus comprises at least two extensions of the two data buses, and the semiconductor device comprises at least one external data bus. 30. The electronic package for high frequency semiconductor devices according to claim 29, comprising two groups of semiconductor devices, each group individually connected to one of said two data bus extensions.