JP2004363351A - Laminated layer type semiconductor device - Google Patents

Laminated layer type semiconductor device Download PDF

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Publication number
JP2004363351A
JP2004363351A JP2003160378A JP2003160378A JP2004363351A JP 2004363351 A JP2004363351 A JP 2004363351A JP 2003160378 A JP2003160378 A JP 2003160378A JP 2003160378 A JP2003160378 A JP 2003160378A JP 2004363351 A JP2004363351 A JP 2004363351A
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Prior art keywords
semiconductor
metal film
semiconductor device
substrate
mounting
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Inventor
Naoki Yuya
直毅 油谷
Hiroshi Fukumoto
宏 福本
Hirofumi Fujioka
弘文 藤岡
Yoshihiro Tomita
至洋 冨田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2003160378A priority Critical patent/JP2004363351A/en
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high density semiconductor device formed by laminating a plurality of semiconductor elements of the same or different size and shape. <P>SOLUTION: The semiconductor device is formed by vertically laminating a plurality of mounting substrates loading semiconductor elements. Each mounting substrate is formed of semiconductor material. A recess is formed at the center of the upper surface of the substrate, a semiconductor element is accommodated and fixed, a through conductor is formed by providing a plurality of through-holes in the thickness direction of the substrate and filling the holes with conductor, one bump electrode of the upper and lower mounting substrates and a metal film at the upper surface of the other mounting substrate opposing to such bump electrode are formed face to face, and a plurality of mounting substrates including semiconductor element are laminated in the vertical direction. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、高集積半導体回路を形成するための半導体素子を搭載する複数の実装基板を用いた半導体装置に関する。
【０００２】
【従来の技術】
従来、複数の半導体素子を重積して構成した半導体装置が知られており、特許文献１には、半導体素子のチップ自体の表面および裏面の互いに対応する位置にパッド電極を設けるとともに上記チップを貫通して表面および裏面のパッド電極の間を接続する導電部を形成し、複数枚のチップを一つのチップの裏面のパッド電極と他のチップの表面のパッド電極が接するように順次積み重ねて、多層に集積化した半導体回路を形成したことが開示されている。
【０００３】
単層の半導体素子を含む半導体装置についてではあるが、表面に凹部が形成された絶縁性の基板と、この基板の表面に、凹部の底面から側面を経て上面まで連続するようにパターン形成された配線層と、基板の凹部内にフリップチップ実装された半導体素子とを有するものが知られている（例えば、特許文献２参照。）。
【０００４】
【特許文献１】
特開昭６１−２２６６０号公報
【特許文献２】
特開２００２−３３４１０号公報
【０００５】
【発明が解決しようとする課題】
特許文献１に記載の半導体装置では、半導体チップにパッド電極を直接形成しているので、積層すべきチップのパッド電極の位置は、全て同じ位置に配置されている。ここで素子チップのサイズ異なると、もはや積層することができなかった。また、半導体素子チップに導電部形成用の貫通孔を形成して、該貫通孔に導電体被覆等を施すので、チップ表面の半導体素子部に不用な熱や応力などがかかることがあり、半導体素子の信頼性が低くなる恐れがあった。さらに、この半導体装置は、半導体素子を積層することはできるが、コンデンサや抵抗器等の受動素子は搭載することができなかった。
【０００６】
そこで、本発明は、チップ寸法の異なる半導体素子であっても、積層配置が可能で、高度に集積化した半導体装置を提供するものである。
また、本発明は、半導体装置の製造工程中に半導体素子にかかる熱や応力を抑えて、信頼性の高い半導体装置を提供するものである。
さらに、本発明は、半導体素子と共に、受動素子や別の能動素子を組み込むことのできる高度に集積化した半導体装置を提供するものである。
【０００７】
【課題を解決するための手段】
本発明の半導体装置は、半導体素子を載置した複数の実装基板を上下に積重ねて構成するが、各実装基板は、半導体から形成し、該基板の上面の中央部に凹部を形成して、半導体素子を収容して固定し、基板の厚さ方向に複数の貫通孔を設けて導体を充填した貫通導電部となし、上下の実装基板の一方のバンプ電極と、対向する他方の実装基板の上面金属膜とが、互いに対合するように形成して、各々半導体素子を備えた複数の実装基板を上下方向に積重ねて、半導体装置とするものである。
【０００８】
本発明の半導体装置は、複数の実装基板に、それぞれバンプ電極と金属膜で形成したパッド電極とを、凹部の周辺部の実装基板の裏面側と表面側とにそれぞれ設けて、バンプ電極とパッド電極とを接続して積層できるように形成したので、実装基板に半導体素子を載置することにより複数の半導体素子を高集積化することができ、チップ寸法の異なる半導体素子であっても、実質的には多層に積層することができる。また、本発明の半導体装置は、半導体素子自体には、貫通孔を形成しないので、半導体素子に不要な応力がかかることがなく、信頼性の高い半導体装置を得ることができる。
【０００９】
本発明の実装基板は、半導体素子を載置した複数の基板を上下に積み重ねて半導体装置を構成するための実装基板であるが、各実装基板は、半導体から形成し、該基板の上面の中央部に凹部を形成して、半導体素子を収容して固定し、基板の厚さ方向に複数の貫通孔を設けて導体を充填して貫通導電部となし、上下の実装基板の一方のバンプ電極と、対向する他方の実装基板の上面金属膜とが、互いに対合するように形成したものである。これら実装基板は、各々半導体素子を備えた複数の実装基板を上下方向に積重ねて、半導体装置とするものである。
【００１０】
【発明の実施の形態】
本実施形態の半導体装置は、半導体から成る実装基板と該基板に固定された半導体素子とから半導体ユニットとし、複数半導体ユニットを積層して構成される。実装基板は、半導体素子を受容する凹部と、厚さ方向に貫通した貫通孔と、が形成された半導体の板状材が利用でき、該板状体の表面に形成された絶縁性被膜と、板状体の貫通孔内に配置された貫通導電部と、板状体の上面側に形成された上面金属膜と、板状体の下面側に形成されたバンプ電極と、から成る。
【００１１】
実装基板の凹部は、その底面部が、好ましくは平坦にされて、半導体素子を載置しやすいようにされている。凹部の深さは、凹部内に受容した半導体素子が実装基板の上面から突出しないように設定されており、半導体ユニットの積層時に、半導体素子と該半導体素子の上側に配置される別体の実装基板の下面とが接触する惧れがない。
【００１２】
凹部は、ドライエッチングや、ウェットエッチングなどの従来のエッチング方法で形成することができる。凹部の形状は、上方向に向かって拡げられているのが、側壁部表面に上部金属膜を形成するには、パターンニング処理が容易になるので、好ましい。凹部形成時のエッチング条件を制御することにより、側壁部が傾斜状や外方向に湾曲した曲面状などの所望の形状寸法に成形することができる。
【００１３】
貫通導電部は、実装基板に形成した貫通孔に充填された導体を含み、基板の表面側と裏面側との間に導電路を形成する。貫通導電部は、実装基板の厚みの大きい凹部の周辺部に形成することができる。この場合は、貫通導電部の下端部に、後述のバンプ電極と接続することにより、重積した実装基板間で共通の導電路として利用することもできる。貫通導電部の上端又は下端には、表面又は裏面の金属膜と接続して、半導体素子の端子に接続することができる。
また、この凹部周辺部は、多数の貫通孔を形成しても基板強度を保持することができるので、半導体装置の信頼性を高くすることができる。
【００１４】
貫通導電部は、実装基板の厚みの小さい凹部の底面部に形成することもできる。底面部の貫通導電部は、凹部内に配置した半導体素子や受動素子の端子と直接に接続する配線に利用することができる。さらに、底面部の貫通孔は、貫通導電部の上端又は下端には、表面又は裏面の金属膜と接続して、半導体素子の端子に接続することができる。底面部に貫通孔を形成する時には貫通させる厚みが少なくて済むので製造時間時を短縮することができ、また、貫通孔に導体を充填することが容易になる。
【００１５】
さらに、貫通導電部は、実装基板の周辺部と、凹部の底面部との両方に配置することもできる。周辺部貫通導電部と底面部貫通導電部とは、対を成すように配置して、周辺部貫通導電部と、底面部貫通導電部に接続した半導体素子ないし受動素子と電気的接続することもできる。
【００１６】
バンプ電極は、実装基板の裏面側に突起電極として形成されて、貫通導電部の下端又は下面金属膜に接続される。バンプ電極は、基板ユニットの積層時に、下側に対向して配置される基板ユニットの上面金属膜のパッド電極と固着されて、ユニット間の導電を可能にする。
【００１７】
上面金属膜は、他の実装基板の上記のバンプ電極と接合するパッド電極としての機能を有し、隣合う実装基板間の電気的接続と機械的接続をはたするものである。さらに、上面金属膜は、適当な幅のストリップとして、半導体素子またはその他の受動素子の端子と、上記の貫通導電部の上端又はバンプ電極とを接続し配置される。
【００１８】
実装基板は、半導体で形成されるので、導電性を有するが、基板の表面と貫通孔の内面とには、電気的短絡や電流のリークを防止するために、絶縁性被膜が形成されている。絶縁性被膜は、基板表面を酸化処理や窒化処理することにより形成することができ、また、基板表面にＣＶＤ法などにより絶縁性材料を成膜して形成することもできる。
【００１９】
実装基板を形成する半導体には、シリコンが好ましく、凹部や貫通孔を精度良く形成することができ、また、熱酸化によって容易に基板表面に絶縁性被膜を形成することができる。さらに、シリコン基板を利用すると、半導体素子と協働する抵抗やコンデンサなどの受動素子を基板内に形成することができ、半導体装置の高集積化を促進することができる。
【００２０】
上面金属膜には、アルミニウム、銅、金、ニッケルなどを利用することができ、スパッタリング、ＣＶＤ法、メッキ法などにより成膜可能である。上面金属膜を所望の形状にパターンニングするために、従来から知られているパターンニング法が利用でき、例えば、写真製版法を用いたエッチングのように基板表面に一様な金属膜を形成した後に不要な部分を除去する方法や、メタルマスクやレジスト膜を用いたリフトオフのように基板の所定の部分にのみ金属膜を形成する方法などが利用できる。
さらに、上面金属膜の表面は、両端部を除いて保護被膜で被覆するのが好ましく、擦過などにより上面金属膜が切断される惧れがない。
【００２１】
バンプ電極は、金やハンダから形成することができる。金バンプを用いた場合は、圧着により半導体ユニットを積層することができ、また、ハンダバンプを用いた場合は、ハンダバンプを一旦溶融させて固着させることにより積層することができる。
【００２２】
貫通導電部を形成するための貫通孔は、エッチングやドリルにより形成することができるが、特に、誘導結合プラズマ式反応性イオンエッチング（ＩＣＰ−ＲＩＥ）などのＲＩＥ法で形成されるのが好ましく、高アスペクト比の孔を形成することができる。
【００２３】
貫通導電部は、貫通孔の内面が絶縁処理されたあと、導体として導電材料を充填するが、この材料には、銅、ニッケル、ハンダ、銀ペーストやハンダペースト等の導電性ペーストなどが利用できる。銅やニッケルは、メッキ法によって貫通孔内部に析出させることができ、ハンダは、溶融状態で貫通孔に充填することができる。また、導電性ペーストは、そのまま貫通孔内部に充填することができる。
【００２４】
貫通導電部は、貫通孔を完全に充填するのが、電気伝導が確実にできるので好ましいが、基板上面と下面とが電気的に接続できれば完全に充填されている必要はなく、例えば、貫通孔の中央部に貫通空隙を有するスルーホールのように未充填部分を有する貫通導電部を形成して、貫通導電部に用いる導電材料の使用量を減らすことができる。
【００２５】
本発明の半導体装置では、凹部に収容配置可能などのような半導体素子でも利用することができ、要求された動作をする半導体装置を形成するために、多種多様な半導体素子を組み合わせることができる。また、半導体素子と協働する受動素子などを組み込むこともできる。
半導体素子や受動素子は、実装基板の凹部内に受容されて、凹部底面部の上面金属膜に接続される。１つの実装基板には、１つ乃至２つ以上の半導体素子や受動素子を載置することが可能であり、もし複数の素子の接続に必要であれば、実装基板の上面に、金属膜から成る追加配線を形成することができる。
【００２６】
半導体ユニットは、半導体素子を固定した後に、凹部をエポキシ樹脂等の絶縁樹脂で封止することができて、湿気による半導体素子の劣化や、半導体ユニットの積層時に半導体素子を誤って損傷することを防止できる。
【００２７】
半導体ユニットは、所定の半導体装置の設計に基づいて積層固定され、半導体装置が形成される。半導体装置は、ケースや半導体装置載置用の基板などに固定されて、外部電源と通電されて使用される。
【００２８】
実施形態１．
この実施形態は、貫通導電部は、実装基板に形成する貫通孔に充填された導体を含み、基板の表面側と裏面側との間に導電路を形成するが、このための貫通孔は、実装基板の厚みの大きい凹部の周辺部に形成している。貫通導電部の下端部には、バンプ電極が形成され、上端部には、金属膜から成るパッド電極を形成することができる。複数の実装基板は、それぞれ、半導体素子を凹部内に固定されて、重積することにより、バンプ電極とパッド電極との接続により、結合され、半導体装置とされる。
【００２９】
この実施形態では、上面金属膜は、実装基板の凹部周辺部から凹部側壁部を横切って凹部底面部まで伸びたストリップ状に形成される。上面金属膜の一端は、凹部の底面部に配置されて半導体素子と接続し、他端は、凹部周辺の実装基板上面に配置されて半導体ユニットの積層に用いられる。また、上面金属膜は、貫通孔の上面開口部を通るように配線されて、貫通孔内に充填された貫通導電部の上端と電気的に接続される。
【００３０】
図１に本発明の１実施例を示すが、この例は、３つの半導体ユニット１ａ、１ｂ、１ｃを積層した半導体装置１である。半導体ユニット１ａは、上面金属膜３、貫通導電部５、下面金属膜４、及びバンプ電極１０を備えた実装基板２４と、半導体素子１１と、から成っている。
【００３１】
実装基板２４は、シリコン板から成形されており、その上面２５の中央部に、断面台形の凹部２が形成されており、凹部２の周辺部２１には、実装基板２４の上面２５から下面２６まで貫通した複数の周辺部貫通孔２２が形成されている。実装基板２４の上面２５、下面２６、および周辺部貫通孔２２の内表面には、酸化ケイ素から成る絶縁性被膜が形成されている。
【００３２】
周辺部貫通孔２２の内部には、銅から成る貫通導電部５が形成されており、その上端と下端とは、実装基板２４の上面２５と下面２６とにそれぞれ達している。
【００３３】
実装基板２４の上面２５には、絶縁性被膜を介して複数の上面金属膜３が形成されている。各上面金属膜３は、ストリップ状にパターンニングされており、その一端８ａがパッド電極として凹部２の周辺部２１に、他端８ｂが凹部２の底面部２７に配置されている。上面金属膜３の中間部は、凹部側壁部である傾斜部９の表面上に形成されている。上面金属膜３は貫通導電部５の上端に接続されている。
【００３４】
実装基板２４の下面２６には、絶縁性被膜を介して複数の下面金属膜３が形成されている。下面金属膜３は、円形、楕円形または矩形にされており、貫通導電部５の下端を覆うように配置されて、貫通導電部５と通電可能にされている。 さらに、各下面金属膜３の下側には、金から成るバンプ電極１０が形成されている。
【００３５】
半導体素子６は、実装基板２４の凹部２に受容されて、半導体素子６の各電極が、半導体ユニット１ａの例ではボールバンプ７を介して各上部金属膜３の他端８ａにそれぞれ接続されている。半導体ユニット１ｂでは、半導体素子１１、１１が２つ組み込まれており、凹部２の底面部２７には、それら２つの半導体素子１１、１１の間を接続するための島状金属膜１９が、さらに形成されている。また、半導体ユニット１ｃでは、半導体素子１２は、上面金属膜３と、金属ワイヤ１３で接続されており、さらに、受動素子１４が、同一の実装基板２４内に組み込まれている。
【００３６】
各半導体ユニット１ａ、１ｂ、１ｃは、実装基板２４の凹部２をエポキシ樹脂により封止されている。
【００３７】
半導体ユニット１ａは、この例では半導体ユニット１ｂの下に積層されており、半導体ユニット１ａの上面金属膜の他端８ｂに、半導体ユニット１ｂのバンプ電極１０が接続されている。さらに、半導体ユニット１ｂの上面金属膜の他端８ｂに、半導体ユニット１ｃのバンプ電極１０が接続されて、本発明の半導体装置１が形成されている。
【００３８】
本発明の半導体装置１は、半導体装置用の基板１８に接続されて、適切に電気接続および配線がなされて、使用される。
【００３９】
本発明の半導体装置１の製造方法を説明する。
実装基板２４は、（１００）面のシリコンウェハから同時に多数個形成される。まず、シリコンウェハの表面に、凹部２の形状に開口部を有するマスキングを形成して、ＫＯＨなどのアルカリ溶液によって、マスキングの開口部を異方エッチングする。形成された凹部２は、底面部が（１００）面の平面で、凹部側壁面９が（１１１）面の傾斜面となり、側壁面９の傾斜の角度は、５４．７度になる。
【００４０】
マスキングを剥離したのち、凹部周辺部２１に、ＩＣＰ−ＲＩＥにより厚さ方向に貫通した貫通孔２２を形成する。
貫通孔２２を形成したシリコンウェハは、熱処理炉に配置されて空気雰囲気中で加熱して酸化処理を行い、表面および貫通孔内面に酸化ケイ素からなる絶縁性被膜を形成する。
【００４１】
次に、貫通孔２２内に無電解メッキ法により銅を析出させて、貫通導電部５を形成する。貫通導電部５は、貫通孔２２を完全に充填しなくてもよく、貫通孔２２中央に連通孔を残したスルーホールであってもよい。
【００４２】
上面金属膜３および下面金属膜４は、シリコンウェハの上面および下面にＣＶＤ法によりアルミニウムからなる金属膜を形成し、さらに、写真製版法により所定の形状にパターンニングすることにより、形成される。上面金属膜３の表面には、さらに、ＣＶＤ法により窒化珪素からなる保護被膜を全面に形成し、その後、上面金属膜３の両端部８ａ、８ｂが露出するように、保護被膜にエッチングにより開口を形成する。
最後に下面金属膜４の下側に金から成るバンプ電極を形成して、シリコンウェハを切り分けて、実装基板２４が形成される。
【００４３】
半導体装置１の製造は、上記の方法で形成された実装基板２４の凹部２に、適切な半導体素子を固定して、上面金属膜３の一端８ａと電気的に接続する。その後、実装基板２４の凹部２を、エポキシ樹脂から成る封止樹脂で充填して、半導体ユニット１ａ、１ｂ、１ｃが形成される。
【００４４】
半導体ユニット１ａ、１ｂ、１ｃは、上面金属膜３の他端８ｂとバンプ電極１０とが対向するように重ねて、加圧して、他端８ｂとバンプ電極１０とを圧着して、半導体装置１が形成される。
【００４５】
実施形態２．
この実施形態は、実装基板に形成する貫通孔を、厚みの小さい凹部の底面部に形成して、貫通導電部にするもので、貫通導電部の上端部が、凹部内に配置する半導体素子や受動素子の端子と直接に接続する配線に利用する。半導体素子や受動素子の別の端子は、表面の周辺部にパッド電極と上面金属膜を介して接続することができる。
【００４６】
この実施形態は、バンプ電極は、実装基板裏面に形成した下面金属膜に接続され、下面金属膜が、上記の貫通導電部の下端部と接続することができる。
上下に隣接する実装基板は、一方のバンプ電極と他方のパッド電極の接合により、一体にして、半導体装置を構成する。
下面金属層は、貫通導電部とバンプ電極との電気的接続を安全かつ確実にすることができ、また、貫通導電部とバンプ電極とを離間して設計する等の設計的自由度を上げることができる。
【００４７】
本発明の半導体装置の別の実施例は、図２に示すように、実装基板２４の貫通孔２３と貫通導電部２０とが、凹部２の底面部２７に形成されている。また、下面金属膜４は、凹部２の周辺部２１に対応する位置に形成されたバンプ電極１０と、凹部２の底面部２７に形成された貫通導電部２０とを接続するので、実施例１とは異なり、ストリップ状に形成される。
【００４８】
この実施例は、実装基板の貫通孔を形成する部分の厚みが薄いので、貫通孔に導体を充填することが容易な反面、薄い部分に開口するので強度が低くなりやすく、貫通孔２３の数が比較的少ない実装基板に適している。
【００４９】
実施形態３．
この実施形態は、実装基板に形成する貫通孔を、厚みの大きい凹部の周辺部と厚みの小さい凹部の底面部との両方に形成し、各貫通孔は、それぞれ貫通導電部が形成される。
【００５０】
この実施形態は、上面金属膜は、実装基板の凹部周辺部と凹部底面部とに分離して形成され、それぞれ周辺部貫通導電部と底部貫通導電部とに接続されている。実施形態１と異なり、凹部の壁面部には、上面金属膜が形成されていない。底部上面金属膜は、凹部の底面部に配置されて半導体素子と接続し、周辺部上面金属膜は、凹部周辺の実装基板上面に配置されてパッド電極として機能し、半導体ユニットの積層に用いられる。
【００５１】
下面金属膜は、周辺部貫通導電部と底部貫通導電部とを実装基板の下面側で接続している。下面金属膜には、バンプ電極が接続されており、半導体ユニット積層時には、下側に対面する半導体ユニットの周辺部上面金属膜と固着して積層する。
【００５２】
本実施形態の半導体装置は、対の貫通導電部と下面金属膜とにより、２つに分離した上面金属膜を通電可能にできるので、パターンニングがしにくい凹部側壁部に上面金属膜が不用になり製造工程を簡便にすることができる。また、本実施例の半導体装置は、上部金属膜が凹部の段差の屈曲部を通らないので、上部金属膜が損傷しにくく、欠陥の少ない半導体装置を得ることができる。
【００５３】
本発明の半導体装置のさらなる実施例は、図３に示すように、貫通孔および貫通導電部が凹部２の周辺部２１と底面部２７との両方に形成されており、また、上面金属膜が凹部２の周辺部２１と底面部２７との両方に分離して形成されている。周辺部貫通導電部５の上端にはパッド電極でもある周辺部上面金属膜３０が、底部貫通導電部２０の上端には底部上面金属膜３１が、それぞれ接続されている。
【００５４】
下面金属膜４は、２つの貫通導電部５、２０の下端と接続可能なようにストリップ状に形成されており、これにより、周辺部上面金属膜３０と低部上面金属膜３１とが導通されるので、実施例１および２と同様の機能を有する実装基板２４および半導体装置１を得ることができる。
【００５５】
【発明の効果】
本発明の半導体装置は、半導体素子を載置できる実装基板を用い、その実装基板を積層可能に形成することにより、異なるチップ寸法の半導体素子を複数積層することが可能になる。これにより、寸法形状や種類の異なる半導体素子を高集積した半導体装置が得られる。また、半導体素子が、必要以上に機械的および熱的な処理を受けないので、欠陥の少ない半導体装置を得ることができる。さらに、本発明の半導体装置では、半導体素子と協働する受動素子等の部品を、半導体装置内部に集積することができる。
【図面の簡単な説明】
【図１】本発明の実施例にかかる半導体装置の断面図である。
【図２】本発明の別の実施例にかかる半導体装置の断面図である。
【図３】本発明のさらに別の実施例にかかる半導体装置の断面図である。
【符号の説明】
１ 半導体装置
１ａ、１ｂ、１ｃ 半導体ユニット
２ 凹部
３ 上面金属膜
４ 下面金属膜
５ 周辺部貫通導電部
８ａ 上面金属膜の一端
８ｂ 上面金属膜の他端
９ 凹部側壁部
１０ バンプ電極
１６ 樹脂
２０ 底部貫通導電部
２２ 周辺部貫通孔
２３ 底部貫通孔
２４ 実装基板
２５ 実装基板の上面
２６ 実装基板の下面
２７ 凹部の底面部
３０ 周辺部上面金属膜
３１ 底部上面金属膜[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device using a plurality of mounting substrates on which semiconductor elements for forming a highly integrated semiconductor circuit are mounted.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor device in which a plurality of semiconductor elements are stacked is known. In Patent Document 1, pad electrodes are provided at positions corresponding to each other on a front surface and a back surface of a chip of a semiconductor element and the chip is mounted. Form a conductive portion that penetrates and connects between the front and back pad electrodes, and sequentially stacks a plurality of chips such that the pad electrode on the back surface of one chip and the pad electrode on the front surface of another chip are in contact with each other, It is disclosed that a semiconductor circuit integrated in multiple layers is formed.
[0003]
Regarding a semiconductor device including a single-layer semiconductor element, an insulating substrate having a concave portion formed on the surface, and a pattern formed on the surface of this substrate so as to be continuous from the bottom surface of the concave portion to the upper surface via the side surface. There is a known device having a wiring layer and a semiconductor element that is flip-chip mounted in a recess of a substrate (for example, see Patent Document 2).
[0004]
[Patent Document 1]
JP-A-61-22660 [Patent Document 2]
JP-A-2002-33410
[Problems to be solved by the invention]
In the semiconductor device described in Patent Literature 1, pad electrodes are directly formed on the semiconductor chip, and therefore, the positions of the pad electrodes of the chips to be stacked are all arranged at the same position. Here, if the element chips differ in size, they could no longer be stacked. Further, since a through hole for forming a conductive portion is formed in the semiconductor element chip and a conductor coating or the like is applied to the through hole, unnecessary heat or stress may be applied to the semiconductor element portion on the chip surface. The reliability of the device may be reduced. Further, in this semiconductor device, semiconductor elements can be stacked, but passive elements such as capacitors and resistors cannot be mounted.
[0006]
Therefore, the present invention provides a highly integrated semiconductor device that can be stacked even if the semiconductor elements have different chip dimensions.
Another object of the present invention is to provide a highly reliable semiconductor device by suppressing heat and stress applied to a semiconductor element during a semiconductor device manufacturing process.
Further, the present invention provides a highly integrated semiconductor device which can incorporate a passive element or another active element together with a semiconductor element.
[0007]
[Means for Solving the Problems]
The semiconductor device of the present invention is configured by vertically stacking a plurality of mounting boards on which semiconductor elements are mounted.Each mounting board is formed from a semiconductor, and a recess is formed at the center of the upper surface of the board. A semiconductor element is accommodated and fixed, a plurality of through holes are provided in the thickness direction of the substrate to form a through conductive portion filled with a conductor, and one of the bump electrodes of the upper and lower mounting substrates and the other of the opposing mounting substrates are formed. A semiconductor device is formed by forming a plurality of mounting substrates each provided with a semiconductor element in an up-down direction by forming an upper surface metal film so as to face each other.
[0008]
In a semiconductor device according to the present invention, a bump electrode and a pad electrode formed of a metal film are provided on a plurality of mounting substrates, respectively, on the rear surface side and the front surface side of the mounting substrate around the concave portion, and the bump electrode and the pad are formed. Since the electrodes are formed so as to be connected and laminated, a plurality of semiconductor elements can be highly integrated by mounting the semiconductor elements on the mounting substrate. Specifically, they can be stacked in multiple layers. Further, in the semiconductor device of the present invention, since a through hole is not formed in the semiconductor element itself, unnecessary stress is not applied to the semiconductor element, and a highly reliable semiconductor device can be obtained.
[0009]
The mounting substrate of the present invention is a mounting substrate for forming a semiconductor device by stacking a plurality of substrates on which semiconductor elements are mounted one above the other, and each mounting substrate is formed from a semiconductor and has a center on the upper surface of the substrate. A recess is formed in the portion, the semiconductor element is accommodated and fixed, a plurality of through holes are provided in the thickness direction of the substrate, and a conductor is filled to form a through conductive portion, and one of the bump electrodes of the upper and lower mounting substrates And the upper surface metal film of the other mounting substrate opposed to each other are formed so as to face each other. In these mounting boards, a plurality of mounting boards each having a semiconductor element are stacked in the vertical direction to form a semiconductor device.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
The semiconductor device according to the present embodiment is configured by stacking a plurality of semiconductor units as a semiconductor unit including a mounting substrate made of a semiconductor and a semiconductor element fixed to the substrate. The mounting substrate, a concave portion for receiving the semiconductor element, a through-hole penetrating in the thickness direction, a semiconductor plate-like material in which is formed, an insulating coating formed on the surface of the plate-like body, It comprises a through conductive portion disposed in a through hole of the plate, an upper metal film formed on the upper surface of the plate, and a bump electrode formed on the lower surface of the plate.
[0011]
The bottom of the concave portion of the mounting substrate is preferably flat so that the semiconductor element can be easily mounted. The depth of the concave portion is set so that the semiconductor element received in the concave portion does not protrude from the upper surface of the mounting substrate. When the semiconductor units are stacked, the semiconductor element and a separate mounting device arranged above the semiconductor element are stacked. There is no risk of contact with the lower surface of the substrate.
[0012]
The recess can be formed by a conventional etching method such as dry etching or wet etching. It is preferable that the shape of the concave portion be widened upward, since patterning processing becomes easy to form the upper metal film on the side wall surface. By controlling the etching conditions at the time of forming the concave portion, the side wall portion can be formed into a desired shape and size such as an inclined shape or a curved surface curved outward.
[0013]
The through conductive portion includes a conductor filled in a through hole formed in the mounting board, and forms a conductive path between the front side and the back side of the board. The penetrating conductive portion can be formed on the periphery of the thick concave portion of the mounting board. In this case, by connecting a lower end portion of the penetrating conductive portion to a bump electrode described later, it can be used as a common conductive path between stacked mounting substrates. The upper end or the lower end of the penetrating conductive portion can be connected to a metal film on the front surface or the back surface to be connected to a terminal of the semiconductor element.
Further, since the peripheral portion of the concave portion can maintain the substrate strength even when a large number of through holes are formed, the reliability of the semiconductor device can be improved.
[0014]
The penetrating conductive portion may be formed on the bottom surface of the concave portion having a small thickness of the mounting board. The penetrating conductive portion on the bottom portion can be used for a wiring directly connected to a terminal of a semiconductor element or a passive element disposed in the recess. Further, the through hole in the bottom portion can be connected to the metal film on the front or back surface at the upper end or lower end of the through conductive portion, and can be connected to the terminal of the semiconductor element. When a through hole is formed in the bottom portion, the thickness of the through hole may be small, so that the manufacturing time can be reduced, and the through hole can be easily filled with a conductor.
[0015]
Furthermore, the penetrating conductive portions can be arranged both on the peripheral portion of the mounting substrate and on the bottom portion of the concave portion. The peripheral penetrating conductive part and the bottom part penetrating conductive part are arranged so as to form a pair, and may be electrically connected to the peripheral penetrating conductive part and the semiconductor element or the passive element connected to the bottom part penetrating conductive part. it can.
[0016]
The bump electrode is formed as a protruding electrode on the back surface side of the mounting substrate, and is connected to the lower end of the through conductive portion or the lower surface metal film. The bump electrode is fixed to the pad electrode of the upper surface metal film of the substrate unit which is disposed to face the lower side when the substrate units are stacked, thereby enabling conduction between the units.
[0017]
The upper surface metal film has a function as a pad electrode to be joined to the above-mentioned bump electrode of another mounting substrate, and establishes electrical connection and mechanical connection between adjacent mounting substrates. Further, the upper surface metal film is disposed as a strip of an appropriate width, connecting the terminal of the semiconductor element or other passive element with the upper end of the above-mentioned through conductive portion or the bump electrode.
[0018]
Since the mounting substrate is formed of a semiconductor, it has conductivity, but an insulating coating is formed on the surface of the substrate and the inner surface of the through-hole in order to prevent an electric short circuit or current leakage. . The insulating film can be formed by oxidizing or nitriding the surface of the substrate, or can be formed by forming an insulating material on the surface of the substrate by a CVD method or the like.
[0019]
The semiconductor forming the mounting substrate is preferably silicon, and a concave portion or a through-hole can be formed with high precision, and an insulating film can be easily formed on the substrate surface by thermal oxidation. Further, when a silicon substrate is used, passive elements such as a resistor and a capacitor cooperating with a semiconductor element can be formed in the substrate, and high integration of a semiconductor device can be promoted.
[0020]
Aluminum, copper, gold, nickel, or the like can be used for the upper surface metal film, and can be formed by sputtering, CVD, plating, or the like. In order to pattern the upper surface metal film into a desired shape, a conventionally known patterning method can be used. For example, a uniform metal film is formed on the substrate surface as in etching using a photoengraving method. A method of removing an unnecessary portion later, a method of forming a metal film only on a predetermined portion of the substrate such as lift-off using a metal mask or a resist film, and the like can be used.
Further, it is preferable that the surface of the upper surface metal film is covered with a protective film except for both end portions, and there is no fear that the upper surface metal film is cut by rubbing or the like.
[0021]
The bump electrode can be formed from gold or solder. When gold bumps are used, the semiconductor units can be stacked by pressure bonding. When solder bumps are used, the semiconductor units can be stacked by melting and fixing the solder bumps once.
[0022]
The through hole for forming the through conductive portion can be formed by etching or drilling, but is particularly preferably formed by RIE such as inductively coupled plasma reactive ion etching (ICP-RIE). High aspect ratio holes can be formed.
[0023]
The through conductive portion is filled with a conductive material as a conductor after the inner surface of the through hole is insulated, and a conductive paste such as copper, nickel, solder, silver paste or solder paste can be used for this material. . Copper or nickel can be deposited inside the through-hole by a plating method, and solder can be filled in the through-hole in a molten state. In addition, the conductive paste can be directly filled in the through holes.
[0024]
It is preferable that the through conductive portion completely fills the through hole, since electric conduction can be surely performed. However, it is not necessary to completely fill the through hole if the upper surface and the lower surface of the substrate can be electrically connected. By forming a penetrating conductive portion having an unfilled portion like a through hole having a penetrating void at the central portion of the substrate, the amount of conductive material used for the penetrating conductive portion can be reduced.
[0025]
In the semiconductor device of the present invention, any semiconductor element that can be accommodated and arranged in the concave portion can be used, and various semiconductor elements can be combined to form a semiconductor device that performs required operation. In addition, a passive element or the like that cooperates with a semiconductor element can be incorporated.
The semiconductor element and the passive element are received in the concave portion of the mounting substrate, and are connected to the upper surface metal film on the bottom portion of the concave portion. One or two or more semiconductor elements and passive elements can be mounted on one mounting board. If necessary for connecting a plurality of elements, a metal film is formed on the upper surface of the mounting board. Can be formed.
[0026]
After fixing the semiconductor element, the concave portion can be sealed with an insulating resin such as an epoxy resin, so that the semiconductor element is not deteriorated due to moisture and the semiconductor element is damaged by mistake when the semiconductor units are stacked. Can be prevented.
[0027]
The semiconductor units are stacked and fixed based on a predetermined design of the semiconductor device, and a semiconductor device is formed. The semiconductor device is used by being fixed to a case, a substrate for mounting the semiconductor device, or the like, and energized with an external power supply.
[0028]
Embodiment 1 FIG.
In this embodiment, the through conductive portion includes a conductor filled in a through hole formed in the mounting substrate, and forms a conductive path between the front surface side and the back surface side of the substrate. It is formed on the periphery of the concave part where the thickness of the mounting board is large. A bump electrode is formed at the lower end of the through conductive portion, and a pad electrode made of a metal film can be formed at the upper end. The plurality of mounting substrates are respectively fixed with semiconductor elements fixed in the recesses, stacked, and connected by connecting the bump electrodes and the pad electrodes to form a semiconductor device.
[0029]
In this embodiment, the upper surface metal film is formed in a strip shape extending from the periphery of the concave portion of the mounting substrate to the bottom surface of the concave portion across the side wall of the concave portion. One end of the upper surface metal film is arranged on the bottom surface of the concave portion and connected to the semiconductor element, and the other end is arranged on the upper surface of the mounting substrate around the concave portion and used for laminating semiconductor units. The upper surface metal film is wired so as to pass through the upper surface opening of the through hole, and is electrically connected to the upper end of the through conductive portion filled in the through hole.
[0030]
FIG. 1 shows an embodiment of the present invention, which is a semiconductor device 1 in which three semiconductor units 1a, 1b, and 1c are stacked. The semiconductor unit 1 a includes a mounting substrate 24 provided with an upper metal film 3, a through conductive portion 5, a lower metal film 4, and a bump electrode 10, and a semiconductor element 11.
[0031]
The mounting substrate 24 is formed of a silicon plate, and has a concave portion 2 having a trapezoidal cross section at the center of the upper surface 25. A plurality of peripheral through holes 22 penetrating therethrough are formed. An insulating film made of silicon oxide is formed on the upper surface 25, the lower surface 26, and the inner surface of the peripheral through hole 22 of the mounting substrate 24.
[0032]
The through conductive portion 5 made of copper is formed inside the peripheral through hole 22, and the upper end and the lower end thereof reach the upper surface 25 and the lower surface 26 of the mounting board 24, respectively.
[0033]
On the upper surface 25 of the mounting substrate 24, a plurality of upper surface metal films 3 are formed via an insulating film. Each upper surface metal film 3 is patterned in a strip shape, and one end 8 a is arranged on the peripheral portion 21 of the concave portion 2 as a pad electrode, and the other end 8 b is arranged on the bottom portion 27 of the concave portion 2. The middle part of the upper surface metal film 3 is formed on the surface of the inclined part 9 which is the side wall part of the concave part. The upper surface metal film 3 is connected to the upper end of the through conductive portion 5.
[0034]
On the lower surface 26 of the mounting substrate 24, a plurality of lower metal films 3 are formed via an insulating film. The lower metal film 3 has a circular, elliptical or rectangular shape, is arranged so as to cover the lower end of the penetrating conductive part 5, and is capable of conducting with the penetrating conductive part 5. Further, a bump electrode 10 made of gold is formed below each lower surface metal film 3.
[0035]
The semiconductor element 6 is received in the recess 2 of the mounting board 24, and each electrode of the semiconductor element 6 is connected to the other end 8a of each upper metal film 3 via a ball bump 7 in the example of the semiconductor unit 1a. I have. In the semiconductor unit 1b, two semiconductor elements 11, 11 are incorporated, and an island-shaped metal film 19 for connecting between the two semiconductor elements 11, 11 is further provided on the bottom surface 27 of the concave portion 2. Is formed. In the semiconductor unit 1c, the semiconductor element 12 is connected to the upper surface metal film 3 by a metal wire 13, and the passive element 14 is incorporated in the same mounting board 24.
[0036]
In each of the semiconductor units 1a, 1b, and 1c, the recess 2 of the mounting board 24 is sealed with epoxy resin.
[0037]
The semiconductor unit 1a is stacked below the semiconductor unit 1b in this example, and the bump electrode 10 of the semiconductor unit 1b is connected to the other end 8b of the upper surface metal film of the semiconductor unit 1a. Furthermore, the bump electrode 10 of the semiconductor unit 1c is connected to the other end 8b of the upper surface metal film of the semiconductor unit 1b, thereby forming the semiconductor device 1 of the present invention.
[0038]
The semiconductor device 1 of the present invention is used after being connected to a substrate 18 for a semiconductor device, appropriately making electrical connection and wiring.
[0039]
A method for manufacturing the semiconductor device 1 of the present invention will be described.
A large number of mounting substrates 24 are simultaneously formed from a (100) plane silicon wafer. First, masking having an opening in the shape of the concave portion 2 is formed on the surface of a silicon wafer, and the masking opening is anisotropically etched with an alkaline solution such as KOH. The formed concave portion 2 has a bottom surface of a plane having a (100) plane, the concave side wall surface 9 has an inclined surface of a (111) plane, and the inclination angle of the side wall surface 9 is 54.7 degrees.
[0040]
After the masking is removed, a through hole 22 penetrating in the thickness direction is formed in the periphery 21 of the concave portion by ICP-RIE.
The silicon wafer having the through-hole 22 formed therein is placed in a heat treatment furnace and heated in an air atmosphere to perform an oxidation treatment, thereby forming an insulating film made of silicon oxide on the surface and the inner surface of the through-hole.
[0041]
Next, copper is deposited in the through holes 22 by electroless plating to form the through conductive portions 5. The through conductive portion 5 does not need to completely fill the through hole 22, and may be a through hole having a communication hole left in the center of the through hole 22.
[0042]
The upper metal film 3 and the lower metal film 4 are formed by forming a metal film made of aluminum on the upper and lower surfaces of a silicon wafer by a CVD method, and then patterning the metal film into a predetermined shape by a photoengraving method. A protective film made of silicon nitride is further formed on the entire surface of the upper surface metal film 3 by a CVD method, and then an opening is formed in the protective film by etching so that both ends 8a and 8b of the upper surface metal film 3 are exposed. To form
Finally, a bump electrode made of gold is formed below the lower metal film 4, and the silicon wafer is cut to form a mounting substrate 24.
[0043]
In manufacturing the semiconductor device 1, an appropriate semiconductor element is fixed in the concave portion 2 of the mounting board 24 formed by the above method, and is electrically connected to one end 8 a of the upper surface metal film 3. Thereafter, the recess 2 of the mounting board 24 is filled with a sealing resin made of an epoxy resin to form the semiconductor units 1a, 1b, and 1c.
[0044]
The semiconductor units 1a, 1b, and 1c are stacked such that the other end 8b of the upper surface metal film 3 and the bump electrode 10 face each other, pressurized, and press-bonded the other end 8b and the bump electrode 10 to form the semiconductor device 1 Is formed.
[0045]
Embodiment 2. FIG.
In this embodiment, a through hole formed in a mounting board is formed in a bottom portion of a concave portion having a small thickness to be a through conductive portion, and an upper end portion of the through conductive portion is a semiconductor element disposed in the concave portion. Used for wiring directly connected to terminals of passive elements. Another terminal of the semiconductor element or the passive element can be connected to a peripheral portion of the surface via a pad electrode and an upper metal film.
[0046]
In this embodiment, the bump electrode is connected to the lower surface metal film formed on the back surface of the mounting board, and the lower surface metal film can be connected to the lower end of the above-described through conductive portion.
The vertically adjacent mounting substrates are integrated to form a semiconductor device by joining one bump electrode and the other pad electrode.
The lower metal layer can secure and ensure electrical connection between the penetrating conductive portion and the bump electrode, and increase design flexibility such as designing the penetrating conductive portion and the bump electrode apart from each other. Can be.
[0047]
In another embodiment of the semiconductor device of the present invention, as shown in FIG. 2, a through hole 23 and a through conductive portion 20 of a mounting board 24 are formed in a bottom portion 27 of the concave portion 2. Further, since the lower surface metal film 4 connects the bump electrode 10 formed at a position corresponding to the peripheral portion 21 of the concave portion 2 and the penetrating conductive portion 20 formed on the bottom portion 27 of the concave portion 2, the first embodiment is performed. Unlike this, it is formed in a strip shape.
[0048]
In this embodiment, since the thickness of the through hole of the mounting substrate is small, it is easy to fill the through hole with a conductor. However, since the opening is formed in the thin portion, the strength tends to be low. Is suitable for a mounting board having a relatively small number.
[0049]
Embodiment 3 FIG.
In this embodiment, the through holes formed in the mounting board are formed in both the peripheral portion of the thick concave portion and the bottom portion of the small thick concave portion, and each through hole is formed with a through conductive portion.
[0050]
In this embodiment, the upper surface metal film is formed separately at the peripheral portion of the concave portion and the bottom portion of the concave portion of the mounting substrate, and is connected to the peripheral portion conductive portion and the bottom portion conductive portion, respectively. Unlike the first embodiment, the upper surface metal film is not formed on the wall surface of the concave portion. The bottom upper surface metal film is disposed on the bottom surface of the concave portion and connects to the semiconductor element, and the peripheral upper surface metal film is disposed on the upper surface of the mounting substrate around the concave portion and functions as a pad electrode, and is used for stacking semiconductor units. .
[0051]
The lower surface metal film connects the peripheral through conductive portion and the bottom through conductive portion on the lower surface side of the mounting board. A bump electrode is connected to the lower metal film, and when the semiconductor units are stacked, they are fixedly stacked with the upper metal film at the peripheral portion of the semiconductor unit facing the lower side.
[0052]
In the semiconductor device of the present embodiment, the upper conductive metal film separated into two can be made conductive by the pair of penetrating conductive portions and the lower metal film, so that the upper metal film is unnecessary on the side wall of the concave portion where patterning is difficult. Therefore, the manufacturing process can be simplified. Further, in the semiconductor device of this embodiment, since the upper metal film does not pass through the bent portion of the step of the concave portion, the semiconductor device with less damage to the upper metal film and less defects can be obtained.
[0053]
In a further embodiment of the semiconductor device of the present invention, as shown in FIG. 3, a through hole and a through conductive portion are formed in both the peripheral portion 21 and the bottom portion 27 of the concave portion 2, and the upper surface metal film is formed. It is formed separately on both the peripheral part 21 and the bottom part 27 of the recess 2. A peripheral upper surface metal film 30 which is also a pad electrode is connected to an upper end of the peripheral through conductive portion 5, and a bottom upper surface metal film 31 is connected to an upper end of the bottom through conductive portion 20.
[0054]
The lower metal film 4 is formed in a strip shape so as to be connectable to the lower ends of the two through conductive portions 5 and 20, whereby the peripheral upper metal film 30 and the lower upper metal film 31 are conducted. Therefore, the mounting board 24 and the semiconductor device 1 having the same functions as those of the first and second embodiments can be obtained.
[0055]
【The invention's effect】
The semiconductor device of the present invention uses a mounting substrate on which a semiconductor element can be mounted, and by forming the mounting substrate in a stackable manner, a plurality of semiconductor elements having different chip dimensions can be stacked. Thus, a semiconductor device in which semiconductor elements having different dimensions, shapes, and types are highly integrated can be obtained. Further, since the semiconductor element is not subjected to unnecessary mechanical and thermal processing, a semiconductor device with few defects can be obtained. Further, in the semiconductor device of the present invention, components such as passive elements cooperating with the semiconductor element can be integrated inside the semiconductor device.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a sectional view of a semiconductor device according to another embodiment of the present invention.
FIG. 3 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 1a, 1b, 1c Semiconductor unit 2 Recess 3 Upper surface metal film 4 Lower surface metal film 5 Peripheral penetration conductive part 8a One end 8b of upper surface metal film The other end 9 of upper surface metal film Through conductive portion 22 Peripheral through hole 23 Bottom through hole 24 Mounting substrate 25 Upper surface of mounting substrate 26 Lower surface of mounting substrate 27 Bottom portion of recess 30 Peripheral upper surface metal film 31 Bottom upper surface metal film

Claims (4)

半導体素子を載置して積層するための複数の半導体基板から成る実装基板と、各実装基板に搭載した半導体素子と、を含む半導体装置であって、
実装基板が、該基板の上面の中央部に形成された凹部と、基板の厚さ方向に貫通した複数の貫通孔に導体を充填して成る貫通導電部と、基板の表面および貫通孔内壁を覆う絶縁性被膜と、該貫通導電部の上端と通電可能に接続した上面金属膜と、実装基板下面に貫通導電部の下端と通電可能に接続して形成されたバンプ電極と、を有し、
半導体素子が、凹部底面部に、上記の上面金属膜又は貫通導電部に導電可能に固定され、
一の基板のバンプ電極が、これに隣接する他の基板の凹部周辺部の金属膜のパッド電極に固着されて成る複数の実装基板を積層した半導体装置。A semiconductor device including: a mounting board composed of a plurality of semiconductor substrates for mounting and stacking semiconductor elements, and a semiconductor element mounted on each mounting board,
The mounting substrate has a recess formed in the center of the upper surface of the substrate, a through conductive portion formed by filling a plurality of through holes penetrating in the thickness direction of the substrate with a conductor, and a surface of the substrate and an inner wall of the through hole. An insulating coating to cover, an upper metal film electrically connected to the upper end of the penetrating conductive portion, and a bump electrode formed to be conductively connected to the lower end of the penetrating conductive portion on the lower surface of the mounting board;
A semiconductor element is conductively fixed to the top metal film or the penetrating conductive portion on the concave bottom portion,
A semiconductor device in which a plurality of mounting substrates are stacked in which a bump electrode of one substrate is fixed to a pad electrode of a metal film around a concave portion of another substrate adjacent thereto. 貫通導電部が、実装基板の凹部の周辺部に形成された請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the through conductive portion is formed in a peripheral portion of the concave portion of the mounting board. 貫通導電部が、実装基板の凹部の底面部に形成された請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the through conductive portion is formed on a bottom surface of the concave portion of the mounting board. 貫通導電部が、凹部底面部に設けた貫通孔に充填された底部貫通導電部と凹部周辺部に設けた周辺部貫通孔に充填された周辺部貫通導電部とを含む請求項１ないし３のいずれかに記載の半導体装置。4. The through conductive part includes a bottom conductive part filled in a through hole provided in a bottom part of the concave part and a peripheral conductive part filled in a peripheral through hole provided in a peripheral part of the concave part. The semiconductor device according to any one of the above.
JP2003160378A 2003-06-05 2003-06-05 Laminated layer type semiconductor device Pending JP2004363351A (en)

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Cited By (6)

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JP2007116015A (en) * 2005-10-24 2007-05-10 Mitsubishi Electric Corp Electronic device
JP2007115789A (en) * 2005-10-19 2007-05-10 Matsushita Electric Ind Co Ltd Laminated semiconductor device and its manufacturing method
JP2007123520A (en) * 2005-10-27 2007-05-17 Matsushita Electric Ind Co Ltd Laminated semiconductor module
JP2008109046A (en) * 2006-10-27 2008-05-08 Shinko Electric Ind Co Ltd Semiconductor package and stacked semiconductor package
JP2011192893A (en) * 2010-03-16 2011-09-29 Zycube:Kk Method for mounting semiconductor device
KR101436034B1 (en) * 2006-11-22 2014-09-01 신꼬오덴기 고교 가부시키가이샤 Electronic component and method for manufacturing the same

Cited By (13)

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Publication number Priority date Publication date Assignee Title
JP4703356B2 (en) * 2005-10-19 2011-06-15 パナソニック株式会社 Multilayer semiconductor device
JP2007115789A (en) * 2005-10-19 2007-05-10 Matsushita Electric Ind Co Ltd Laminated semiconductor device and its manufacturing method
JP2007116015A (en) * 2005-10-24 2007-05-10 Mitsubishi Electric Corp Electronic device
US8159061B2 (en) 2005-10-27 2012-04-17 Panasonic Corporation Stacked semiconductor module
US7667313B2 (en) 2005-10-27 2010-02-23 Panasonic Corporation Stacked semiconductor module
JP4512545B2 (en) * 2005-10-27 2010-07-28 パナソニック株式会社 Multilayer semiconductor module
US8008766B2 (en) 2005-10-27 2011-08-30 Panasonic Corporation Stacked semiconductor module
JP2007123520A (en) * 2005-10-27 2007-05-17 Matsushita Electric Ind Co Ltd Laminated semiconductor module
JP2008109046A (en) * 2006-10-27 2008-05-08 Shinko Electric Ind Co Ltd Semiconductor package and stacked semiconductor package
US8253229B2 (en) 2006-10-27 2012-08-28 Shinko Electric Industries Co., Ltd. Semiconductor package and stacked layer type semiconductor package
KR101412718B1 (en) 2006-10-27 2014-06-27 신꼬오덴기 고교 가부시키가이샤 Semiconductor package and stacked layer type semiconductor package
KR101436034B1 (en) * 2006-11-22 2014-09-01 신꼬오덴기 고교 가부시키가이샤 Electronic component and method for manufacturing the same
JP2011192893A (en) * 2010-03-16 2011-09-29 Zycube:Kk Method for mounting semiconductor device

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