JP2004363198A - Method of producing strained silicon soi substrate - Google Patents

Method of producing strained silicon soi substrate Download PDF

Info

Publication number
JP2004363198A
JP2004363198A JP2003157400A JP2003157400A JP2004363198A JP 2004363198 A JP2004363198 A JP 2004363198A JP 2003157400 A JP2003157400 A JP 2003157400A JP 2003157400 A JP2003157400 A JP 2003157400A JP 2004363198 A JP2004363198 A JP 2004363198A
Authority
JP
Japan
Prior art keywords
film
soi substrate
sige
layer
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003157400A
Other languages
Japanese (ja)
Inventor
Katsumi Kakimoto
勝己 垣本
Masaharu Ninomiya
正晴 二宮
Masahiko Nakamae
正彦 中前
Koji Matsumoto
光二 松本
Hajime Konoue
肇 鴻上
Ichiro Shiono
一郎 塩野
Masanobu Miyao
正信 宮尾
Taizo Sado
泰造 佐道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumitomo Mitsubishi Silicon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Mitsubishi Silicon Corp filed Critical Sumitomo Mitsubishi Silicon Corp
Priority to JP2003157400A priority Critical patent/JP2004363198A/en
Publication of JP2004363198A publication Critical patent/JP2004363198A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Recrystallisation Techniques (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of producing a strained Si-SOI (silicon-on-insulator) substrate having a flat and flawless surface and containing only Si. <P>SOLUTION: The production method is characterised in that, after an amorphous SiGe layer containing Ge at a set concentration and an amorphous silicon thin film are formed sequentially on an SOI substrate, hydrogen ions are injected into the interface between the Box oxide film and an Si layer on the SOI substrate and then heat treatment is performed at least once at a specified temperature in an oxidizing atmosphere, and subsequently, the amorphous SiGe layer and the amorphous silicon layer are melted by heat treatment and the oxide film is removed before a strained silicon film is deposited. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は半導体装置用の基板、特に歪シリコンSOI基板の製造方法に関するものである。
【0002】
【従来の技術】
シリコンMOSデバイスは、スケーリング則に従った微細化や動作電圧の低減を行うことにより、高速化と低消費電力化を両立してきた。
しかし、ゲート長が100nm以下の領域となると、上記の両立が困難となりつつある。この為に、SOI基板及び歪シリコンの導入が検討され、特にSOI基板上に歪シリコンを導入した基板が究極の基板と考えられ、研究が進められている。
【0003】
第1の方法としてSOI基板とSiGeエピ技術との組み合わせが提供されている(例えば、特許文献1参照。)。この特許文献1に示される方法は、既存のSOI基板上にSiGeエピ層を形成して歪緩和を起こし、歪緩和したSiGe膜上にSi膜を形成して歪Siとする方法である。
第2の方法として酸素イオン注入分離法(SIMOX)により埋め込み酸化膜上に歪緩和SiGe層を形成する方法が開示されている(例えば、特許文献2参照。)。
【0004】
第3の方法としてSOI基板上にSiGe膜を形成し、その後に酸化雰囲気の熱処理によりGeを拡散させつつ歪緩和を行う方法が開示されている(例えば、特許文献3参照。)。
第4の方法としてSOI基板上にSiGe膜を形成し、熱処理にSiGe層を溶融し、その後にGeを拡散させつつSiGe層を固化させることにより歪緩和を行う方法がが開示されている(例えば、特許文献4参照。)。
【0005】
【特許文献1】
特開平7−169926号公報
【特許文献2】
特開平9−321307号公報
【特許文献3】
特開2000−243946号公報
【特許文献4】
特開2003−31495号
【0006】
【発明が解決しようとする課題】
本発明の目的は、表面が平坦で欠陥が少ないと同時にSiしか含まない歪Si−SOI基板の製造方法を提供することにある。
【0007】
【課題を解決するための手段】
本発明はSOI基板上に設定した濃度のGeを含むアモロファスSiGe層とアモロファスシリコン薄膜とを順次形成した後に、SOI基板のBox酸化膜とSi層との界面に水素をイオン注入し、酸化雰囲気下で所定の温度と時間で熱処理を1回以上行ない、その後アモルファスSiGe層とアモルファスシリコン層を溶融させる熱処理をし、酸化膜を除去した後に歪シリコンを成膜することを特徴とする歪シリコンSOI基板の製造方法である。
本発明の歪シリコンSOI基板の製造方法においては、水素原子注入条件は、加速電圧はBox酸化膜上のSi、SiGe等のエピタキシャル成長で形成した膜厚の総厚さで選択し、注入量は1×1014〜1×1016atoms/ccとする。
【0008】
注入する元素は水素以外に、ヘリウム、炭素、酸素とする。熱処理の最高温度は、最終のSiGe膜中のGe濃度に応じて固相線より低い温度とする。酸化膜除去後に平坦化処理を行なう。
水素原子注入後の熱処理は最終のSiGe膜中のGe濃度に応じて固相線より低い温度とする。
【0009】
SOI基板のBox酸化膜とSi層との界面に水素をイオン注入することによってその間の原子結合が切れやすくなるために、その後の溶融し単結晶化したSiGe層は十分緩和し、形成された歪シリコン層はSiGe層のGe濃度に応じた十分な歪み量を有することができる。また注入する元素は大きいものであるとSOI基板のシリコン層の結晶性を乱す可能性がある。また同様の理由で、注入量は少ない方が良い。
【0010】
【発明の実施の形態】
以下に本発明の実施の形態を説明する。
まず図1に示すように、シリコン1上にBOX酸化膜2と55nmの厚さのシリコン薄膜3を持つSOI基板上にGe濃度42%のアモルファスSiGe層4を125nm、30nmのアモルファスシリコン層5をCVD装置にて順に形成する。このときの成膜装置として今回はCVD装置を使用したが、特に方法は問わない。その後SOI基板のBOX酸化膜4とシリコン薄膜5の界面に5×1015atoms/ccの水素原子を注入する。このときの水素注入量は1×1014〜1×1016atoms/ccが良い。1×1014以下の注入量であるとラマンピークシフトは小さくSiGe層は十分緩和していないので、1×1014以上の注入量が必要であるが、一方注入量が多すぎるとSOI基板のシリコン薄膜3の結晶性を乱すために注入量はなるべく少ない方が良く、1×1016以下が望ましい。また注入する元素は水素が最も良いが、そのほかヘリウム、炭素、酸素でも同様の効果が得られる。
【0011】
次に図2のように表面に絶縁体6を形成する。これは後の溶融プロセスにて表面からGe成分が蒸発することを避けるためである。絶縁体は表面のアモルファスシリコン5を酸化させるなどして形成しても良い。次にSiGeを溶融させ、さらに単結晶化させるために1210℃にて2時間の熱処理を行なう。溶融後単結晶化するには図3に示すSiGe系の状態図より、熱処理後のGe濃度に応じて固相線より低い温度とする必要がある。図3中の横軸はSiGeのSi含有率(%)、縦軸は温度(℃)を表す。図中に2本ある曲線のうち、上の曲線を液相線といい、これよりも高温側では完全に溶融し、液体状態である。下の曲線を固相線といい、これよりも低温側では固体状態である。二本の曲線に囲まれた領域では部分溶融状態になっている。このようにアモルファスSiGe層4およびアモルファスシリコン層5は単結晶であるシリコン薄膜3とともに、シリコン薄膜3を種結晶として210nmでGe濃度25%のSiGe単結晶7になる。熱処理後のウェハの断面概略図を図4に示す。その後、表面の絶縁膜を除去した。ここで図5に注入量と、その後に熱処理をして、絶縁膜を除去した後のラマンピークシフト量の関係を示す。これはSiGe層がどのくらい緩和しているかを示すものであるが、水素注入を行っていないものについてラマンシフト量は十分でなくSiGe層が十分緩和していないが、おおよそ水素注入量1×1015以上でその後熱処理を110分以上行ったものに関してはGe濃度に対して十分なラマンシフト量が得られ、SiGe層も十分緩和していることが分かる。この後、CVDにてGe濃度25%、50nmのSiGe8、さらに20nmの歪シリコン層9を連続して形成し図6に示すような絶縁膜を下層に持つ歪シリコンウェハとなる。本実施例により作製されたウェハの熱処理後の表面粗さはRMSでおよそ0.5nmと非常に平坦である。さらにCVD前にCMP処理し、CVDにてGe濃度25%、50nmのSiGe8、さらに20nmの歪シリコン層9を連続して形成することによって表面ラフネスは0.3nmまで低減できた。
【0012】
【発明の効果】
本発明による製造方法によって酸化膜上にSiGe層の濃度に応じた十分な歪み量を持った歪シリコンウェハを製造することができる。
【図面の簡単な説明】
【図1】SOI基板上に設定した濃度のGeを含むアモロファスSiGe層とアモロファスシリコン薄膜とを順次形成したときの断面構成図。
【図2】図1の積層体に絶縁体を形成したときの断面構成図。
【図3】SiGe系の状態図。
【図4】熱処理後のウェハの断面概略図。
【図5】注入量と、その後に熱処理をして絶縁膜を除去した後のラマンピークシフト量の関係を示す図。
【図6】絶縁膜を下層に持つ歪シリコンウェハの断面構成図。
【符号の説明】
1…シリコン基板
2…BOX酸化膜
3…シリコン薄膜
4…アモルファスSiGe層
5…アモルファスシリコン層
6…絶縁膜層
7…熱処理後の単結晶SiGe層
8…CVDによる再形成した単結晶SiGe層
9…歪シリコン層
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a substrate for a semiconductor device, in particular, a strained silicon SOI substrate.
[0002]
[Prior art]
Silicon MOS devices have achieved both high speed and low power consumption by reducing the size and operating voltage in accordance with the scaling rule.
However, when the gate length is in the region of 100 nm or less, it is becoming difficult to achieve both of the above. For this reason, the introduction of an SOI substrate and strained silicon has been studied. In particular, a substrate in which strained silicon has been introduced on an SOI substrate is considered to be the ultimate substrate, and research is proceeding.
[0003]
As a first method, a combination of an SOI substrate and a SiGe epi technology is provided (for example, see Patent Document 1). The method disclosed in Patent Document 1 is a method in which a SiGe epilayer is formed on an existing SOI substrate to cause strain relaxation, and a Si film is formed on the strain-relaxed SiGe film to obtain strained Si.
As a second method, a method of forming a strain-relaxed SiGe layer on a buried oxide film by an oxygen ion implantation separation method (SIMOX) is disclosed (for example, see Patent Document 2).
[0004]
As a third method, a method is disclosed in which a SiGe film is formed on an SOI substrate, and then strain is relaxed while diffusing Ge by heat treatment in an oxidizing atmosphere (for example, see Patent Document 3).
As a fourth method, a method is disclosed in which a SiGe film is formed on an SOI substrate, the SiGe layer is melted by heat treatment, and then the SiGe layer is solidified while diffusing Ge, thereby relaxing strain (for example, disclosed). And Patent Document 4.).
[0005]
[Patent Document 1]
JP-A-7-169926 [Patent Document 2]
JP-A-9-321307 [Patent Document 3]
JP 2000-243946 A [Patent Document 4]
JP-A-2003-31495 [0006]
[Problems to be solved by the invention]
An object of the present invention is to provide a method for manufacturing a strained Si-SOI substrate that has a flat surface, few defects, and contains only Si.
[0007]
[Means for Solving the Problems]
According to the present invention, after an Amorphous SiGe layer containing a set concentration of Ge and an Amorphous silicon thin film are sequentially formed on an SOI substrate, hydrogen is ion-implanted into an interface between the Box oxide film and the Si layer of the SOI substrate to form an oxidizing atmosphere. A heat treatment at a predetermined temperature and for a predetermined time under heat, a heat treatment for melting the amorphous SiGe layer and the amorphous silicon layer, and removing an oxide film to form a strained silicon SOI. This is a method for manufacturing a substrate.
In the method for manufacturing a strained silicon SOI substrate according to the present invention, the hydrogen atom implantation condition is such that the acceleration voltage is selected by the total thickness of the film formed by epitaxial growth of Si, SiGe or the like on the Box oxide film, and the implantation amount is 1 × 10 14 to 1 × 10 16 atoms / cc.
[0008]
Elements to be implanted are helium, carbon, and oxygen in addition to hydrogen. The maximum temperature of the heat treatment is lower than the solidus depending on the Ge concentration in the final SiGe film. After removing the oxide film, a flattening process is performed.
The heat treatment after the implantation of the hydrogen atoms is performed at a temperature lower than the solidus depending on the Ge concentration in the final SiGe film.
[0009]
Since hydrogen is easily ion-implanted at the interface between the Box oxide film and the Si layer of the SOI substrate, the atomic bond therebetween is easily broken, and the subsequent melted and single-crystallized SiGe layer is sufficiently relaxed and the formed strain is reduced. The silicon layer can have a sufficient amount of strain according to the Ge concentration of the SiGe layer. Further, if the element to be implanted is large, the crystallinity of the silicon layer of the SOI substrate may be disturbed. For the same reason, it is better that the injection amount is small.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
First, as shown in FIG. 1, an amorphous SiGe layer 4 having a Ge concentration of 42% is 125 nm and an amorphous silicon layer 5 having a thickness of 30 nm is formed on an SOI substrate having a BOX oxide film 2 and a silicon thin film 3 having a thickness of 55 nm on a silicon 1. They are formed sequentially by a CVD apparatus. In this case, a CVD apparatus was used as a film forming apparatus, but the method is not particularly limited. Thereafter, 5 × 10 15 atoms / cc of hydrogen atoms are implanted into the interface between the BOX oxide film 4 and the silicon thin film 5 of the SOI substrate. The hydrogen injection amount at this time is preferably 1 × 10 14 to 1 × 10 16 atoms / cc. When the implantation amount is 1 × 10 14 or less, the Raman peak shift is small and the SiGe layer is not sufficiently relaxed. Therefore, the implantation amount of 1 × 10 14 or more is necessary. In order to disturb the crystallinity of the silicon thin film 3, the injection amount is preferably as small as possible, and is preferably 1 × 10 16 or less. Hydrogen is the best element to be implanted, but helium, carbon, and oxygen also provide the same effect.
[0011]
Next, an insulator 6 is formed on the surface as shown in FIG. This is to prevent the Ge component from evaporating from the surface in the subsequent melting process. The insulator may be formed by oxidizing the amorphous silicon 5 on the surface. Next, heat treatment is performed at 1210 ° C. for 2 hours in order to melt the SiGe and further single-crystallize it. In order to perform single crystallization after melting, it is necessary to set the temperature to be lower than the solidus temperature according to the Ge concentration after the heat treatment according to the SiGe-based phase diagram shown in FIG. The horizontal axis in FIG. 3 represents the Si content (%) of SiGe, and the vertical axis represents the temperature (° C.). Of the two curves in the figure, the upper curve is called a liquidus line, and on a higher temperature side, it completely melts and is in a liquid state. The lower curve is called the solidus line, and it is in a solid state at lower temperatures. The region surrounded by the two curves is in a partially melted state. As described above, the amorphous SiGe layer 4 and the amorphous silicon layer 5 become a single crystal silicon thin film 3 and a SiGe single crystal 7 having a Ge concentration of 25% at 210 nm using the silicon thin film 3 as a seed crystal. FIG. 4 shows a schematic sectional view of the wafer after the heat treatment. After that, the insulating film on the surface was removed. Here, FIG. 5 shows the relationship between the amount of implantation and the amount of Raman peak shift after the insulating film is removed by heat treatment. This indicates how much the SiGe layer is relaxed, but the Raman shift amount is not sufficient for those without hydrogen implantation and the SiGe layer is not sufficiently relaxed, but the hydrogen implantation amount is approximately 1 × 10 15 From the above, it can be seen that for the case where the heat treatment was performed for 110 minutes or more, a sufficient Raman shift with respect to the Ge concentration was obtained, and the SiGe layer was sufficiently relaxed. Thereafter, SiGe 8 having a Ge concentration of 25% and 50 nm and a strained silicon layer 9 having a thickness of 20 nm are successively formed by CVD to obtain a strained silicon wafer having an insulating film as a lower layer as shown in FIG. The surface roughness of the wafer manufactured according to the present embodiment after the heat treatment is very flat, approximately 0.5 nm in RMS. Further, the surface roughness could be reduced to 0.3 nm by performing a CMP treatment before CVD and continuously forming SiGe 8 having a Ge concentration of 25%, 50 nm, and a strained silicon layer 9 having a thickness of 20 nm by CVD.
[0012]
【The invention's effect】
According to the manufacturing method of the present invention, a strained silicon wafer having a sufficient amount of strain according to the concentration of the SiGe layer on the oxide film can be manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional configuration diagram when an Amorphous SiGe layer containing Ge at a set concentration and an Amorphous silicon thin film are sequentially formed on an SOI substrate.
FIG. 2 is a cross-sectional configuration diagram when an insulator is formed on the laminate of FIG.
FIG. 3 is a state diagram of a SiGe system.
FIG. 4 is a schematic cross-sectional view of a wafer after heat treatment.
FIG. 5 is a diagram showing a relationship between an implantation amount and a Raman peak shift amount after a heat treatment is performed to remove an insulating film.
FIG. 6 is a sectional configuration diagram of a strained silicon wafer having an insulating film as a lower layer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... BOX oxide film 3 ... Silicon thin film 4 ... Amorphous SiGe layer 5 ... Amorphous silicon layer 6 ... Insulating film layer 7 ... Single crystal SiGe layer 8 after heat treatment 8 ... Single crystal SiGe layer 9 reformed by CVD ... Strained silicon layer

Claims (6)

SOI基板上に設定した濃度のGeを含むアモロファスSiGe層とアモロファスシリコン薄膜とを順次形成した後に、SOI基板のBox酸化膜とSi層との界面に水素をイオン注入し、酸化雰囲気下で所定の温度と時間で熱処理を1回以上行ない、その後アモルファスSiGe層とアモルファスシリコン層を溶融させる熱処理をし、酸化膜を除去した後に歪シリコンを成膜することを特徴とする歪シリコンSOI基板の製造方法。After an Amorphous SiGe layer containing Ge at a set concentration and an Amorphous silicon thin film are sequentially formed on an SOI substrate, hydrogen is ion-implanted into an interface between the Box oxide film and the Si layer of the SOI substrate, and a predetermined amount is formed under an oxidizing atmosphere. A heat treatment for melting the amorphous SiGe layer and the amorphous silicon layer at least once at a temperature and for a time, and then forming a strained silicon film after removing an oxide film. Method. 水素原子注入条件は、加速電圧はBox酸化膜上のSi、SiGe等のエピタキシャル成長で形成した膜厚の総厚さで選択し、注入量は1×1014〜1×1016atoms/ccとする請求項1記載の歪シリコンSOI基板の製造方法。The hydrogen atom implantation conditions are such that the acceleration voltage is selected based on the total thickness of the film formed by epitaxial growth of Si, SiGe, or the like on the Box oxide film, and the implantation amount is 1 × 10 14 to 1 × 10 16 atoms / cc. A method for manufacturing a strained silicon SOI substrate according to claim 1. 注入する元素は水素以外に、ヘリウム、炭素、酸素とする請求項1又は2記載の製造方法。3. The method according to claim 1, wherein the element to be implanted is helium, carbon, or oxygen in addition to hydrogen. 熱処理の最高温度は、最終のSiGe膜中のGe濃度に応じて固相線より低い温度とする請求項1記載の製造方法。2. The method according to claim 1, wherein the maximum temperature of the heat treatment is lower than the solidus temperature according to the Ge concentration in the final SiGe film. 酸化膜除去後に平坦化処理を行なう請求項1記載の製造方法。2. The method according to claim 1, wherein a flattening process is performed after removing the oxide film. 水素原子注入後の熱処理は最終のSiGe膜中のGe濃度に応じて固相線より低い温度とする請求項1記載の製造方法。2. The method according to claim 1, wherein the heat treatment after the implantation of the hydrogen atoms is performed at a temperature lower than the solidus depending on the Ge concentration in the final SiGe film.
JP2003157400A 2003-06-02 2003-06-02 Method of producing strained silicon soi substrate Pending JP2004363198A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003157400A JP2004363198A (en) 2003-06-02 2003-06-02 Method of producing strained silicon soi substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003157400A JP2004363198A (en) 2003-06-02 2003-06-02 Method of producing strained silicon soi substrate

Publications (1)

Publication Number Publication Date
JP2004363198A true JP2004363198A (en) 2004-12-24

Family

ID=34051112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003157400A Pending JP2004363198A (en) 2003-06-02 2003-06-02 Method of producing strained silicon soi substrate

Country Status (1)

Country Link
JP (1) JP2004363198A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006033292A1 (en) * 2004-09-24 2006-03-30 Shin-Etsu Handotai Co., Ltd. Method for manufacturing semiconductor wafer
JP2006270000A (en) * 2005-03-25 2006-10-05 Sumco Corp PROCESS FOR PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THAT METHOD
JP2006269999A (en) * 2005-03-25 2006-10-05 Sumco Corp PROCESS FOR PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THAT METHOD
JP2007505477A (en) * 2003-07-23 2007-03-08 エーエスエム アメリカ インコーポレイテッド Silicon-on-insulator structures and SiGe deposition on bulk substrates
US7687356B2 (en) * 2006-03-06 2010-03-30 Stmicroelectronics Crolles 2 Sas Formation of shallow siGe conduction channel
US7977221B2 (en) 2007-10-05 2011-07-12 Sumco Corporation Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007505477A (en) * 2003-07-23 2007-03-08 エーエスエム アメリカ インコーポレイテッド Silicon-on-insulator structures and SiGe deposition on bulk substrates
JP2012231165A (en) * 2003-07-23 2012-11-22 Asm America Inc Deposition of silicon germanium on silicon-on-insulator structures and bulk substrates
WO2006033292A1 (en) * 2004-09-24 2006-03-30 Shin-Etsu Handotai Co., Ltd. Method for manufacturing semiconductor wafer
US7550309B2 (en) 2004-09-24 2009-06-23 Shin-Etsu Handotai Co., Ltd. Method for producing semiconductor wafer
JP2006270000A (en) * 2005-03-25 2006-10-05 Sumco Corp PROCESS FOR PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THAT METHOD
JP2006269999A (en) * 2005-03-25 2006-10-05 Sumco Corp PROCESS FOR PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THAT METHOD
KR100783984B1 (en) 2005-03-25 2007-12-11 가부시키가이샤 섬코 Production method of strained silicon-soi substrate and strained silicon-soi substrate produced by same
US7687356B2 (en) * 2006-03-06 2010-03-30 Stmicroelectronics Crolles 2 Sas Formation of shallow siGe conduction channel
US7977221B2 (en) 2007-10-05 2011-07-12 Sumco Corporation Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same

Similar Documents

Publication Publication Date Title
US6723541B2 (en) Method of producing semiconductor device and semiconductor substrate
KR100783984B1 (en) Production method of strained silicon-soi substrate and strained silicon-soi substrate produced by same
US20060281234A1 (en) Semiconductor device and method of manufacturing the same
US6251754B1 (en) Semiconductor substrate manufacturing method
TWI310962B (en)
KR101154916B1 (en) Manufacture of thin soi devices
EP1801854B1 (en) Method for manufacturing semiconductor wafer
TW200403720A (en) Manufacturing method for semiconductor substrate and manufacturing method for semiconductor device
US20070117350A1 (en) Strained silicon on insulator (ssoi) with layer transfer from oxidized donor
JP2006524426A (en) Method and layer structure for producing strained layers on a substrate
TWI298911B (en) Sige/soi cmos and method of making the same
US20080164572A1 (en) Semiconductor substrate and manufacturing method thereof
JP2005236272A (en) LOW TEMPERATURE ANNEAL TO REDUCE DEFECT IN HYDROGEN-IMPLANTED, RELAXED SiXGe1-X LAYER
US7977221B2 (en) Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same
JP2001148473A (en) Semiconductor device and manufacturing method therefor
JP2004363198A (en) Method of producing strained silicon soi substrate
JP2010040931A (en) Manufacturing method of semiconductor substrate, and semiconductor substrate
JP2005072054A (en) METHOD FOR MANUFACTURING STRAIN RELAXING SiGe SUBSTRATE
JP4757519B2 (en) Manufacturing method of strained Si-SOI substrate and strained Si-SOI substrate manufactured by the method
JP2004363197A (en) Method of producing strained silicon soi substrate
JP2004342819A (en) Semiconductor substrate and its producing process
JP5257401B2 (en) Method for manufacturing strained silicon SOI substrate
JP2010062291A (en) Semiconductor substrate and its manufacturing method
JP2005050984A (en) Method for manufacturing strain si-soi substrate and strain si-soi substrate manufactured thereby
JP2004363199A (en) Process for producing semiconductor substrate

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20051117

Free format text: JAPANESE INTERMEDIATE CODE: A621

A977 Report on retrieval

Effective date: 20080201

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Effective date: 20080227

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080421

A131 Notification of reasons for refusal

Effective date: 20090224

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090415

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100202