JP2004362157A - Semiconductor device, address assignment method thereof, and control method of semiconductor device - Google Patents

Abstract

A semiconductor device capable of simultaneously selecting and operating a plurality of function macros, an address assignment method thereof, and a control method of the semiconductor device are realized.
A semiconductor device, an address assignment method thereof, and a control method of a semiconductor device according to the present invention have a plurality of function macros which have the same main configuration and generate the same output signal with respect to a predetermined input signal. And selecting means for simultaneously activating at least two of the plurality of selection signal outputs and simultaneously selecting at least two of the plurality of function macros when a common address is received. By accessing a common address, a plurality of function macros can be operated in parallel, and the processing time of the semiconductor device can be reduced.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device equipped with a plurality of function macros, an address assignment method thereof, and a control method of the semiconductor device.
[0002]
[Prior art]
In a conventional semiconductor device having a function macro, for example, an IP (Intellectual Property), it is necessary to execute a test of the function macro in a final test before shipment. For this, a method is used in which a system operation when the user actually uses the system is assumed, a test program for each function macro is created in accordance with the system operation, and these are sequentially executed.
[0003]
In recent years, since the entire system has become complicated and it is not practical to test all combinations, the degree of completion of the test program greatly affects the reliability of operation guarantee of the semiconductor device.
[0004]
Furthermore, with the rapid progress of miniaturization in semiconductor processes, SOC (System on Chip) has appeared and many functional macros have been mounted on one chip, so such test technology is becoming increasingly important. It has become.
[0005]
By the way, the test method as described above has a problem that a test time is increased in proportion to the number of mounted function macros because the test program is repeatedly executed by the number of function macros. Also, in the final test before shipment, the completeness of the test program that guarantees the operation of the entire system is very important, and simplifying the test routine introduced to screen past problem cases will provide sufficient assurance. It can be difficult. For this reason, the final test requires an enormous amount of test time in combination with the increase in the number of mounted macros due to the complexity of the system.
[0006]
Therefore, for a semiconductor device with simple input / output, a so-called multi-cavity test device for simultaneously testing a plurality of semiconductor devices is used, and a plurality of such devices are operated in parallel to increase the number of tests per unit time. The method has traditionally been adopted. However, in a semiconductor device having a large number of inputs and outputs such as an SOC, there is no test device capable of obtaining a large number of devices. Therefore, this method requires a huge capital investment including the installation area of the test device. .
[0007]
In order to cope with such a problem, there has been proposed a method of reducing a test time of a scan test. That is, Patent Document 1 describes a method of shortening a test time by branching a part of a scan path and performing input / output of scan data in that part in parallel.
[0008]
However, the scan test has an essential disadvantage that the operation of the function macro cannot be sufficiently guaranteed. The scan test is originally intended to verify partial circuit logic and to detect wiring connection failures, that is, open or shorted wiring, and is not suitable for screening of semiconductor devices in the final test as described above. It is. In particular, in order to guarantee the operation of the function macro, the scan test is not sufficient, and the operation test using the accumulated test routine is indispensable.
[0009]
In recent years, as described above, the system tends to be more complicated, and reducing the test time required for guaranteeing the operation in the final test is an important issue.
[0010]
[Patent Document 1]
JP-A-2002-196045
[0011]
[Problems to be solved by the invention]
As described above, conventionally, since the operation test of a plurality of function macros mounted by repeatedly and sequentially executing the test program is performed, there is a problem that an enormous test time is required for a final test before shipment.
[0012]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a semiconductor device capable of testing a plurality of function macros in a short time, an address assignment method thereof, and a semiconductor device control method. Aim.
[0013]
[Means for Solving the Problems]
According to one aspect of the present invention, a plurality of function macros having the same main configuration and generating the same output signal with respect to a predetermined input signal and the plurality of function macros when a predetermined address is received. There is provided a semiconductor device comprising a selecting means for simultaneously selecting at least two of the macros, wherein the same processing is executed in parallel in the selected function macro.
[0014]
According to one embodiment of the present invention, a semiconductor device having the same main configuration and including a plurality of function macros that generate the same output signal with respect to a predetermined input signal and a selection unit that selects the function macro Address allocation method, wherein the plurality of function macros are allocated to a predetermined common address so that the selection means simultaneously selects at least two of the plurality of function macros, and the common address is received. Accordingly, there is provided an address allocation method for a semiconductor device, wherein the same processing is executed in parallel in the selected function macro.
[0015]
Further, according to one aspect of the present invention, a semiconductor device having the same main configuration and including a plurality of function macros that generate the same output signal with respect to a predetermined input signal and a selection unit that selects the function macro An address setting step of supplying a predetermined common address to the selection unit such that the selection unit simultaneously selects at least two of the plurality of function macros, and the selected function An access step of reading data from a register specified by the common address of the macro or writing data to the register, so that the same processing is executed in parallel in the selected function macro A method for controlling a semiconductor device is provided.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor device, an address assignment method thereof, and a control method of a semiconductor device according to the present invention (hereinafter, referred to as “embodiments”) will be described with reference to the drawings.
[0017]
FIG. 1 is a circuit block diagram illustrating a semiconductor device according to an embodiment of the present invention. Here, mainly, a portion relating to a plurality of function macros having the same main configuration and a means for operating them at the same time is shown.
[0018]
The semiconductor device according to the embodiment of the present invention has a function macro A11 and a function macro B12 (hereinafter, referred to as “IP-A11” and “IP-B12”, respectively) having the same main configuration. These are collectively referred to as “IPs”), an address decoder 13 (hereinafter, referred to as “DEC 13”) for selecting IPs, and a multiplexer 14 (hereinafter, “MUX 14”) for receiving an output signal from the IPs and selecting and outputting one of them. ), A comparator 15 (hereinafter, referred to as “CMP15”) that receives output signals from IPs and compares them to determine a match or mismatch, an error signal multiplexer 16 that generates an error interrupt (hereinafter, “ErMX16”). And a system bus 17 to which a CPU (not shown) can be connected. It has.
[0019]
The DEC 13 receives the upper address 20 from the system bus 17, outputs a selection signal A21 (hereinafter, referred to as “Sel-A21”) to the IP-A11, and outputs a selection signal B22 (hereinafter, “Sel-B22”) to the IP-B12. ").
[0020]
The IP-A11 includes, in addition to the Sel-A21 from the DEC 13, the lower address 23, the read / write signal 24 (hereinafter, referred to as "RW24"), and the write data 25 (hereinafter, referred to as "WrD25") which are input signals from the system bus 17. ), An output signal read data A26 (hereinafter referred to as “RdD-A26”), a response signal A27 (hereinafter referred to as “Ack-A27”), and an error signal A28 as an error output. (Hereinafter, referred to as “Err-A28”).
[0021]
Further, the IP-A11 inputs and outputs serial data A29 to and from the outside of the semiconductor device via the pad A18.
[0022]
The IP-B 12 receives, in addition to the Sel-B 22 from the DEC 13, the lower address 23, RW 24, and WrD 25 that are input signals from the system bus 17, and outputs read data B 30 (hereinafter, “RdD-B 30”) that is an output signal. ), A response signal B31 (hereinafter, “Ack-B31”), and an error signal B32 (hereinafter, “Err-B32”) which is an error output.
[0023]
The IP-B12 inputs and outputs serial data B33 to and from the outside of the semiconductor device via the pad B19.
[0024]
The MUX 14 receives the upper address 20 from the system bus 17, the output signals RdD-A26 and Ack-A27 of the IP-A11, and the output signals RdD-B30 and Ack-B31 of the IP-B12, The read data 34 (hereinafter, referred to as “RdD34”) and the response signal 35 (hereinafter, referred to as “Ack35”) are output to the system bus 17 as output signals.
[0025]
The CMP 15 receives the output signals RdD-A26 and Ack-A27 of the IP-A11 and the output signals RdD-B30 and Ack-B31 of the IP-B12, and determines whether the signals match or mismatch (refer to FIG. Hereinafter, “Err-M36” is output.
[0026]
The ErMX 16 receives the upper address 20 from the system bus 17, the Err-M 36 from the CMP 15, the Err-A 28 from the IP-A 11, and the Err-B 32 from the IP-B 12, and generates an interrupt to the CPU. An error interrupt signal 37 (hereinafter, referred to as “Error 37”) to be output is output to the system bus 17.
[0027]
The system bus 17 includes a 32-bit address bus, a control bus including the RW 24, the Ack 35, and the Error 37, and a data bus including the RdD 34 and the WrD 25. The system bus 17 is connected to a CPU to control IPs.
[0028]
For the 32-bit address, the upper 20 bits ([31:12]) are used as the upper address 20, and the lower 12 bits ([11: 0]) are used as the lower address 23. As described later, the upper address 20 is used to identify IPs, and the lower address 23 is used as an address in each IPs.
[0029]
WrD25 is data written to IPs, and RdD34 is data read from IPs. RW24 is a signal for controlling reading from IPs or writing to IPs. RW24 = "1" means reading, and RW24 = "0" means writing.
[0030]
That is, when RW24 = "1", data is read from the register specified by the lower address 23 for the IPs specified by the upper address 20, and the data is output to the RdD 34 in synchronization with the system clock. You. When RW24 = "0", WrD25 is written to the register specified by the lower address 23 for the IPs specified by the upper address 20 in synchronization with the system clock.
[0031]
Ack35 is a response signal of IPs indicating that a command can be received from the CPU. When "1", the IPs can receive the command, and when "0", the IPs indicate that the IPs are being processed. I have.
[0032]
Hereinafter, the control signal is positive logic unless otherwise specified.
[0033]
The Error 37 is an interrupt signal for notifying the CPU when a fatal processing error in IPs occurs.
[0034]
The DEC 13 outputs Sel-A21 and Sel-B22 for selecting IPs according to the value of the upper address 20 received from the system bus 17. That is, if the upper address 20 is {C0000}, "1" is output to Sel-A21 and "0" is output to Sel-B22 to select IP-A11. (Hereinafter, the value of the address is represented by hexadecimal notation, such as {C0000}. The details of the address map will be described later.)
[0035]
If the upper address 20 is {C0001}, "0" is output to Sel-A21 and "1" is output to Sel-B22 to select IP-B12. Further, if the upper address 20 is {C000F}, “1” is output to Sel-A21 and “1” is output to Sel-B22, and both IP-A11 and IP-B12 are selected simultaneously.
[0036]
The IP-A11 is a serial input / output module that inputs and outputs serial data A29 to and from the outside of the semiconductor device, and has a serial input / output terminal connected to a dedicated pad A18. Further, the IP-A 11 has a data register, a command register, a flag register, and a macro ID identified by the lower address 23, receives data and a processing command from the CPU through these register groups, and The processing result is output to the CPU.
[0037]
The data register is used to transfer data input and output as serial data A29 to and from the CPU. The command register is a register in which the CPU writes a processing command to be executed by the IP-A 11, and the flag register is a set of flag bits indicating the processing result and the like.
[0038]
Reading from these register groups is performed as follows. First, Ack-A 27 is checked. If this is “1”, a register is selected according to the lower address 23. Next, "1" is given to the RW 24, and the RdD-A 26 is output in synchronization with the system clock.
[0039]
Similarly, writing to the register group is performed as follows. First, Ack-A 27 is checked. If this is “1”, a register is selected according to the lower address 23. Next, "0" is given to RW24, and WrD25 is written to the selected register in synchronization with the system clock.
[0040]
The macro ID holds an identification code for identifying IPs, and is read-only.
[0041]
The configuration and operation of the IP-B12 are the same as those of the IP-A11 except that the serial input / output terminal is connected to the dedicated pad B19 and the identification code held by the macro ID is different from the IP-A11. Is the same.
[0042]
According to the value of the upper address 20 received from the system bus 17, the MUX 14 selects one of the output signals RdD-A26 and Ack-A27 of the IP-A11 and the output signal RdD-B30 and Ack-B31 of the IP-B12. These signal sets are selected and output to the system bus 17 as output signals RdD34 and Ack35.
[0043]
That is, if the upper address 20 is {C0000}, the output signal of the IP-A11 is selected, and if the upper address 20 is {C0001}, the output signal of the IP-B12 is selected and output. If the upper address 20 is {C000F}, the output of the IP-A11 is selected and output. As described above, since the main configurations of the IP-A11 and the IP-B12 are the same and operate in the same manner, if both are selected at the same time, the output signal is not changed for the same input signal unless a processing error occurs. Will be the same.
[0044]
The CMP 15 compares the output signals RdD-A26 and Ack-A27 of the IP-A11 with the output signals RdD-B30 and Ack-B31 of the IP-B12, and if all of them match, Err "0" is output to -M36, and if even one is different, "1" is output to Err-M36 to generate an interrupt to the CPU.
[0045]
The ErMX 16 performs a logical operation on Err-A 28, Err-B 32, and Err-M 36 according to the value of the upper address 20 received from the system bus 17 and outputs the result to the system bus 17 as an Error 37. That is, if the upper address 20 is {C0000}, Err-A28 is selected, and if the upper address 20 is {C0001}, Err-B32 is selected and output. If the upper address 20 is {C000F}, the logical sum of Err-M36 and Err-A28 is output.
[0046]
Next, a control method of the semiconductor device having the above-described configuration will be described. FIG. 2 is a flowchart showing a method for controlling the semiconductor device according to the embodiment of the present invention. Here, a control flow for connecting a CPU module to the system bus 17 to simultaneously operate IPs and efficiently perform an IPs operation test has been described.
[0047]
The control method of the semiconductor device according to the embodiment of the present invention includes a waiting step 41 for waiting for the end of processing of IPs, an address setting step 42 for designating IPs, an access step 43 for reading / writing a register, and checking a processing status in IPs. This is composed of a process determining step 44, an end determining step 45, and an interrupt processing step 46.
[0048]
In the standby step 41, the CPU waits until the IPs becomes ready to receive a command. That is, while Ack35 is "0", the IPs are busy, and the CPU waits while monitoring Ack35 periodically. When the Ack 35 becomes “1” and the IPs are ready to receive a command, the CPU proceeds to the next address setting step 42.
[0049]
In the address setting step 42, the CPU outputs {C000F} (the details of the address map will be described later) to the upper address 20 as a common address. With this common address, the DEC 13 selects both the IP-A11 and the IP-B12, and the MUX 14 outputs the output signals RdD-A26 and Ack-A27 of the IP-A11 to the system bus 17 as output signals RdD34 and Ack35. It is set as follows.
[0050]
The ErMX 16 is set so as to output the logical sum of the Err-M 36 from the CMP 15 and the Err-A 28 from the IP-A 11 as an interrupt signal Error 37 to the system bus 17.
[0051]
The IPs are set so that the register receives the data from the WrD 25 and outputs the data to the RdD 34 by the lower address 23 output from the CPU simultaneously with the upper address 20. When the output of the address is completed, the CPU proceeds to the next access step 43.
[0052]
The access step 43 is a step of actually accessing the register specified in the address setting step 42. For example, when writing to a register, the CPU outputs the address of the register to be accessed in the address setting step 42 or {000} to the lower address 23 if it is a data register.
[0053]
Next, in access step 43, data to be written to the data register is output to WrD25, and RW24 is set to "0". Actual writing is performed in synchronization with the system clock, and the same data is simultaneously written to both the IP-A11 and the IP-B12 data registers.
[0054]
Similarly, when performing reading, the CPU first sets the RW 24 to “1” in the access step 43 and receives data from the RdD 34 in synchronization with the next system clock. At this time, since the common address is given to the MUX 14 in the address setting step 42, the RdD-A26 is output to the RdD34, and the CPU reads the value of the data register of the IP-A11. Output the same output signal unless an error occurs, so there is no problem. When the access to the IPs is completed, the CPU proceeds to the next processing determination step 44.
[0055]
The processing determination step 44 is a step of determining whether the access to the IPs performed in the access step 43 has been correctly processed as designed. That is, when reading is performed in the access step 43, the output signals from the IPs are compared by the CMP 15 and it is determined whether the output signals match or mismatch.
[0056]
If the comparison results are inconsistent, the CMP 15 outputs “1” to the Err-M 36 and sends an error signal 37 as an interrupt signal to the CPU via the ErMX 16. In response to this, the CPU proceeds to the interrupt processing step 46.
[0057]
In the processing determination step 44, the CPU reads the IPs flag register and confirms that the values are correct. The specific method is the same as the data reading in the access step 43 except that {008} designating the flag register is output to the lower address 23.
[0058]
That is, similarly to the access step, the CMP 15 sends the Error 37 to the CPU as needed, and the CPU shifts to the interrupt processing step 46 in response to this. Even when the comparison results in the CMP 15 match, the processing in the IPs may not be performed correctly.
[0059]
In this case, an interrupt is generated by Err-A28 from IP-A11 and can be confirmed by checking the value of the flag register. This means that there is a problem in the design or a bug in the test routines, except when errors are generated correctly as designed. In such a case (“NG”), the CPU abnormally ends the test routine. However, when applied to a pre-shipment test of a semiconductor device whose development has been completed and has reached the mass production stage, that is, a so-called screening test, such “NG” is excluded except for a mismatch in the CMP 15 due to a defect in individual IPs. Since it is unlikely that this will happen, the part that checks the flag register can be omitted.
[0060]
Further, in the process determination step 44, the output unique to each IPs, that is, the serial data A29 and the serial data B33 is also determined. That is, for example, when a serial output processing command is written in the command register in the access step 43, the output of the serial data A29 and the serial data B33 is as designed by an external test device connected to the pads A18 and B19. Is confirmed. If the result is "NG", the CPU abnormally ends the test routine.
[0061]
If the above-described problem does not occur (“OK”), the CPU proceeds to the end determination step 45.
[0062]
In the end determination step 45, when all necessary tests have been completed ("Yes"), the CPU normally ends the test routine. If the test still remains ("No"), the CPU proceeds to the standby step 41 and enters the next processing cycle.
[0063]
When an error 37 from the CMP 15 occurs in the processing determination step 44, the CPU proceeds to an interrupt processing step 46. Here, the address for each individual IPs is output to the upper address 20, the flag register of each IPs is read, which IPs has caused an error, the information is notified to the outside, and the test routine ends. .
[0064]
In this way, the CPU can simultaneously test the operation of a plurality of IPs.
[0065]
Next, an address assignment method for the semiconductor device having the above-described configuration will be described. FIG. 3 is an address map showing address assignment of the semiconductor device according to the embodiment of the present invention. Here, an address map of a portion related to IPs is mainly shown.
[0066]
In the address map of the semiconductor device according to the embodiment of the present invention, the register group of the IP-A11 is allocated to the upper address 20 = {C0000} (hereinafter, referred to as “dedicated address A”), and the upper address 20 = {C0001}. (Hereinafter, referred to as “dedicated address B”), a register group of IP-B12 is allocated, and upper address 20 = {C000F} (hereinafter, referred to as “common address”) of both IP-A11 and IP-B12. Register groups are assigned multiple times.
[0067]
To the dedicated address A, DR-A51 which is a data register of IP-A11 is allocated to lower address 23 = {000}, and CMD-A52 which is a command register of IP-A11 is allocated to lower address 23 = {004}. Flag-A53, which is a flag register of IP-A11, is allocated to lower address 23 = {008}, and ID-A54, which is a macro ID of IP-A11, is allocated to lower address 23 = {FFC}.
[0068]
Here, the reason why the lower address 23 is a multiple of 4 is that the address allocation is in units of bytes, whereas the data bus width is 32 bits, that is, 4 bytes.
[0069]
For the dedicated address B, DR-B55 which is a data register of IP-B12 is allocated to lower address 23 = {000}, and CMD-B56 which is a command register of IP-B12 is allocated to lower address 23 = {004}. Flag-B57 which is a flag register of IP-B12 is allocated to lower address 23 = {008}, and ID-B58 which is a macro ID of IP-B12 is allocated to lower address 23 = {FFC}.
[0070]
To the common address, DR-M59 which is a data register of IPs is assigned to lower address 23 = {000}, CMD-M60 which is a command register of IPs is assigned to lower address 23 = {004}, and lower address 23 is assigned. Flag-M61, which is a flag register of IPs, is assigned to {008}. Here, DR-M59 is a virtual register indicating that DR-A51 and DR-B55 are multiplexed, and the same applies to CMD-M60 and Flag-M61.
[0071]
That is, when the CPU accesses the common address, as described above, the DEC 13 outputs “1” to both the Sel-A21 and the Sel-B22, and the IP-A11 and the IP-B12 are simultaneously selected. , Or read from both register groups simultaneously.
[0072]
Note that no macro ID is assigned to the lower address 23 = {FFC} of the common address. This is because the macro ID is used for the purpose of uniquely identifying IPs.
[0073]
An example of performing serial output using a semiconductor device having such an address map will be described.
[0074]
When serial output is performed using the IP-A11, the CPU first writes data to be serially output to the DR-A51 according to the processing cycle of the above-described control flow (FIG. 2). Next, a processing command for instructing serial output is written into the CMD-A 52 to start the processing of the IP-A 11, and the processing enters a standby state of waiting for its termination in a standby step 41.
[0075]
However, in the pre-shipment test at the stage of mass production after the development is completed, reading of the flag register for each processing cycle in the processing determination step 44 of FIG. 2 is not performed. When the output of the serial data A29 is completed, the CPU reads the Flag-A53, checks the execution status of the process, and confirms that the process has been performed as requested.
[0076]
In this series of operations, the CPU outputs {C0000} to the upper address 20 in order to access the register group of the IP-A11. Therefore, the MUX 14 and the ErMX16 select and output the output signal from the IP-A11. ing.
[0077]
Further, when a fatal error occurs during the execution of the processing in the IP-A11, the Err-A28 output from the IP-A11 interrupts the CPU as the Error37, so that the CPU may execute the error processing routine. it can.
[0078]
The case of performing serial output using the IP-B12 is the same as that of the IP-A11, except that the register group of the IP-B12 is accessed.
[0079]
Next, a case where IPs are operated simultaneously for an operation test will be described by taking a serial output as an example. First, the CPU writes data to be serially output to the DR-M59. Next, a processing command instructing a serial output is written into the CMD-M60, and the execution of the processing of the IPs is started at the same time.
[0080]
When the output of the serial data is completed, the CPU reads the Flag-M61, checks the execution status of the process, and confirms that the process has been performed as requested. In this series of operations, the CPU outputs {C000F} as the upper address 20, so the MUX 14 selects and outputs the output signal from the IP-A11, and the ErMX16 selects the Err-M36 from the CMP 15 and the Err-M36 from the IP-A11. The logical sum with Err-A28 is output.
[0081]
If the IPs are operating as designed, their output signals have exactly the same value, and Err-M36 is "0". Conversely, if any error occurs during the execution of the process in the IPs, the output signal of the IPs has a different value, and the Err-M 36 becomes “1”, the CPU is interrupted by the Error 37, and the CPU An error handling routine can be executed.
[0082]
If the same error occurs in the IPs as designed, the Err-A 28 from the IP-A 11 becomes “1” and the CPU is interrupted by the Error 37.
[0083]
In this way, both IPs can be tested with one command execution. The important thing is that the program executed by the CPU can use the routine for the conventional IPs as it is, except for accessing a common address. In other words, the test routine for IPs accumulated in the past can be used with almost no change.
[0084]
According to the above embodiment, a plurality of IPs can be simultaneously selected and operated easily, so that the operation test time of the semiconductor device can be significantly reduced.
[0085]
Furthermore, since multiple access to IPs can be easily realized only by changing the upper address 20, the conventional stored test routine can be used almost as it is, and the test program development time can be greatly reduced. It does not impair the reliability of the program, and thus the reliability of the operation test.
[0086]
In the above embodiment, the control signal has a positive logic, but the present invention is not limited to this. In the above-described embodiment, as an example, a method of performing an operation test by accessing a common address has been described. However, the present invention is not limited to this. For example, an initial value may be set to a plurality of IPs at the same time. It can also be applied to the case. In this case, if it is confirmed by the pre-shipment operation test that the IPs operate correctly, the comparison judgment of the output signal by the CMP 15 is not necessarily required.
[0087]
Furthermore, in the above-described embodiment, IPs are two serial input / output macros. However, the present invention is not limited to this. The main configuration is the same, and the same output signal is output for a predetermined input signal. The number and functions of the function macros to be generated are not limited.
[0088]
In this case, it goes without saying that the types and order of the register groups (hereinafter collectively referred to as “common registers”) allocated to the address space of the common address are different from those in the above-described embodiment. The present invention can be widely applied to a system LSI having a plurality of function macros and the like.
[0089]
Further, some of the IPs that are multiple-accessed may have additional functions, additional registers, and the like different from the others. In principle, the present invention can be applied to multiple access IPs provided that they have a common function and register.
[0090]
For example, registers unique to the function macro (hereinafter, referred to as “unique registers”) are not allocated to the address space of the common address as in the macro ID described above, and only registers common to the IPs operated simultaneously are used. May be assigned as a common register.
[0091]
Conversely, a unique register can also be assigned to the address space of the common address, and when the CPU accesses it, it can be set so that only the function macro operates.
[0092]
Further, it is not necessary that the multiple-accessed IPs all generate the same output signal for all combinations that can be input to the common register. In principle, the present invention can be applied to a subset of input signals that generate the same output signal, and can be set so that only those input signals are operated in parallel using a common address.
[0093]
Further, in the above-described embodiment, the number of common addresses is one. However, the present invention is not limited to this. IPs may be divided into a plurality of groups having similar functions and operations, and a common address may be provided for each group. . In this case, the DEC 13 simultaneously activates the selection signals for the IPs belonging to the group corresponding to each common address.
[0094]
What is important is that IPs belonging to a group accessed by one common address have the same type of register assigned to the same lower address 23. Furthermore, this grouping need not be exclusive, and one IPs may be accessed by a plurality of common addresses.
[0095]
Further, in the above-described embodiment, the upper address 20 is 20 bits, but the present invention is not limited to this, and the number of bits of the upper address 20 and the lower address 23 may be arbitrarily set as necessary. Good.
[0096]
Furthermore, in the above-described embodiment, the MUX 14 selects the output signal of the IP-A11 when the common address is accessed, but the present invention is not limited to this, and the MUX 14 is accessed multiple times with the common address. The output signal of any of the IPs may be selected.
[0097]
Further, in the above-described embodiment, the Err-M36 which is the determination result of the CMP 15 is output to the ErMX16. However, the present invention is not limited to this, and the output is performed via external output means such as an output buffer and an output pad. Alternatively, the data may be directly output to the outside of the semiconductor device. In this case, the quality of the semiconductor device is determined by an external device according to Err-M36.
[0098]
In addition, a function equivalent to the above-described CMP 15 can be implemented as software of a CPU. In this case, the output signals of the IPs need to be sequentially read out using the respective dedicated addresses, but the comparison by software can be flexibly performed as necessary, such as comparing only specific bits of the output signal. There is a merit that can be.
[0099]
Further, in the above-described embodiment, the CPU is an internal module connected to the system bus 17, but the present invention is not limited to this. For example, the system bus 17 is pulled out of the semiconductor device, A general-purpose CPU or computer or the like is connected thereto, and similarly to the above-described CPU module, an operation test of IPs and initial value setting can be performed.
[0100]
【The invention's effect】
As described above, according to the present invention, it is easy to select a plurality of function macros at the same time and to execute the same processing in parallel on the selected function macros, so that the processing time of the semiconductor device is greatly reduced. be able to.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a flowchart showing a control method of the semiconductor device according to the embodiment of the present invention.
FIG. 3 is an address map showing address assignment of the semiconductor device according to the embodiment of the present invention.
[Explanation of symbols]
11 Function macro A
12 Function macro B
13 Address decoder
14 Multiplexer
15 Comparator
16 Error signal multiplexer
17 System bus
18 Pad A
19 Pad B
20 Upper address
21 Selection signal A
22 Selection signal B
23 Lower address
24, 25 input signal
26, 27 output signal A
28 Error signal A
29 Serial data A
30, 31 output signal B
32 Error signal B
33 Serial data B
34, 35 output signal
36 Judgment signal
37 Error interrupt signal
41 Waiting step
42 Address setting step
43 Access Step
44 Processing decision step
45 End judgment step
46 Interrupt processing step
51, 55, 59 data registers
52, 56, 60 Command register
53, 57, 61 flag registers
54, 58 Macro ID

Claims (13)

A plurality of function macros having the same main configuration and generating the same output signal with respect to a predetermined input signal,
When receiving a predetermined address, comprising: selecting means for simultaneously selecting at least two of the plurality of function macros;
A semiconductor device wherein the same processing is executed in parallel in the selected function macro. The selecting means,
2. The semiconductor device according to claim 1, wherein when a predetermined address is received, all of the plurality of function macros are selected at the same time. 2. The semiconductor device according to claim 1, further comprising a comparison unit that receives the output signals generated by the plurality of function macros and generates a determination signal indicating a match or a mismatch between the output signals. 3. 4. The semiconductor device according to claim 3, further comprising an output unit that outputs the determination signal to the outside. The function macro is
It further has a function to generate and output an error signal when the processing is not completed normally,
An error output switching unit that receives the determination signal and the error signal from the plurality of function macros, selects one of the determination signal and the error signal according to a received address, and outputs the selected signal as an error interrupt signal; The semiconductor device according to claim 3, further comprising: An output switching unit that receives the output signals from the plurality of function macros, selects one of the output signals according to a received address, and outputs the selected output signal; A system bus connectable to a CPU for supplying the input signal to a macro, supplying the address to the output switching means, receiving the selected output signal from the output switching means, and causing the function macro to execute a process The semiconductor device according to claim 1, further comprising: An output switching unit that receives the output signals from the plurality of function macros, selects one of the output signals according to a received address, and outputs the selected output signal; Supplying the input signal to a macro, supplying the address to the output switching means, receiving the selected output signal from the output switching means, supplying the address to the error output switching means, 6. The semiconductor device according to claim 5, further comprising a system bus connectable to a CPU that receives the error interrupt signal from output switching means and causes the function macro to execute a process. A plurality of function macros having the same main configuration and generating the same output signal with respect to a predetermined input signal,
An address assignment method for a semiconductor device, comprising a selection unit for selecting the function macro,
By assigning the plurality of function macros to a predetermined common address and receiving the common address so that the selecting means simultaneously selects at least two of the plurality of function macros, the selected function is selected. An address allocation method for a semiconductor device, wherein the same processing is executed in parallel in a macro. The method according to claim 8, wherein all of the plurality of function macros are assigned to the common address. A plurality of function macros having the same main configuration and generating the same output signal with respect to a predetermined input signal,
A control method of a semiconductor device comprising a selection unit for selecting the function macro,
An address setting step of supplying a predetermined common address to the selection unit such that the selection unit simultaneously selects at least two of the plurality of function macros;
An access step of reading data from a register specified by the common address of the selected function macro, or writing data to the register,
A method of controlling a semiconductor device, wherein the same processing is executed in parallel in the selected function macro. The method according to claim 10, wherein the common address is an address for selecting all of the plurality of function macros. After the processing of the function macro in the access step is completed, the output signal from the function macro is compared, and if they do not match, a processing determining step of selecting execution suspension is further provided. The method for controlling a semiconductor device according to claim 10. A method for controlling a semiconductor device, further comprising: a comparison unit configured to receive the output signals generated by the plurality of function macros and generate a determination signal indicating a match or a mismatch between the output signals.
The method according to claim 10, further comprising a process determining step of selecting execution interruption when the determination signals do not match.

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