JP2004362074A - Method for analyzing emi noise of electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To extract EMI noises through simulations to high accuracy, thereby lowering the cost of designing a printed board on which an integrated circuit device is mounted. <P>SOLUTION: This method includes a step P1 for creating an IC device model F3 having the internal power supplies of IC chips, a model of an internal circuit connected between the internal power supplies, a common power plane on the board, and a plurality of power pins connected to the internal power supplies; a process P2 for simulating the operation of the IC device model to create current waveform information F5 generated on the plurality of power pins; and a process P4 in which the operation of a board model F8 having a plurality of power planes and a plurality of current sources arranged in the positions of the plurality of power pins connected to the planes is simulated as the current waveform information F5 is given to the plurality of current sources to create an electromagnetic field that emanates from the power planes. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an EMI noise analysis method for an electronic device, and more particularly, to an EMI noise analysis method capable of reproducing EMI noise of an electronic device having a board such as a printed circuit board mounted with an LSI with high accuracy by simulation.
[0002]
[Prior art]
Since EMI (Electro Magnetic Interference) noise of electronic devices causes malfunction of other electronic devices, EMI measures for electronic devices are obligated in major countries. If EMI noise exceeds a certain standard level, import and sale to the country are prohibited. EMI noise refers to noise in which power supply noise generated from an LSI is radiated to space as an electromagnetic wave via a power supply plane of a printed circuit board. With the recent increase in speed, increase in pins, and increase in current of LSIs, In addition, power supply noise tends to increase, and EMI noise also tends to increase.
[0003]
According to the conventional EMI countermeasures, a board such as a printed circuit board on which an LSI is mounted is actually manufactured, EMI noise generated in an operation test is measured, and whether or not the level is within a standard level is checked. If it exceeds, components such as a bypass capacitor for EMI noise suppression are mounted on the board in a tri-and-error manner, and EMI noise is measured again to confirm that the EMI noise does not exceed the standard level.
[0004]
In this specification, a board is a general term for a board on which an LSI is mounted, such as a printed board. Therefore, the board model is a general term for the printed circuit board model.
[0005]
The above-mentioned EMI countermeasure method involves manufacturing an actual product, measuring EMI noise, and taking a specific countermeasure, and has a problem that the number of steps is complicated and the cost is high. If EMI noise cannot be suppressed to within a standard level by a countermeasure component, countermeasures such as redesigning a power supply plane of a printed circuit board are required, and unexpected rework may be forced.
[0006]
Therefore, it is desired to take EMI measures at the design stage. As a method of EMI countermeasures at the design stage, Japanese Patent Application Laid-Open No. H11-150572 described later models an LSI circuit mounted on a printed board as a power supply model, and uses a power supply model of the LSI circuit and connection data of the printed circuit board. It has been proposed to obtain a current distribution on a substrate and obtain an electromagnetic field distribution on the substrate using an electromagnetic field analysis simulator.
[0007]
FIG. 1 is a diagram showing the conventional LSI circuit model. According to this LSI model 80, a power supply plane and a large number of logic gate circuits are connected to a single inverter circuit 81, an operation signal source 82 provided to the gate thereof, and a power supply / ground and an output of the inverter circuit 81. It is modeled by a load capacitance 83 and an equivalent internal capacitance 84 between the power supply and the ground. By simulating the operation of the LSI circuit model, power supply noise generated at the power supply pin 85 can be obtained.
[0008]
FIG. 2 is a diagram showing a printed circuit board model for obtaining EMI noise using the above-described conventional LSI circuit model. According to this, the power supply pin 85 of the LSI model of FIG. 1 is connected to the transmission lines 93 and 94 modeling the power supply on the printed circuit board via the external terminals 91 and 92 modeled by inductance and resistance, and the bypass capacitor. Is generated, and the generated electromagnetic wave noise is obtained by simulating the printed circuit board model 90 including the capacity 95.
[0009]
According to Patent Document 2, in order to simulate LSI noise, the LSI is divided into a plurality of functional blocks, current consumption of the plurality of functional blocks is obtained by simulation, and each functional block is connected to an inverter circuit and an output load capacitance. It is described that the circuit block is replaced by a circuit block consisting of: a circuit for noise simulation, a circuit for noise simulation is generated by extracting impedance information of a power supply wiring connecting the functional blocks, and noise is obtained by operation simulation.
[0010]
[Patent Document 1]
JP 2001-222573 A (for example, FIGS. 1, 22, and 25)
[0011]
[Patent Document 2]
JP-A-11-120214 (for example, FIG. 1)
[0012]
[Problems to be solved by the invention]
According to Patent Document 1, the LSI circuit model has only one set of power supply pins for one power supply system, and therefore cannot reproduce the structure of a plurality of power supply pins provided in an actual LSI. The power supply noise of the LSI, which is a cause of the EMI noise, cannot be obtained with high accuracy. With the increase in the size of LSIs, an actual LSI is provided with a plurality of power pins, and the internal impedance on the printed circuit board varies greatly depending on the location. In particular, the internal impedance changes near the bypass capacitor on the printed circuit board. Since it is remarkable, it is required to reproduce power supply noise generated from a plurality of power supply pins of the LSI, but this is not possible with the above-described LSI circuit model.
[0013]
Furthermore, according to Patent Document 1, the LSI circuit model is equivalent to one current source, and it is difficult to reproduce the operation inside a large-scale LSI with high accuracy. In particular, the LSI circuit includes an internal logic cell circuit and peripheral input / output cell circuits. The internal logic cell circuit generates power supply noise depending on the internal operation. Since power supply noise is generated depending on the operation between the LSIs on the substrate, highly accurate power supply noise cannot be obtained with an LSI model that does not consider such points.
[0014]
According to Patent Document 2 described above, power supply noise is obtained using an LSI circuit model. However, the technique does not reproduce a plurality of power supply pin structures provided in an actual LSI. It has the same problems as the first.
[0015]
Therefore, an object of the present invention is to provide an EMI noise analysis method capable of accurately obtaining power supply noise given to a board such as a printed circuit board by an LSI circuit and obtaining EMI noise of an electronic device with high accuracy. .
[0016]
[Means for Solving the Problems]
In order to achieve the above object, one aspect of the present invention is a method for performing EMI noise analysis using a board model equipped with an integrated circuit device including a package having a plurality of power pins and including an integrated circuit chip. (1) An integrated circuit having an internal power supply of the integrated circuit chip, an internal circuit model connected between the internal power supplies, a common power supply plane on the board, and a plurality of power supply pins connected to the internal power supply. A step of generating a device model; (2) a step of simulating the operation of the integrated circuit device model to generate current waveform information generated at the plurality of power pins; and (3) a plurality of power planes and connected to the plurality of power planes. An operation simulation of a board model having a plurality of current sources disposed at the positions of the plurality of power supply pins is performed by the plurality of current sources. Generating an electromagnetic field generated from the power plane by giving the waveform information.
[0017]
According to the above aspect of the present invention, an integrated circuit device model having a plurality of power supply pins for providing power supply noise to a power supply plane of a board is obtained, current waveform information generated at each power supply pin is obtained, and the obtained power supply waveform information is obtained from the board. Operation simulation is performed by applying the power supply pins to the corresponding power supply pins in the model, and an electromagnetic field generated from the power supply plane of the board is obtained. Therefore, power supply noise from a plurality of power supply pins depending on the position on the board can be reproduced with high accuracy, and the strength of the electromagnetic field required thereby also has high accuracy. Therefore, optimal EMI countermeasures can be taken at the design stage, and it can be manufactured beforehand to confirm that EMI noise is equal to or lower than the standard level, and the overall cost can be reduced.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments, but extends to the inventions described in the claims and their equivalents.
[0019]
FIG. 3 is a flowchart of the EMI noise analysis method according to the present embodiment. This EMI noise analysis method includes the following four steps P1 to P4.
(1) Integrated circuit device model generation step P1: layout information F10 of an integrated circuit chip, operating condition information F11 of an integrated circuit, load condition information F12 including information of resistance and inductance of a bonding wire and a lead frame of a package, input and output. An integrated circuit device model F3 including an integrated circuit chip and a package is created from the output cell circuit description information F13 and the like (S10). The integrated circuit device model F3 includes an internal power supply network, a plurality of power supply pins connected to a common power supply plane on the printed circuit board and the internal power supply network, and a plurality of current consumption sources and power supplies connected between the internal power supply networks. It has an inter-capacitance and a plurality of input or output cells connected to a distributed constant line on a printed circuit board and an internal power supply network.
(2) Current waveform information generation step P2 for power supply pins: The operation of the integrated circuit device model is simulated (S12) to generate current waveform information F5 generated at a plurality of power supply pins.
(3) Printed circuit board model generation step P3: Based on printed circuit board layout information F6 having a plurality of power supply planes and position information F7 of power supply pins of the integrated circuit device on the printed circuit board, a plurality of pieces of power supply plane information and a plurality of pieces of information connected thereto. A printed circuit board model F8 having the current source information arranged at the position of the power supply pin is generated (S14).
(4) Electromagnetic field strength generation step P4: The operation simulation of the printed circuit board model is performed by giving current waveform information to the current sources of the plurality of power pins (S16), and the strength of the electromagnetic field generated from the power plane of the printed circuit board is generated. I do.
[0020]
The above four steps will be described in detail.
(1) Integrated circuit device model generation process P1
FIG. 4 is a configuration diagram of a device for creating an integrated circuit device model. The integrated circuit device model creation device divides the integrated circuit device to be analyzed for power supply noise into power supply wiring, internal capacitance, internal current consumption, and input / output cells, and models these power supply wiring, internal capacitance, internal current consumption, and input / output cells. Then, the power supply wiring, the internal capacitance, the internal current consumption, and the input / output cell model are combined to create an integrated circuit device model for power supply noise analysis for the integrated circuit device to be analyzed for power supply noise.
[0021]
In FIG. 4, reference numeral 1 denotes an integrated circuit device model creation information storage unit that stores information necessary for creating an integrated circuit device model for power supply noise analysis, and 2 denotes an integrated circuit device model creation information storage unit 1. An integrated circuit device model creation unit for creating an integrated circuit device model for power supply noise analysis by inputting information for creating an integrated circuit device model, and an integrated circuit for power supply noise analysis created by the integrated circuit device model creation unit 2 It is an integrated circuit device model storage unit that stores a device model.
[0022]
In the integrated circuit device model creation information storage unit 1, reference numeral 4 denotes an integrated circuit device layout information storage unit for storing layout information F10 of the power supply noise analysis target integrated circuit device, and reference numeral 5 denotes operating conditions of the power supply noise analysis target integrated circuit device. An integrated circuit device operating condition storage means for storing F11, 6 is a load condition storing means for storing a load condition F12 of the integrated circuit device to be analyzed for power supply noise, and 7 is a circuit of an input / output cell of the integrated circuit device to be analyzed for power supply noise. This is an input / output cell circuit description storage unit that stores the description F13.
[0023]
In the integrated circuit device model creation unit 2, the power supply wiring sub-model creation means 8 uses the layout information of the integrated circuit device to be analyzed for power supply noise to create a power supply wiring model that can be analyzed by a circuit simulator (hereinafter referred to as a power supply wiring sub model). Create Further, the internal capacitance submodel creating means 9 creates a model of an internal capacitance (hereinafter, referred to as an internal capacitance submodel) that can be analyzed by a circuit simulator from the layout information of the integrated circuit device to be analyzed for power supply noise.
[0024]
The internal current consumption submodel creating means 10 creates a model of internal current consumption that can be analyzed by a circuit simulator (hereinafter referred to as an internal current consumption submodel) from the layout information and the operating conditions of the integrated circuit device to be analyzed for power supply noise. . The input / output sub-model creating means 11 generates input / output cell models (hereinafter referred to as input / output cells) that can be analyzed by a circuit simulator based on the layout information, operating conditions, load conditions, and input / output cell circuit description of the integrated circuit device to be analyzed for power supply noise. Output sub-model).
[0025]
The sub-model coupling unit 12 is created by the power supply wiring sub-model created by the power supply wiring sub-model creation unit 8, the internal capacitance sub-model created by the internal capacitance sub-model creation unit 9, and the internal current consumption sub-model creation unit 10. The internal current consumption sub-model and the input / output sub-model created by the input / output sub-model creating means 11 are combined to provide an integrated circuit device for power supply noise analysis that can be analyzed by a circuit simulator for an integrated circuit device to be analyzed for power supply noise. Create a model.
[0026]
FIG. 5 is a configuration diagram of the power supply wiring sub-model creating means 8. In FIG. 5, reference numeral 13 denotes a power supply line dividing means for extracting a power supply line from layout information of an integrated circuit device to be subjected to power supply noise analysis and dividing the extracted power supply line into a plurality of power supply lines in a grid pattern. A power supply wiring sub-model resistance / inductance calculation means for calculating resistance and inductance for each power supply wiring divided by the means 13.
[0027]
Reference numeral 15 denotes a power supply wiring submodel circuit description creating means for creating a circuit description of a power supply wiring submodel that can be analyzed by a circuit simulator based on the calculation result of the power supply wiring submodel resistance / inductance calculation means 14. In addition, even if the power supply wiring network in the grid is of the same power supply type, it is generally composed of a plurality of wiring layers. May be synthesized.
[0028]
FIG. 6 is a configuration diagram of the internal capacitance sub-model creating means 9. In FIG. 6, reference numeral 16 denotes a grid in the same manner as in the case of extracting power supply wiring capacitance and decoupling capacitor and transistor arrangement information from the layout information F10 of the integrated circuit device to be analyzed for power supply noise, and dividing the power supply wiring. This is an internal capacity dividing means that divides the internal capacity.
[0029]
Reference numeral 17 denotes an internal capacitance calculating unit that calculates the capacitance value in the lattice by combining the capacitance between the power supply lines, the capacitance of the decoupling capacitor, and the capacitance of the transistor included in each lattice. An internal capacitance submodel circuit description creating means for creating a circuit description of an internal capacitance submodel that can be analyzed by a circuit simulator based on the result.
[0030]
FIG. 7 is a configuration diagram of the internal current consumption sub-model creating means 10. In FIG. 7, reference numeral 19 denotes an internal current consumption dividing means for extracting the arrangement information of the logic gates from the layout information F10 of the integrated circuit device to be analyzed for the power supply noise, and dividing the arrangement information into a grid pattern as in the case of dividing the power supply wiring. is there. Reference numeral 20 denotes an internal current consumption calculation unit that combines the current consumption waveforms in consideration of the switching timing of the logic gate included in each grid and calculates the current consumption waveform in the grid.
[0031]
Reference numeral 21 denotes an internal current consumption submodel circuit description creation unit that creates a circuit description of an internal current consumption submodel that can be analyzed by a circuit simulator based on the calculation result of the internal current consumption calculation unit 20. When the switching timing of the logic gates in the grid is unknown in the internal current consumption calculating means 20, the average current consumption in one cycle is obtained from the operating frequency of the chip and the power consumption. Create a current consumption waveform without changing the charge.
[0032]
FIG. 8 is a configuration diagram of the input / output sub-model creating means 11. The input / output cell dividing means 22 extracts the arrangement of the input / output cells from the layout information of the integrated circuit device to be analyzed for power supply noise. The input / output cells used for power supply noise analysis are classified into four types: an input cell model, an output cell model, an input / output cell model, and a power supply cell model.
[0033]
The input signal generating means 23 generates a signal of an external signal source in the case of an input cell model or an input / output cell model based on the operating condition F1 of the integrated circuit device to be analyzed for power supply noise, and outputs the signal of the output cell model and the input signal. In the case of an output cell model, a signal of an internal signal source is generated. In the case of an input / output cell model, a control signal for switching polarity (input or output) is generated.
[0034]
The load generating means 24 creates an internal capacitance, a resistance / capacity / inductance of a bonding wire / lead frame, a damping resistance, a distributed constant line, and an external load based on a load condition of an integrated circuit device to be analyzed for power supply noise. The input / output submodel circuit description creating means 25 arranges the input / output cell circuit descriptions in accordance with the arrangement of the input / output cells, and combines the input signals and loads with the input / output subcircuit model descriptions. Create a description.
[0035]
FIG. 9 is a flowchart of an integrated circuit device model creation method. In the integrated circuit device model creation method, for the integrated circuit device to be analyzed for power supply noise, a power supply wiring sub model creation unit 8 creates a power supply wiring sub model (S101), and an internal capacitance sub model creation unit 9 creates an internal capacitance sub model. A creating step (S102), an internal current consumption submodel creating step by the internal current consumption submodel creating means 10 (S103), an input / output submodel creating step by the input / output submodel creating means 11 (S104), and finally, A step (S105) of creating an integrated circuit device model for power supply noise analysis by the model coupling unit 12 is performed.
[0036]
FIG. 10 is a conceptual diagram of the power supply wiring sub-model created by the power supply wiring sub-model creation means 8. In the present embodiment, the power supply wiring is divided into a plurality of layers according to the power supply type, each layer is divided into a lattice shape by a specified division number, and each of the divided areas (power supply lattice) has a cross-shaped pattern including a resistance and an inductance. A power supply wiring sub model is obtained by applying the circuit model.
[0037]
In the example of FIG. 10, the power supply wiring layer is a square of 2 mm × 2 mm, and a VDE layer 26 which is a 3.3 V system power supply wiring layer, a VDD layer 27 which is a 1.2 V system power supply wiring layer, and 0 V The power supply wiring layer is divided into a VSS layer 28 which is a (grounding) system power supply wiring layer. A power supply wiring sub model 29 is created by applying a cross-shaped circuit model including a resistance and an inductance to a grid region of × 500 μm. Reference numeral 29 denotes one of the power supply wiring sub-models.
[0038]
Note that, depending on the location of the grid, a structure in which the power supply wiring is cut off halfway may be considered, and if a cross-shaped circuit model is applied as it is, uncoupled resistance and inductance may remain. In such a case, it is necessary to delete the relevant part. This processing can be performed manually, but can also be performed automatically by a program when the model is created.
[0039]
By modifying the power supply wiring sub-model in this manner, it becomes possible to model various wiring structures, and an integrated circuit device including a flip-chip type integrated circuit device, a macro having a different operating voltage, or the like, or It is also possible to model an integrated circuit device of a type in which power supply wiring is not uniform, such as an integrated circuit device in which an internal ground line is intentionally divided.
[0040]
As for the values of the resistance and the inductance in the circuit model, values estimated from design specifications are set, or values extracted from actual layout data F2 are used. Further, in the example of FIG. 10, although the number of divisions is small, if the number of divisions is sufficiently large, the power supply wiring network is represented as a distributed constant line in the power supply wiring submodel, and the noise behavior of the power supply wiring is reduced. It is possible to analyze in detail.
[0041]
FIG. 11 is a conceptual diagram of the internal capacitance submodel created by the internal capacitance submodel creation means 9. In FIG. 11, reference numeral 30 denotes a power grid of the VDE layer or the VDD layer, 31 denotes a power grid of the VSS layer, and 32 denotes an internal capacity sub model. The internal capacitance submodel 32 includes a capacitance between power supply lines existing in a plane represented by the two power supply lattices 30 and 31 of interest, a capacitance of a decoupling capacitor for reducing power supply noise, and a logic gate. The total capacity is defined as capacity. The capacity of the logic gate is a capacity based on a capacity between a source and a gate, a capacity between a drain and a gate of the CMOS inverter, and the like. The internal capacitance submodel 32 is determined by summing the capacitances in each photon.
[0042]
As described above, since the integrated circuit device is divided into a lattice shape and modeling is performed with the total value of the capacitance existing inside each lattice as a unit, the distribution of the capacitance inside the integrated circuit device can be expressed. In addition, it is possible to accurately analyze the effect of the capacitance component that reduces power supply noise, such as optimizing the arrangement of the decoupling capacitor.
[0043]
FIG. 12 is a conceptual diagram of the internal current consumption submodel created by the internal current consumption submodel creation means 10. In FIG. 12, reference numeral 33 denotes an internal current consumption sub model. The internal current consumption submodel 33 is defined as a current source of the total value of the current consumption of the logic gates existing in the plane represented by the power grids 30 and 31 of interest.
[0044]
As described above, regarding the internal current consumption, since the integrated circuit device is divided into a lattice and modeling is performed for each logic gate existing therein, the distribution of the current consumption inside the integrated circuit device can be expressed. For example, a current consumption model can be individually set for a clock buffer disposed locally, for a data path section, for a RAM, and the like, so that power supply noise due to current consumption by a logic gate inside an integrated circuit device is reduced. It is possible to analyze with high accuracy.
[0045]
FIG. 13 is a conceptual diagram of an input cell model created by the input / output submodel creation means 11. In the input cell model, a transistor level input cell 34 is arranged at an actual position of an integrated circuit device, and an external signal 35, a distributed constant line 36, a damping resistor 37, a bonding wire / lead frame 38, and an internal load 39 are connected. Be composed. Therefore, in creating this input cell model, it is necessary to refer to the data of the integrated circuit device model F3 including the package model.
[0046]
Here, the distributed constant line 36 represents the wiring on the printed circuit board outside the integrated circuit device, and the internal load 39 represents the capacitance of the wiring connecting the input cell 34 and the logic gate and the gate capacitance of the logic gate itself. ing. The input cell model is also connected to power supply wiring submodels 40, 41, and 42 that are located directly above the target input cell.
[0047]
FIG. 14 is a conceptual diagram of an output cell model created by the input / output submodel creation means 11. In the output cell model, a transistor-level output cell 43 is arranged at an actual position of an integrated circuit device, and an external load 44, a distributed constant line 45, a damping resistor 46, a bonding wire / lead frame 47, and an internal signal 48 are connected. Be composed.
[0048]
Here, the distributed constant line 45 represents a wiring on a printed circuit board outside the integrated circuit device, and the internal signal 48 represents an input signal waveform near the input terminal of the output cell 43. The output cell model is also connected to power supply wiring sub-models 49, 50, and 51 that are located immediately above the output cell 43 of interest.
[0049]
FIG. 15 is a conceptual diagram of the input / output cell model created by the input / output submodel creation means 11. In the input / output cell model, a transistor level input / output cell 52 is arranged at an actual position of an integrated circuit device, and an external signal 53, an external load 54, an operation changeover switch 55, a distributed constant line 56, a damping resistor 57, a bonding wire It is configured by connecting a lead frame 58, an internal load 59, an internal signal 60, and an internal operation switching signal (not shown).
[0050]
In the case of the input / output cell 52, since it operates both as an input cell and an output cell, it has a configuration in which an operation switching mechanism is added to a combination of the input cell model and the output cell model. In the example of FIG. 15, the external operation is switched by the switch 55, but a transistor circuit such as an input / output cell can be used for this part.
[0051]
The input / output cell model is also connected to power supply wiring submodels 62, 63, and 64 that are located directly above the target input / output cell 52. By appropriately setting the input / output switching control signal for the input / output cell model and performing the analysis, it is also possible to analyze the dynamic switching of the input / output cell operation mode (input mode or output mode). Become.
[0052]
FIG. 16 is a conceptual diagram of the power supply cell model created by the input / output submodel creation means 11. The power supply cell model (A) of VDE or VDD is configured by arranging a power supply cell 65 at an actual position of an integrated circuit device and adding an external power supply (VDE or VDD) 66 and a bonding wire lead frame 67. It is connected to the wiring sub model 68.
[0053]
The VSS power supply cell model (B) is configured by arranging a power supply cell 69 at an actual position of an integrated circuit device, adding an external power supply (VSS) 70 and a bonding wire / lead frame 71, and includes a power supply wiring sub model 72. Connected to. As described above, the power supply cell connects the power supply terminal on the package and the power supply wiring network inside the integrated circuit device. Although the voltage value of the voltage source connected for each power supply type is different, the structure is the same. Have been. The power cells 65 and 69 are virtual cells that are merely connection points.
[0054]
As described above, the input / output submodels such as the input cell model, the output cell model, the input / output cell model, and the power supply cell model express the vicinity of the input / output cell of the actual integrated circuit device in detail. By creating an input / output submodel, it is possible to analyze the details of the power supply noise near the input / output cells.
[0055]
FIG. 17 is a conceptual diagram of an integrated circuit device model for power supply noise analysis created by the sub-model coupling unit 12. In FIG. 17, reference numeral 73 denotes a semiconductor device (integrated circuit device). Power supply wiring sub-models 30, 31, an internal capacitance sub-model 32, and an internal current consumption sub-model 33 are created in a square portion 74. , The output cell model 76, the input / output cell model 77, and the power supply cell models 78 and 79 are respectively created at the positions of the corresponding external pins (external terminals) 34P, 43P, 52P, 65P and 69P of the integrated circuit chip. Although not shown, the power supply cell models 78 and 79 are created at a plurality of locations for each power supply corresponding to the external power supply terminals 78P and 79P of the actual integrated circuit device. Further, models 75, 76, and 77 are also created at positions corresponding to the signal terminals 34P, 43P, and 52P.
[0056]
In the present embodiment, an example is described in which a peripheral-type package having external terminals provided on an outer peripheral portion is used. It is also possible to similarly create an integrated circuit device model for power supply noise analysis for a flip-chip type integrated circuit device arranged at an arbitrary position inside the integrated circuit device.
[0057]
(2) Power Pin Current Waveform Information Generation Step P2
As described above, what is shown in FIG. 17 is the integrated circuit device model F3. Therefore, as shown in FIG. 3, the operation of the integrated circuit device model is simulated (S12) to generate current waveform information F5 generated at the plurality of power pins 78P and 79P. Specifically, an integrated circuit device model is provided to a commercially available H-spice simulator, and an internal consumption current 33, an external signal of an input cell, an output cell, and an input / output cell, an internal signal, an input / output switching control signal, and the like are provided. Perform a simulation. The operation simulation can reproduce an operation in which power supply noise is generated in the power supply wiring inside the integrated circuit device and the power supply noise propagates to the power supply plane of the printed circuit board via the power supply pin. As a result, current waveform information F5 of the power supply pin connected to each power supply cell can be extracted. The propagation of the power supply noise to the printed circuit board can be expressed by the current waveform information.
[0058]
18 and 19 are diagrams illustrating examples of power supply noise analysis results using a power supply noise analysis integrated circuit device model created using the present embodiment. In this example, the simultaneous switching of the gates occurs, the simultaneous switching of the input / output cells occurs, and the simultaneous switching of the logic gates occurs locally at the center of the integrated circuit device.
[0059]
FIG. 18 is a voltage waveform graph of the power supply wiring near the center of the integrated circuit device of the VDD wiring and the VSS wiring. During power supply noise analysis, the current consumption in the logic gate and the simultaneous switching of the input and output cells are set, so the observed power supply noise depends on the power supply on each power supply wiring in the presence of both these effects. It is noise.
[0060]
According to the power supply noise analysis result, it is understood that both in-phase noise and anti-phase noise are generated between the VDD wiring and the VSS wiring, that is, between the power supplies of the logic gates inside the integrated circuit device. The main cause of common-mode noise is simultaneous switching of input / output cells, and the main cause of negative-phase noise is simultaneous switching of logic gates.
[0061]
19 is a graph showing the voltage distribution of the VSS wiring of the entire integrated circuit device. FIG. 19A shows the time point 0 on the graph shown in FIG. 18, and FIG. 19B shows the time point 2.475 ns on the graph shown in FIG. Is shown. From FIG. 19B, it can be seen that the amplitude of the power supply noise increases due to local current consumption at the center of the integrated circuit device.
[0062]
In this way, by collecting the power supply noise analysis results at each time in the order of time and creating a moving image, it is possible to observe where power supply noise occurs inside the integrated circuit device and how it propagates to the surroundings. It is also possible to check the range in which the noise reduction effect of the decoupling capacitor is effective.
[0063]
As described above, in the present embodiment, a power supply wiring submodel, an internal capacitance submodel, an internal current consumption submodel, and an input / output submodel are created for an integrated circuit device to be analyzed for power supply noise. Various parameter values given to the model can be set in consideration of design specifications or values extracted from actual layout information, including flip-chip type integrated circuit devices and macros with different operating voltages Such an integrated circuit device, or an integrated circuit device in which power supply wiring is not uniform, such as an integrated circuit device in which an internal ground line is intentionally divided, can be modeled with high accuracy.
[0064]
In addition, simultaneous switching noise of input / output cells and simultaneous switching noise of logic gates can be analyzed at the same time, so that simultaneous switching noise caused by input / output cells and simultaneous switching noise caused by logic gates exist. The generation process and the spatial distribution of the power supply noise of the entire integrated circuit device can be expressed, and the manner in which the delay of the input / output cell changes due to the power supply noise can be observed.
[0065]
In addition, since the power supply wiring sub-model is created for each type of power supply wiring in units of a grid-divided integrated circuit device to be analyzed for power supply noise, the model is individually modeled according to the type and location of the power supply wiring. Since the minimum unit of the circuit model is a circuit composed of a cross-shaped resistor and inductance, it is necessary to set the values estimated by the designer as the resistance and inductance values of this circuit. Alternatively, a value extracted from the actual layout can be set, and the difference depending on the location of the wiring shape can be expressed as a distribution constant, so that a detailed power supply network analysis can be performed.
[0066]
The internal capacitance submodel is a model of the capacitance existing in the plane represented by the power supply wiring submodel of interest, including the capacity between the power supply wirings and the power supply wiring when the power supply wirings are divided in a grid pattern. And the capacitance of the decoupling capacitor intentionally placed by the designer.Therefore, the capacitance distribution due to the difference in the placement density of the power supply wiring, logic gate, and decoupling capacitor is considered. Variations can also be expressed.
[0067]
In addition, since the internal current consumption submodel models the current consumption in the plane represented by the power supply wiring submodel of interest, differences in the arrangement density of logic gates inside the integrated circuit device and current consumption for each macro Can be modeled, and variations in current consumption inside the integrated circuit device can be expressed.
[0068]
Further, since the input / output submodel expresses in detail the vicinity of the input / output cells of the actual integrated circuit device, it is possible to analyze the details of the power supply noise near the input / output cells. Furthermore, since the input / output cell model in the input / output sub-model can express dynamic switching between the input mode and the output mode, it is also possible to analyze noise generated when the operation is switched. .
[0069]
Further, the power supply model can model power supply pins for each of a plurality of systems of power supplies, and can further model a plurality of power supply pins arranged in an integrated circuit device including their position information. Current waveform information generated at a plurality of power pins of a plurality of power systems of a circuit device can be extracted with high accuracy.
(3) Printed circuit board model generation step P3
Next, based on the printed circuit board layout information F6 and the power pin position information F7 of the integrated circuit device on the printed circuit board, a plurality of power plane information and current source information arranged at the positions of the plurality of power pins connected thereto are obtained. Is generated (S14).
[0070]
FIG. 20 is a diagram illustrating an example of the printed circuit board layout information F6. The printed circuit board layout information F6 includes plane information 100 for external power supply VDE, plane information 102 for internal power supply VDD, plane information 104 for ground VSS, and component arrangement information 106. Each of the plane information 100, 102, and 104 includes a power plane pattern and power pin arrangement information 101 of an integrated circuit device connected to the power plane. Further, the component arrangement information 106 includes position information of components mounted on a printed circuit board as EMI countermeasures such as the integrated circuit device 107 and a bypass capacitor 108 provided accompanying the integrated circuit device 107.
[0071]
FIG. 21 is a diagram illustrating an example of the power supply pin information F7 of the integrated circuit device. The power pin information F7 includes position information of a plurality of power pins for a plurality of power supplies provided in the integrated circuit device. Further, the position information of the signal pin is also included.
[0072]
FIG. 22 is a configuration diagram of a printed circuit board model corresponding to the printed circuit board of FIG. The ground plane VSS arranged on the entire surface of the printed circuit board, the internal power supply plane VDD and the external power supply plane VDE arranged in a partial area of the printed circuit board, and the integrated circuit device LSI mounted thereon are shown in FIG. Is shown in FIG. In the example of FIG. 22, a bypass capacitor 108 is provided between the power supply planes VDD and VDE, and a current source 110 of a power supply pin is provided between the ground plane VSS and the external power supply plane VDE. FIG. 22 also shows an outline of a model of the integrated circuit device to be mounted.
[0073]
Returning to FIG. 3, a printed circuit board model F8 is generated in the printed circuit board model creation step S14. FIG. 23 is a diagram illustrating an example of a printed circuit board model. The printed circuit board model includes power supply planes VDE and VSS in the printed circuit board, current sources 110 corresponding to a plurality of external pins of the integrated circuit device LSI, and mounted components such as a bypass capacitor 108 provided between the power supply planes. And component information that affects the generation of an electromagnetic field.
(4) Electromagnetic field intensity generation step P4
The current waveform information of the power pin extracted in the power pin current waveform information generating step P2 is given to the plurality of current sources of the printed circuit board model shown in FIG. 23, and the electromagnetic field analysis simulation is performed (S16). In this electromagnetic field analysis simulation, for example, by solving Maxwell's electromagnetic equation, the electromagnetic field intensity can be obtained for each frequency generated via the power plane of the printed circuit board. An electromagnetic field is generated when power supply noise resonates on a printed circuit board. The resonance frequency of the printed circuit board largely depends on the shape of the power supply plane and EMI countermeasure components. When the resonance frequency of the printed circuit board matches the frequency of the power supply noise, the electromagnetic field strength increases.However, by changing the position of the bypass capacitor and its capacitance, the resonance frequency of the printed circuit board changes and the power supply noise itself is suppressed. In addition, the electromagnetic field strength can be reduced.
[0074]
FIG. 24 is a flowchart for designing a printed circuit board using the EMI noise analysis method. When a certain printed circuit board is designed first, a printed circuit board model F8 is generated from the design information F6, F7. This printed circuit board model F8 is as described with reference to FIG. Therefore, an electromagnetic field analysis simulation S16 is performed to extract an electromagnetic field distribution F9 generated from the printed circuit board. From the extracted electromagnetic field distribution F9, it is checked whether or not the electromagnetic field intensity is equal to or smaller than the EMI allowable value (S20). If the allowable value is not satisfied, add or relocate a bypass capacitor, add or relocate a snubber circuit, change the shape of the power plane, change the number of layers of the power plane, etc. (S22), a redesigned printed circuit board model F8 is generated.
[0075]
Then, an electromagnetic field analysis simulation S16 is performed on the newly redesigned printed circuit board model F8, and it is checked whether the EMI noise satisfies an allowable value. Then, the redesign S22 is repeated until the allowable value is satisfied. If the EMI noise level cannot be reduced below the allowable value due to a worst-case change in the printed circuit board model, the integrated circuit device must be redesigned.
[0076]
According to the design method shown in FIG. 24, it is not necessary to perform a complicated procedure such as creating an actual printed circuit board, mounting an integrated circuit device, and measuring EMI noise. The standard level of EMI noise can be satisfied, and the overall cost can be reduced.
[0077]
As described above, the embodiments are summarized as follows.
[0078]
(Supplementary Note 1) In a method of performing EMI noise analysis using a board model in which an integrated circuit chip having a plurality of power supply pins and a built-in integrated circuit chip is mounted in a package,
Generating an integrated circuit device model having an internal power supply of the integrated circuit chip, an internal circuit model connected between the internal power supplies, and a plurality of power pins connected to the common power plane on the board and the internal power supply The process of
Generating current waveform information generated in the plurality of power pins by simulating the operation of the integrated circuit device model;
The operation simulation of a board model having a plurality of power supply planes and a plurality of current sources arranged at the positions of the plurality of power supply pins connected thereto is performed by giving the current waveform information to the plurality of current sources. Generating an electromagnetic field generated from a power plane.
[0079]
(Supplementary Note 2) In Supplementary Note 1,
An EMI noise analysis method, wherein a plurality of power pins of the integrated circuit device model correspond one-to-one to a plurality of power pins of an actual integrated circuit device.
[0080]
(Supplementary Note 3) In Supplementary Note 1,
An EMI noise analysis method, wherein a plurality of power supply pins of the integrated circuit device model are provided corresponding to a ground power supply, a first power supply, and a second power supply, respectively.
[0081]
(Supplementary Note 4) In Supplementary Note 1,
The EMI noise analysis method, wherein the board model further has a coupling capacitance connected between the power planes together with its position information.
[0082]
(Supplementary Note 5) In Supplementary Note 1,
In the integrated circuit device model, further, the internal power supply is an internal power supply network, and the internal circuit model includes a plurality of current consumption sources and inter-power supply capacitances connected between the internal power supply networks, and a distribution on the board. An EMI noise analysis method having a constant line and a plurality of input or output cells connected to the internal power supply network.
[0083]
(Supplementary Note 6) In Supplementary Note 5,
The integrated circuit device model is formed by connecting a network of inductances and resistances determined corresponding to a plurality of regions into which the internal power supply network is divided, and wherein the current consumption source and the inter-power supply capacitance are the plurality of regions. Characterized by being provided as a current source and a capacity respectively generated in the area of
[0084]
【The invention's effect】
As described above, according to the present invention, EMI noise can be extracted with high accuracy by simulation, and the design cost of a printed circuit board on which an integrated circuit device is mounted can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a conventional LSI circuit model.
FIG. 2 is a diagram showing a printed circuit board model for obtaining EMI noise using a conventional LSI circuit model.
FIG. 3 is a flowchart of an EMI noise analysis method according to the present embodiment.
FIG. 4 is a configuration diagram of a device for creating an integrated circuit device model.
FIG. 5 is a configuration diagram of a power supply wiring sub-model creating means 8;
FIG. 6 is a configuration diagram of an internal capacitance sub-model creating means 9;
FIG. 7 is a configuration diagram of an internal current consumption sub-model creating means 10;
FIG. 8 is a configuration diagram of an input / output submodel creation unit 11;
FIG. 9 is a flowchart of an integrated circuit device model creation method.
FIG. 10 is a conceptual diagram of a power supply wiring sub-model created by a power supply wiring sub-model creation means 8;
FIG. 11 is a conceptual diagram of an internal capacitance sub-model created by an internal capacitance sub-model creating means 9;
FIG. 12 is a conceptual diagram of an internal current consumption submodel created by an internal current consumption submodel creation unit 10;
FIG. 13 is a conceptual diagram of an input cell model created by an input / output submodel creation unit 11;
FIG. 14 is a conceptual diagram of an output cell model created by an input / output submodel creating unit 11;
FIG. 15 is a conceptual diagram of an input / output cell model created by an input / output submodel creation unit 11;
FIG. 16 is a conceptual diagram of a power supply cell model created by an input / output sub-model creation unit 11;
FIG. 17 is a conceptual diagram of an integrated circuit device model for power supply noise analysis created by the sub-model coupling unit 12.
FIG. 18 is a diagram illustrating an example of a power supply noise analysis result using an integrated circuit device model for power supply noise analysis.
FIG. 19 is a diagram illustrating an example of a power supply noise analysis result using an integrated circuit device model for power supply noise analysis.
FIG. 20 is a diagram illustrating an example of printed circuit board layout information F6.
FIG. 21 is a diagram illustrating an example of power supply pin information F7 of the integrated circuit device.
FIG. 22 is a configuration diagram of a printed circuit board model corresponding to the printed circuit board of FIG. 20;
FIG. 23 is a diagram illustrating an example of a printed circuit board model.
FIG. 24 is a flowchart of designing a printed circuit board using an EMI noise analysis method.
[Explanation of symbols]
F3: integrated circuit device model, F5: current waveform information,
F8: Board model, printed circuit board model, F9: Electromagnetic field distribution

Claims (5)

A method for performing EMI noise analysis using a board model having an integrated circuit device having a plurality of power supply pins with a built-in integrated circuit chip in a package,
Generating an integrated circuit device model having an internal power supply of the integrated circuit chip, an internal circuit model connected between the internal power supplies, and a plurality of power pins connected to the common power plane on the board and the internal power supply The process of
Generating current waveform information generated in the plurality of power pins by simulating the operation of the integrated circuit device model;
The operation simulation of a board model having a plurality of power supply planes and a plurality of current sources arranged at the positions of the plurality of power supply pins connected thereto is performed by giving the current waveform information to the plurality of current sources. Generating an electromagnetic field generated from a power plane. In claim 1,
An EMI noise analysis method, wherein a plurality of power pins of the integrated circuit device model correspond one-to-one to a plurality of power pins of an actual integrated circuit device. In claim 1,
An EMI noise analysis method, wherein a plurality of power supply pins of the integrated circuit device model are provided corresponding to a ground power supply, a first power supply, and a second power supply, respectively. In claim 1,
The EMI noise analysis method, wherein the board model further has a coupling capacitance connected between the power planes together with its position information. In claim 1,
In the integrated circuit device model, further, the internal power supply is an internal power supply network, and the internal circuit model includes a plurality of current consumption sources and inter-power supply capacitances connected between the internal power supply networks, and a distribution on the board. An EMI noise analysis method having a constant line and a plurality of input or output cells connected to the internal power supply network.

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