JP2004355670A - Nonvolatile semiconductor storage device, write/reset method thereof, and read method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device capable of high-speed operation with low power consumption. <P>SOLUTION: A nonvolatile memory cell 30 connects one end of a variable resistance device the resistance value of which changes with voltage application and holds the resistance value even after the voltage application with the drain of a selection transistor. In a memory array 1, the memory cell 30 connects another adjoining memory cell on one side in the row direction and the sources of the selection transistors with the common 1st column selection lines C0, C1, and also connects another adjoining memory cell on the other side in the row direction and the ends of the variable resistance devices with the common 2nd column selection lines B1, B2. Each row of the memory cells 30 arrayed in the row direction is provided with two row selection lines W0, W1. The gate of the selection transistor of one of the adjoining memory cells arrayed in the row direction is connected to one of the two row selection lines, and the gate of the selection transistor of the another memory cell is connected to the other side of the two row selection lines. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device in which a plurality of nonvolatile memory cells each including a variable resistance element for storing information by a change in electrical resistance due to an electrical stress and a selection transistor are arranged in a row direction and a column direction, respectively. More specifically, the present invention relates to a memory cell array structure of the nonvolatile semiconductor memory device and a method of writing / resetting and reading out the memory cells.
[0002]
[Prior art]
2. Description of the Related Art Non-volatile semiconductor memory devices that retain their stored contents even when power supply is cut off have formed a large market, mainly for portable small-sized devices such as mobile phones and digital still cameras. I have. At present, flash EEPROMs are mainly used as nonvolatile semiconductor memory devices. However, flash EEPROMs require a long processing time for data writing and erasing operations. Since a high voltage is required, there is a problem in that it is disadvantageous in terms of power consumption for applications in which data rewriting operation frequently occurs.
[0003]
Against this background, the development of a non-volatile semiconductor storage device that combines the convenience of non-volatility with the data rewriting speed of a volatile memory such as an SRAM or DRAM and a low-cost new storage mechanism has been developed. It is thriving. As such a new nonvolatile semiconductor memory device, a variable resistance nonvolatile semiconductor using a nonvolatile memory cell whose resistance value changes due to an electrical stress such as voltage application and holds the resistance value after voltage application in a nonvolatile manner. Storage devices have been proposed.
[0004]
As the variable resistance nonvolatile semiconductor memory device, a 1T1R (one transistor + 1 resistance element) type memory cell structure disclosed in the specification of a patent application (Japanese Patent Application No. 2002-185234) filed by the present applicant was employed. There is a nonvolatile semiconductor memory device. The memory cell disclosed in the specification of the patent application includes one transistor and one variable resistance element (CMR [Colossal Magnetoresistance] memory element), and thus includes a combination of one transistor and one resistance element. The configured memory cell is called a 1T1R type.
[0005]
FIG. 19 shows an equivalent circuit of the 1T1R memory cell 40. In the memory cell 40, a variable resistance element (programmable CMR memory element) 42 is connected to the source or drain electrode of the selection transistor 41, a word line 43 is connected to its gate electrode, and a common source line 44 is connected to the other electrode. Line 45 is connected. The word lines 43 and the common source lines 44 are arranged in a direction orthogonal to the bit lines 45. That is, a structural feature is that the word lines 43 and the common source lines 44 are arranged in parallel.
[0006]
The variable resistance element 42 which is a memory carrier as a nonvolatile memory cell shown in FIG. 19 has a characteristic that a resistance value continuously changes reversibly when a voltage is applied between terminals of the variable resistance element 42. . After applying a voltage between the terminals of the variable resistance element 42, the variable resistance element 42 can maintain the changed resistance value even after the voltage application is stopped. That is, the data can be stored in a nonvolatile manner by using the resistance value as the storage information.
[0007]
The variable resistance element 42 can be formed using, for example, a thin film material having a perovskite-type crystal structure, in particular, a giant magnetoresistance (CMR) material or a high temperature superconductivity (HTSC) material. Patent Document 1 listed below proposes a method of changing one or more short electric pulses to a thin film or a bulk composed of a thin film material having such a perovskite-type crystal structure to change the electric characteristics. Have been. The intensity of the electric field and the current density due to the electric pulse are large enough to change the physical state of the material, and conversely, it is sufficient if the energy is low enough not to destroy the material itself. The pulse may be of either positive or negative polarity. Further, by repeatedly applying the electric pulse a plurality of times, the material characteristics can be further changed. As a material having a perovskite-type crystal structure exhibiting a giant magnetoresistance and a high-temperature superconductivity, for example, Pr _1-X Ca _X MnO ₃ (0 <x <1), La _1-X Ca _X MnO ₃ (0 <x <1), Nd _1-X Sr _X MnO ₃ (0 <x <1) or the like may be used.
[0008]
The above Pr _1-X Ca _X MnO ₃ (0 <x <1), La _1-X Ca _X MnO ₃ (0 <x <1), Nd _1-X Sr _X MnO ₃ When a pulse voltage is applied to both terminals of the variable resistance element 42 formed using (0 <x <1) or the like, the resistance value of the variable resistance element 42 continuously changes according to the number of times the pulse voltage is applied. .
[0009]
Thereby, the nonvolatile memory cell 40 provided with the variable resistance element 42 as a memory carrier can store the multi-value information by continuously changing the threshold voltage according to the amount of charge injected into the floating gate. By controlling the amount of change in the resistance value of the variable resistance element 42, not only the binary information but also the multi-valued information having three or more values can be stored.
[0010]
FIG. 20 shows a configuration diagram of a memory cell array using a conventional memory cell 40. The memory cell array 20 has a configuration in which two adjacent memory cells 40 are commonly connected to each other so as to be folded around the common source line. The configuration of this memory cell array is characterized in that word lines and common source lines are arranged in parallel.
[0011]
FIG. 21 schematically shows a write operation for a specific memory cell in the memory cell array 20. Consider a case where a write operation is performed on the memory cell A1 shown in FIG. When writing is performed on the memory cell A1 to be written, as shown in FIG. 21, a high-level voltage is applied to the bit line B1, and the gate of the selection transistor of the memory cell A1 (word line W1 ), And a low-level voltage is applied to the common source line C1 connected to the memory cell A1. As a result, a potential difference between the high-level voltage and the low-level voltage is applied to both ends of the variable resistance element in the memory cell A1 in the direction shown by the arrow in the figure (the side with the arrow is low level), and the resistance of the variable resistance element is reduced. The value can be increased from a low resistance level to a high resistance level.
[0012]
In this case, for a non-selected memory cell that is not a write target, that is, is not accessed, the selection transistor is turned off by lowering the potential of another word line so that no voltage is applied to the variable resistance element. At the same time, the potentials of the other common source lines (not shown) and the bit lines also maintain a low level. The above is the outline of the write operation to the memory cell.
[0013]
Next, FIG. 22 schematically shows a reset operation for a specific memory cell in the memory cell array 20. Here, the reset operation means an operation of returning the resistance value of the variable resistance element at the high resistance level to the low resistance level. Note that the reset operation may be referred to as an erase operation.
[0014]
When a reset operation is performed on the memory cell A1 to be reset, a low-level voltage is applied to the bit line B1 as shown in FIG. A high-level potential is applied to (word line W1), and a high-level voltage is applied to common source line C1 connected to memory cell A1 to be reset. Thereby, the potential difference between the high-level and low-level voltages is applied to both ends of the variable resistance element in the memory cell A1 in the direction indicated by the arrow in the figure (the side with the arrow is the low level, and the write operation shown in FIG. Is applied in the opposite direction), and the resistance value of the variable resistance element can be lowered from the high resistance level to the low resistance level.
[0015]
In this case, the selection transistor is turned off by lowering the potential of the other word line so that no voltage is applied to the variable resistance element for a non-selected memory cell that is not a reset target, that is, is not accessed. At the same time, the potential of another common source line (not shown) also maintains a low level. However, all the potentials of the other bit lines connected to the unselected memory cells that are not accessed must be kept at a high level. This is because the selection transistors of other unselected memory cells to which the word line W1 is commonly connected, for example, the selection transistors of the memory cells A2 and A3 are also turned on, so that the potential of the bit line connected to these is changed to the common source line. If the same high-level potential as that of C1 is not set, a potential difference occurs between both ends of the variable resistance element in each memory cell, which may change the resistance value of the variable resistance element. The above is the outline of the reset operation of the memory cell.
[0016]
FIG. 23 is a diagram schematically showing a signal flow at the time of the reset operation for the selected memory cell A1 to be subjected to the reset operation, including the non-accessed unselected memory cells A0, A2, A3, and A4 in the vicinity thereof. It is.
[0017]
As shown in FIG. 23, for memory cells A0, A2, A3, and A4 that are not accessed during the reset operation, the same high level potential as the high level supplied from common source line C1 is applied to bit lines B0, B2, and B3. , B4. This is a measure for eliminating the potential difference between both ends of the variable resistance elements in the non-selected unselected memory cells A0, A2, A3, and A4 so that the resistance values do not change.
[0018]
Next, FIGS. 24A and 24B schematically show a read operation for a specific memory cell in the memory cell array 20. FIG. Arrows in FIGS. 24A and 24B show a flow (current path) of a signal for reading a resistance value in the 1T1R type memory cell, and a main part of the read circuit as a peripheral circuit of the memory cell array 20. It has been described. That is, in FIGS. 24A and 24B, the read circuit includes a sense amplifier 22 that determines the resistance value of the variable resistance element as a logical value, and a load transistor 21 that drives a current to the current path. Have been.
[0019]
FIG. 24A shows an example in which one input of the load transistor 21 and the sense amplifier 22 is connected to the bit line side, and FIG. 24B shows one example in which one input of the load transistor 21 and the sense amplifier 22 is connected to the common source line C1. The example connected to the side is shown. In FIG. 24A, when, for example, about 1 V is applied to the load transistor 21, the current driven from the load transistor is transferred from the bit line B1 to the memory cell A1 to be read and the common source line C1 to which a low-level potential is applied. A current path that reaches the ground potential is formed. Since two resistive elements, that is, the load transistor 21 and the memory cell A1 (combined resistance of the variable resistance element and the selection transistor) are connected in series to this current path, a connection node to the sense amplifier 22, which is a connection point between the two, is connected. The potential of N1 is a value obtained by resistance division by these two resistive elements. That is, assuming that the resistance value of the load transistor 21 is constant, the input potential of the sense amplifier 22 is determined depending on the resistance value of the memory cell A1. Here, the resistance value of the memory cell A1 changes depending on whether the resistance value of the variable resistance element is a high resistance level or a low resistance level.
[0020]
Then, the potential of the connection node N1 with the bit line B1 and the reference voltage V _REF Are compared by the sense amplifier 22 to determine the logical level of the stored data from the resistance value of the variable resistance element.
[0021]
In FIG. 24B, when, for example, about 1 V is applied to the load transistor 21, the current driven from the load transistor 21 is supplied from the common source line C1 to the memory cell A1 to be read and the bit applied with the low-level potential. A current path to the ground potential via the line B1 is formed.
[0022]
Also in this case, similarly to FIG. 24A, the potential of the connection node N1 to the common source line C1 and the reference level V _REF Is compared by the sense amplifier 22, the logical level of the stored data can be determined from the resistance value of the variable resistance element.
[0023]
[Patent Document 1]
U.S. Pat. No. 6,204,139
[0024]
[Problems to be solved by the invention]
As described with reference to FIG. 23, in a memory cell array using a conventional memory cell (see FIG. 19), when a reset operation is performed on a certain memory cell, a bit connected to an unselected memory cell is A high level potential needs to be applied to all of the lines. That is, as shown in FIG. 23, since a high-level potential is applied to the common source line connected to the selected memory cell to be reset, the resistance value of the non-selected non-selected memory cell is not changed. In order to maintain the voltage, a potential difference must not be generated between both ends of the unselected memory cell, and a high-level voltage must be applied to bit lines other than the bit line connected to the selected memory cell.
[0025]
At this time, if the storage capacity of the memory cell array is large, the number of bit lines, the number of memory cells connected to the same bit line, or both increase, so that the parasitic capacitance of the bit line supplying a high-level potential increases. Then, the charging time (time during which the high-level potential is supplied to the bit line and the bit line reaches the high-level potential) increases, and the time required for the reset operation increases accordingly.
[0026]
Also, an increase in the number of bit lines, the number of memory cells connected to the same bit line, or both increases the parasitic capacitance of the bit line that supplies a high-level potential, and is not accessed during the reset operation. Current consumption due to charging and discharging of all bit lines increases.
[0027]
In addition, there is also a circuit design problem that the control circuit becomes complicated because the applied voltage levels to the accessed bit lines and the unaccessed bit lines are different between the write operation and the reset operation.
[0028]
Regarding the read operation, in the above-described conventional technique, a load transistor (load resistor) is provided, and a connection node of a resistance component formed in a current path passing through a memory cell to be accessed (a load transistor and a memory cell). The logic level is determined using the potential of the connection node) as a measurement point.
[0029]
However, in the read method in which the logic value is determined by converting the resistance value into a voltage, the timing at which the logic level should be determined is determined by the resistance value of the variable resistance element of the memory cell and the combined resistance of the selection transistor and the load transistor (load transistor). Resistance) and the time constant of the resistance including the parasitic resistance value in the current path and the capacitance in the current path, that is, the time required to charge and discharge the current path.
[0030]
In this conventional reading method, the timing for determining the resistance value of the variable resistance element, that is, the time required for the determination depends on the time constant of the current path. There is a problem that an increase in the value causes a delay in access time.
[0031]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device which can solve the above problems and can operate at high speed with low power consumption.
[0032]
[Means for Solving the Problems]
In order to achieve this object, a nonvolatile semiconductor memory device according to the present invention includes a plurality of nonvolatile memory cells arranged in a row direction and a column direction, respectively, and a predetermined memory cell or a memory cell group is selected from among them. A nonvolatile semiconductor memory device having a memory cell array in which a plurality of row selection lines are arranged in a row direction and a plurality of first column selection lines and a plurality of second column selection lines are arranged in a column direction. Each of the memory cells includes a variable resistance element that stores information by a change in electric resistance due to electric stress and a selection transistor, and connects one end of the variable resistance element to a drain of the selection transistor. The other end of the variable resistance element and the source of the selection transistor form two column connection terminals of the memory cell, and the gate of the selection transistor is connected to a row connection terminal. Forming, in the memory cell array, connecting one of the column connection terminals to another memory cell adjacent on one side in the row direction to the common first column selection line; The other of the memory cells adjacent to the other side in the direction and the other of the column connection terminals are connected to a common second column selection line, and two rows are provided in each row of the memory cells arranged in a row direction. A selection line is provided, and in the two memory cells adjacent to each other in the row direction, the row connection terminal of one of the memory cells is connected to one side of the two row selection lines, and the other of the memory cells is connected to one of the two row selection lines. The row connection terminal is connected to the other side of the two row selection lines.
[0033]
Further, in the semiconductor device according to the present invention having the above characteristics, the variable resistance element is formed of an oxide having a perovskite crystal structure containing manganese.
[0034]
According to the semiconductor device of the present invention having the above characteristics, at the time of executing the reset operation, the non-selected bit lines which are not accessed only need to keep the low level, and an increase in current consumption and an increase in access time can be avoided. That is, when a reset operation is performed using a conventional memory cell (see FIG. 19) and a memory cell array (see FIG. 20), a high-level voltage is applied to all unselected bit lines that are not accessed. The necessity causes an increase in current consumption and an increase in reset operation time. However, according to the semiconductor device of the present invention, a high-level voltage is applied to all unselected bit lines that are not accessed. Since there is no need, the current consumption can be reduced and the reset operation time can be shortened accordingly.
[0035]
In order to achieve the above object, a method for writing and resetting a nonvolatile semiconductor memory device according to the present invention comprises the steps of: arranging a plurality of nonvolatile memory cells in a row direction and a column direction, respectively; In order to select a group, a nonvolatile memory cell array having a plurality of row selection lines arranged in a row direction and a plurality of first column selection lines and a plurality of second column selection lines arranged in a column direction, respectively. In a semiconductor memory device, each of the memory cells includes a variable resistance element and a selection transistor that store information by a change in electric resistance due to an electric stress, and one end of the variable resistance element and a drain of the selection transistor. And the other end of the variable resistance element and the source of the selection transistor form two column connection terminals of the memory cell, and the selection transistor The gate of the memory cell forms a row connection terminal, and in the memory cell array, the memory cell is connected to another memory cell adjacent to one side in a row direction and the first column common to one of the column connection terminals. A memory cell connected to a column select line, the other memory cell adjacent to the other side in the row direction, and the other of the column connection terminals connected to a common second column select line; A method of performing at least one of a data write operation and a reset operation on one or more selected memory cells, wherein the row select line connected to the one or more selected memory cells is A row selection voltage for turning on a selection transistor is applied, and the write or reset operation is applied to the first column selection line connected to the selected one or more memory cells. A write voltage or a reset voltage according to the value of the data according to the above is applied, and the row selection voltage is applied to the second column selection line connected to the selected one or more memory cells. And applying a voltage pulse having a predetermined voltage amplitude that transitions at least once from a low voltage level to a high voltage level or from a high voltage level to a low voltage level, and the write voltage is applied to the first column selection line. In the case, when the voltage level of the voltage pulse is different from the write voltage during the row select voltage application period, the write operation is performed, and the reset voltage is applied to the first column select line. In the case where the voltage level of the voltage pulse is at a voltage level different from the reset voltage during the application period of the row selection voltage, A reset operation is performed.
[0036]
Here, in the writing / resetting method for the nonvolatile semiconductor memory device according to the present invention having the above characteristics, the voltage pulse transits from a low voltage level to a high voltage level and returns to a low voltage level, or from a high voltage level. Preferably, one or more voltage pulses transition to a low voltage level and back to a high voltage level.
[0037]
According to the write / reset method of the nonvolatile semiconductor memory device of the present invention having the above characteristics, the write operation and the reset operation are performed by inputting the voltage pulse to the bit line without distinction between the write operation and the reset operation. It is possible to do. Therefore, unlike the related art, there is no need for a control circuit for discriminating between the write operation and the reset operation and then inputting the voltage level applied to the bit line separately, and the control circuit can be simplified accordingly.
[0038]
In order to achieve this object, a method for reading a nonvolatile semiconductor memory device according to the present invention includes a method of arranging a plurality of nonvolatile memory cells in a row direction and a column direction, respectively, and arranging a predetermined memory cell or a memory cell group from among them. A nonvolatile semiconductor memory having a memory cell array in which a plurality of row selection lines are arranged in a row direction for selection, and a plurality of first column selection lines and a plurality of second column selection lines are respectively arranged in a column direction. An apparatus, wherein each of the memory cells includes a variable resistance element that stores information by a change in electric resistance due to an electric stress and a selection transistor, and connects one end of the variable resistance element to a drain of the selection transistor. The other end of the variable resistance element and the source of the select transistor form two column connection terminals of the memory cell, and the gate of the select transistor is connected. Forms a row connection terminal, and in the memory cell array, the memory cell is connected to another memory cell adjacent to one side in a row direction and the first column selection line is connected to one of the column connection terminals. And the other of the memory cells adjacent to the other side in the row direction and the other of the column connection terminals are connected to a common second column selection line. A method of reading data from one or more memory cells, comprising: applying a row selection voltage that turns on the selection transistor to the row selection line connected to the selected one or more memory cells; One side of the first column selection line and the second column selection line connected to the selected one or more memory cells is precharged to a predetermined precharge voltage, and after the precharge, Applying a predetermined read voltage to the other side of the first column selection line and the second column selection line connected to the selected one or the plurality of memory cells, and setting the voltage level of the first column selection line to In a transient state in which the precharge voltage changes toward the read voltage, it is detected that a change in voltage varies depending on the resistance state of the variable resistance element of the memory cell.
[0039]
According to the method for reading a nonvolatile semiconductor memory device according to the present invention having the above characteristics, since a load transistor is not required in a read current path, it is possible to reduce a time constant required for charging in the read current path. In addition, the reading speed can be increased.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of a nonvolatile semiconductor memory device according to the present invention, a method of writing / resetting the same, and a method of reading the same (hereinafter, appropriately referred to as “the present invention device” and “the present invention method”) will be described with reference to the drawings.
[0041]
<First embodiment>
FIG. 1 shows a block diagram of the apparatus of the present invention. 1, a memory cell array 1 is configured using memory cells 30 shown by an equivalent circuit in FIG. As shown in FIG. 2, the memory cell 30 includes a variable resistive element 7 for storing information by a change in electric resistance due to an electric stress and a select transistor 6, and one end of the variable resistive element 7 and a select transistor formed of a MOSFET. The other end of the variable resistance element 7 and the source of the selection transistor 6 form two column connection terminals of the memory cell 30, and the first column selection line 9 (common source line or data ) And the second column selection line 10 (bit line), and the gate of the selection transistor 6 forms a row connection terminal and is connected to the row selection line 8 (word line).
[0042]
Here, the memory cell 30 is manufactured by using a well-known MOS integrated circuit manufacturing method. As shown in FIG. 2, in the memory cell 30 of the device of the present invention, the row selection line 8 (word line) includes the first column selection line 9 (common source line) and the second column selection line 10 (bit line). The first column selection line 9 (common source line) and the second column selection line 10 (bit line) are arranged in parallel to each other. In this sense, the equivalent circuit of the memory cell 30 shown in FIG. 2 also shows how to arrange the wirings 8 to 10 connected to the elements 6 and 7 constituting the memory cell 30. Note that the drain and source electrodes of the selection transistor 6 composed of MOSFETs are basically symmetrical because the ON current flows in both directions due to the difference in the applied voltage between the drain and source. The term “drain” or “source” is arbitrary, and in this specification, the function is equivalent even if the drain and source are inverted.
[0043]
Further, the variable resistance element 7 changes its electrical resistance due to the application of an electrical stress, and retains the changed electrical resistance even after the electrical stress is released. Is a CMR (Colossal Magnetoresistance) memory element formed of an oxide having a perovskite-type crystal structure containing manganese, for example, Pr _(1-x) Ca _x MnO ₃ , La _(1-x) Ca _x MnO ₃ Or La _(1-xy) Ca _x Pb _y MnO ₃ (However, any substance represented by x <1, y <1, x + y <1), for example, Pr _0.7 Ca _0.3 MnO ₃ , La _0.65 Ca _0.35 MnO ₃ , La _0.65 Ca _0.175 Pb _0.175 MnO ₃ And the like are formed by MOCVD, spin coating, laser ablation, sputtering, or the like.
[0044]
As shown in FIG. 3, the memory cell array 1 includes a plurality of memory cells 30 arranged in a row direction and a column direction, and a plurality of memory cells 30 extending in the row direction in order to select a predetermined memory cell or memory cell group from the memory cells. Are arranged, a plurality of first column selection lines 9 (common source lines C0, C1...) Extending in the column direction and a plurality of second column selection lines 10 (bits). ., And common source lines C0, C1... And bit lines B0 to B2... Are connected to peripheral function blocks as described later. I do.
[0045]
More specifically, as shown in FIG. 3, in the memory cell array 1, the memory cell 30 is connected to another memory cell 30 adjacent to one side in the row direction (extending direction of the word line) and the column connection terminal. Are connected to a common first column selection line 9 (common source lines C0, C1,...), And the other of the memory cells 30 adjacent to the other side in the row direction and the other of the column connection terminals are connected to a common first column selection line 9. It is connected to a two-column selection line 10 (bit lines B0, B1, B2,...). That is, two memory cells 30 adjacent to each other in the row direction are folded back around the common source lines C0, C1... Or the bit lines B0, B1, B2. B2... Are commonly connected and shared.
[0046]
Specifically, in FIG. 3, the source of the selection transistor 6 of the memory cell A0 (one of the column connection terminals) and the source of the selection transistor of the memory cell A1 (one of the column connection terminals) are connected to a common common source line C0. One terminal of the variable resistance element 7 of the memory cell A1 (the other of the column connection terminals) and one terminal of the variable resistance element 7 of the memory cell A2 (the other of the column connection terminals) are connected to the common bit line B1. Connecting. This connection is developed in the row direction and the column direction, and the memory cell array 1 is configured.
[0047]
Further, as shown in FIG. 3, two row selection lines 8 (word lines) are provided as a pair in each row of the memory cells 30 arranged in the row direction in the memory cell array 1, and are adjacent to each other in the row direction. The row connection terminal of one of the memory cells 30 (the gate of the selection transistor 6) is connected to one side of a pair of row selection lines (word lines), and the row connection terminal of the other memory cell 30 (the gate of the selection transistor 6). ) Is connected to the other side of the pair of row selection lines (word lines). That is, two memory cells 30 adjacent to each other in the row direction are arranged so as to be mirror-inverted with respect to each other, with the extension direction of the word lines W0 to W5.
[0048]
As a result, each memory cell 30 and the word line connect the row connection terminal (gate of the selection transistor 6) of the memory cell A0 in FIG. 3 to the word line W1, and connect the row connection terminal of the memory cell A1 (the selection transistor 6). The row connection terminals (gates of the selection transistors 6) of the memory cells 30 adjacent to each other in the row direction such that the gate is connected to the word line W0 are not connected to the same word line.
[0049]
Incidentally, in order to select and access a predetermined memory cell in the memory cell array 1 shown in FIG. 3, for example, only the bit line B1 connected to the memory cell A1, the common source line C0, and the word line W0 are accessed. By supplying a necessary potential and keeping all other bit lines, common source lines, and word lines at a low level potential, a desired memory cell A1 can be selected and accessed.
[0050]
That is, for example, since the word line W1 is held at a low level, the selection transistors 6 of the memory cells adjacent to both sides of the memory cell A1 to be accessed are all turned off, and the non-selected memories adjacent to both sides adjacent in the row direction are turned off. The cell is not affected by the potential supplied to the common source line C0 and the bit line B1. In other unselected memory cells commonly connected to the word line W0 connected to the memory cell A1 to be accessed, the selection transistor 6 is turned on, but the common source line connected to the unselected memory cell is Since both bit lines are held at the same low-level potential, there is no potential difference in the voltage across the variable resistance element of the non-selected memory cell, and the resistance value does not change. Therefore, the stored information is held. Only the memory cell A1 thus selected can be accessed.
[0051]
In FIG. 1, a row decoder 2 supplies a predetermined voltage to a word line Wi connected to a memory cell 30 to be accessed. The data driver 3 is a circuit that supplies a voltage corresponding to write data in accordance with a high-level or low-level signal externally supplied as a data signal when writing to a common source line Cj connected to the memory cell 30 to be accessed. The column decoder 5 selects a common source line Cj connected to the memory cell 30 to be accessed, and a high-level or low-level voltage output from the data driver 3 is supplied to the selected common source line Cj. Here, the selected common source line Cj is connected to an externally input data signal via the data driver 3 and the column decoder 5.
[0052]
On the other hand, at the time of reading, the data driver 3 generates about 1 V as a read voltage, and supplies the read voltage to the selected common source line Cj connected to the memory cell 30 to be accessed selected by the column decoder 5.
[0053]
The bit line driver 4 is a circuit that supplies a pulse voltage to the bit line Bk connected to the memory cell 30 to be accessed during a write operation and a reset operation. The column decoder 6 selects a bit line Bk connected to the memory cell 30 to be accessed, and a pulse voltage output from the bit line driver 4 is supplied to the selected bit line Bk.
[0054]
Next, referring to FIG. 4, a write operation to a desired memory cell and a control method therefor in the method of the present invention will be briefly described.
[0055]
It is assumed that a write operation (an operation of increasing the resistance value of the variable resistance element 7) is performed on the memory cell A in FIG. A high-level potential is applied from the bit line B1 connected to the memory cell A, and a low-level potential is applied to the common source line C0 connected to the memory cell A. Further, by applying a high-level potential to the word line W0 connected to the gate of the selection transistor 6 in the memory cell A, the selection transistor 6 is turned on, and as shown by an arrow in FIG. A current path to the common source line C0 is formed. Therefore, a low-level potential from the common source line C0 is applied to the lower electrode of the variable resistance element 7. A high-level potential from the bit line B1 is applied to the upper electrode of the variable resistance element 7. As a result, the resistance value of the variable resistance element 7 in the memory cell A increases, and the write operation is completed. During the write operation, the other word lines W1 to W5, the other bit lines B0 and B2, and the other common source line C1 are in a state of maintaining a low level potential.
[0056]
Next, a reset operation to a desired memory cell and a control method thereof in the method of the present invention will be briefly described with reference to FIG.
[0057]
It is assumed that a reset operation (an operation of reducing the resistance value of the variable resistance element 7) is performed on the memory cell A in FIG. A high level potential is applied from the common source line C0 connected to the memory cell A, and a low level potential is applied to the bit line B1 connected to the memory cell A. When a high-level potential is applied to the word line W0 connected to the gate of the selection transistor 6 in the memory cell A, the selection transistor 6 is turned on, and the common source line C0 is turned on as shown by an arrow in FIG. , A current path from bit line B1 to bit line B1 is formed. Therefore, a high-level potential from the common source line C0 is applied to the lower electrode of the variable resistance element 7. Further, a low-level potential from the bit line B1 is applied to the upper electrode of the variable resistance element 7. As a result, by applying a voltage in the opposite direction to that at the time of writing shown in FIG. 4 between the two electrodes of the variable resistance element 7 in the memory cell A, the resistance value decreases and the reset operation is completed. During the reset operation, similarly to the write operation, the other word lines W1 to W5, the other bit lines B0 and B2, and the other common source line C1 are in a state of holding the low-level potential.
[0058]
Here, a comparison between the case where the reset operation is performed on the memory cell array 20 created using the conventional memory cell 40 (see FIG. 19) and the setting of the potential level applied to the bit line (see FIG. 22) is shown. In the reset operation for the memory cell array 1 (see FIG. 5) using the memory cells 30 (see FIG. 2) of the device of the present invention, the potential level of the bit line can be controlled very easily.
[0059]
That is, when a reset operation is performed using the conventional memory cell 40 and the memory cell array 20, it is necessary to apply a high-level potential to all bit lines connected to unselected memory cells that are not accessed. Occurs, the current consumption due to charging and discharging of a large capacitive load parasitic on these many bit lines increases.In addition, in order to charge the bit lines to a high level potential, a time constant taking into account an additional resistance component is added. Since the charging time is required for one minute, the reset operation time is increased.
[0060]
However, when the reset operation is performed using the memory cells 30 and the memory cell array 1 of the device of the present invention, the unselected bit lines that are not accessed only need to keep the low level, and the increase in current consumption and the increase in access time are reduced. I will not invite you.
[0061]
Next, a method of controlling voltages (voltage application timing) according to the method of the present invention for a word line, a common source line, and a bit line applied when accessing the above-described memory cell will be described.
[0062]
First, a diagram in which a temporal element is added to the voltage relationship applied to each signal line at the time of a write operation to a memory cell and a reset operation of the device of the present invention shown in FIGS. 6, shown in FIG. FIG. 6 shows a write operation corresponding to FIG. 4, and FIG. 7 shows a reset operation corresponding to FIG. As can be seen from the respective comparisons, the control method of the applied voltage according to the present invention applies to the access memory cell A1 to be subjected to the write operation or the reset operation in both the write operation (FIG. 6) and the reset operation (FIG. 7). It is characterized in that a pulse voltage is applied to the connected bit line B1.
[0063]
That is, in this access control method, the same pulse signal shown in FIGS. 8 and 9 described later is input to the bit line B1 connected to the memory cell A1 to be accessed without distinction between the write operation and the reset operation. In addition, a very simple control method can be achieved as compared with the conventional memory cell access method shown in FIGS. 21 and 22 described above.
[0064]
That is, when a write operation and a reset operation are performed on the memory cell array 20 (see FIG. 20) using the cell structure of the conventional memory cell 40 (see FIG. 19), either the write operation or the reset operation is performed. After determining whether or not there is, it is necessary to apply a high-level voltage to the bit line to be accessed in the case of a write operation and to apply a low-level voltage in the case of a reset operation. is there. As described above, since it is necessary to distinguish between the write operation and the reset operation and then apply the voltage level applied to the bit line separately, as long as the conventional memory cell 40 and memory cell array 20 are used, The configuration of the control circuit corresponding to the bit line driver 4 shown in FIG. 1 is inevitably complicated.
[0065]
Next, FIGS. 8 and 9 are timing charts showing a method of controlling voltage application to each signal line connected to a memory cell according to the method of the present invention. FIG. 8 shows the timing at the time of the write operation, and FIG. 9 shows the timing at the time of the reset operation. As shown in FIGS. 8 and 9, in both the write operation and the reset operation, first, the word line 8 is set to a high level in order to turn on the internal select transistor for the memory cell to be operated. Start up to potential. Next, the selection transistor is turned on, that is, a high-level pulse voltage is applied to the bit line 10 connected to the access memory cell during the period P0 when the potential of the word line 8 is high. When the writing or resetting operation is completed by the application of the pulse voltage, the word line 8 is shifted to a low level potential in order to turn off the selection transistor.
[0066]
Here, as can be seen from a comparison between FIG. 8 and FIG. 9, it is the potential level of the common source line 9 connected to the access memory cell that determines whether the operation is the writing operation or the reset operation. 8 and 9, only one pulse voltage application to the bit line 10 is described, but the resistance value of the variable resistance element of the memory cell does not reach a predetermined value by one pulse voltage application. In such a case, application may be performed a plurality of times.
[0067]
Next, it will be described that the writing operation and the resetting operation are separately performed depending on the potential level of the common source line 9.
[0068]
First, as described above, a potential level corresponding to a data signal input from the outside is applied to the common source line 9 via the data driver 3 and the column decoder 5 shown in FIG. As a first case, it is assumed that a low-level data signal is externally supplied when the memory cell is in a reset state (low resistance value) (see FIG. 8). At this time, as shown in FIG. 8, a low-level potential is supplied to the common source line 9, and in this state, the selection transistor is turned on in the period P0, and a high-level pulse is applied to the bit line 10 in the period P1. When the voltage is applied, the application of the pulse voltage forms a current path schematically indicated by an arrow in FIG. 6, and the variable resistance element in the memory cell selected as described above changes to the high resistance state. . That is, in the period P1, a writing operation to the memory cell is performed.
[0069]
Next, as a second case, it is assumed that a low-level data signal is externally supplied when the variable resistance element is already in the written state (high resistance value) (see FIG. 8). At this time, similarly to the first case, the low level potential is supplied to the common source line 9, and in this state, the selection transistor is turned on in the period P0, and the high level is applied to the bit line 10 in the period P1. When a pulse voltage of a level is applied, a current path schematically shown by an arrow in FIG. 6 is formed by the application of the pulse voltage. At this time, a voltage in the writing direction is applied to both ends of the variable resistance element in the selected memory cell. However, since the variable resistance element is already in a high resistance state, the variable resistance element stores by applying this pulse voltage. The logic level of the data does not change.
[0070]
When the common source line 9 has a low-level potential, the bit lines 10 in the period P0 in which the selection transistor is in the ON state and before and after the period P1 in which the high-level pulse voltage is applied have low-level potentials P2 and P3. Since no potential difference occurs between both ends of the selected memory cell, the resistance state of the internal variable resistance element does not change.
[0071]
As a third case, it is assumed that a high-level data signal is externally supplied when the variable resistance element is in a write state (high resistance value) (see FIG. 9). At this time, a high-level potential is supplied to the common source line 9. In this state, the selection transistor is turned on in the period P0, and when a high-level pulse voltage is applied to the bit line 10 in the period P1, In periods P2 and P3 in which the bit line 10 has a low-level potential before and after the period P1 in which the pulse voltage is applied in the period P0, a current path schematically indicated by an arrow in FIG. 7 is formed and selected as described above. The variable resistance element in the memory cell changes from the high resistance state to the low resistance state. That is, the reset operation for the memory cells is performed in the periods P2 and P3.
[0072]
Next, as a fourth case, assume that a high-level data signal is externally supplied when the variable resistance element is in a reset state (low resistance value) (see FIG. 9). At this time, as in the third case, the high level potential is supplied to the common source line 9, and in this state, the selection transistor is turned on in the period P0, and the high level potential is applied to the bit line 10 in the period P1. When the pulse voltage of the level is applied, the bit lines 10 before and after the period P1 in which the pulse voltage is applied in the period P0 are applied to the current paths schematically indicated by arrows in FIG. Is formed. At this time, a voltage in the reset direction is applied to both ends of the variable resistance element in the selected memory cell. However, since the variable resistance element is already in a low resistance state, the variable resistance element stores by this pulse voltage application. The logic level of the data does not change.
[0073]
When the common source line 9 has a high-level potential, a potential difference does not occur at both ends of the selected memory cell during a period in which a high-level pulse voltage is applied to the bit line 10, so that the internal variable resistor The state of the element does not change.
[0074]
In other words, the period P1 during which the high-level pulse voltage is applied to the bit line 10 contributes to the write operation, but does not contribute to the reset operation. Conversely, the periods P2 and P3 before and after the period P1 It does not contribute to the operation, but contributes to the reset operation.
[0075]
In the above description, the write operation is performed when a low-level data signal is input from outside, and the reset operation is performed when a high-level data signal is input. Even if the level and the potential level of the internal common source line 9 are inverted to reverse the correspondence between the external signal level and the write operation and the reset operation, the essence of the control method for the write operation and the reset operation in the method of the present invention is as follows. does not change.
[0076]
Here, when the timing of the reset operation shown in FIG. 9 is examined in more detail, it can be seen that two reset operations (periods P2 and P3) are performed. As a result, the case may be considered where the resistance value of the variable resistance element excessively decreases depending on the characteristics of the element. An access control method for avoiding such an excessive reset state is shown in FIGS. 10 and 11 as a second embodiment of the method of the present invention.
[0077]
FIGS. 10 and 11 show a modification of the input timing to each signal line shown in FIGS. 8 and 9. After the pulse signal input to the bit line 10 rises from a low level to a high level, The word line 8 is controlled to start up.
[0078]
With this timing control, one reset operation can be executed in one period P5 shown in FIG. 11 for one pulse voltage application to the bit line 10. The write operation is also performed once in the period P4 shown in FIG. 10 in this access control method, so that the write operation is the same as that shown in FIG.
[0079]
FIGS. 12 and 13 show a third embodiment of the method of the present invention as another access control method for avoiding an excessive reset state. In the third embodiment, as a modification of the timing waveform of the second embodiment shown in FIGS. 10 and 11, the timing when the polarity of the input pulse to the bit line 10 to be accessed is reversed is shown.
[0080]
Also in this case, as in the case where the input pulse to the bit line 10 to be accessed shown in FIGS. 10 and 11 has a positive polarity (transition from low level to high level and back to low level), the variable resistance element Is set for the write operation period and the reset operation period. In the third embodiment, a write operation is executed in a period P4, and a reset operation is executed in a period P5.
[0081]
The timing control of each signal line connected to a memory cell in the method of the present invention can be performed in various combinations as shown in FIGS. 8 to 13. A suitable timing control method may be appropriately selected depending on the design of the voltage generation circuit built in the invention device.
[0082]
Next, a read operation in the method of the present invention will be described with reference to FIGS.
[0083]
FIG. 14A shows a state in which the bit line B1 connected to the memory cell A to be read is precharged to a low level in advance as the first stage of the read operation. FIG. 14B shows that, as the second stage of the read operation, a high-level potential is applied to the word line W0 connected to the memory cell A, and a high-level voltage of about 1 V is applied to the common source line C0 connected to the memory cell A. The drawing shows a current path (indicated by an arrow) at the time of reading when a voltage is applied, and a main part of a reading circuit that determines the logical level of data stored in the memory cell A from the potential of the bit line B1.
[0084]
In order to form the current path shown in FIG. 14B from the state precharged to a low level shown in FIG. 14A, the current path shown in FIG. It is necessary to charge the parasitic capacitance load included in the current path. When the charge time is in the write state where the resistance value of the variable resistance element of the memory cell A to be read is high, the time constant required for charging the bit line B1 increases, and the rise of the potential of the bit line B1 becomes slow. . Conversely, in the reset state where the resistance value of the variable resistance element of the memory cell A to be read is low, the time constant required for charging the bit line B1 becomes small, so that the potential of the bit line B1 rises due to the variable resistance. This is faster than when the element is in the written state.
[0085]
The potential of the bit line B1 is applied to the reference voltage V of the reference node by the sense amplifier 22. _REF By comparing with, the level of the resistance value of the variable resistance element of the memory cell A can be determined, the logical level of the data stored in the memory cell A can be determined, and the data can be read.
[0086]
In contrast to the read operation of the method of the present invention, in the conventional read circuit (see FIG. 24), a load transistor 21 is provided. Had been determined. However, in the method of the present invention, by not using the load transistor, the time constant related to the charging of the bit line is reduced, and the access time (read time) is improved.
[0087]
Next, FIG. 15 shows a timing waveform of each signal line according to the read operation of the method of the present invention. FIG. 15A shows a timing waveform when the resistance value of the variable resistance element of the memory cell A is high, and FIG. 15B shows a timing waveform in a reset state where the resistance value of the variable resistance element of the memory cell A is low. The timing waveforms in each case are shown.
[0088]
From time T1 to T2 in FIGS. 15A and 15B, the bit line B1 connected to the memory cell A is precharged to a low level. At the next time T2, a read voltage of about 1 V is applied to the common source line C0 connected to the memory cell A. At time T2, by applying a high-level voltage to the word line W0 to be accessed, the current path shown in FIG. 14B becomes conductive, and charging of the bit line B1 is started. And the reference voltage V _REF By comparing the magnitude relationship between the potential and the potential of the bit line B1 by the sense amplifier 22, the logical value of the data stored in the memory cell is determined from the determination of the magnitude relationship.
[0089]
FIG. 15A shows a signal waveform in a write state in which the resistance value of the variable resistance element is high. As described above, the charging time of the bit line B1 in this case becomes longer, and the determination of the sense amplifier 22 is performed. At time T3, the potential of the bit line B1 is changed to the reference voltage V _REF For example, the sense amplifier 22 determines that the logic level of the data is low.
[0090]
FIG. 15B shows a signal waveform in a reset state where the resistance value of the variable resistance element is low, and is the same as FIG. 15A except for the signal waveform of the bit line B1.
In the case of FIG. 15B, as described above, the charging time of the bit line B1 becomes short, and at the determination time T3 of the sense amplifier 22, the potential of the bit line B1 becomes the reference voltage V _REF For example, the sense amplifier 22 determines that the logic level of the data is high.
[0091]
Here, in the embodiment illustrated in FIG. 15, the reference voltage V _REF Is also precharged to a low level from time T1 to T2 in the same manner as the bit line B1, and is designed to be charged to the read voltage of about 1 V at the next time T2. The speed is set such that the speed of the variable resistance element is just intermediate between the write state and the reset state. As a specific design method, for example, a plurality of memory cell arrays are provided, and in each memory cell array, a dummy memory cell in which the resistance value of the variable resistance element is exactly intermediate between the write state and the reset state is provided. One of the other memory cell arrays that does not include the memory cell to be read is selected, and for that memory cell array, the dummy memory cell is selected, and a word line, common source line, and bit line connected to the dummy memory cell are selected. By applying the same control at the same timing as a word line, a common source line, and a bit line connected to a memory cell to be read, so that the reference voltage V illustrated in FIG. _REF Can be obtained. Note that the reference voltage V _REF Is not limited to the above method.
[0092]
<Second embodiment>
Next, a second embodiment of the method of the present invention will be described. In the first embodiment, the target of the write operation, the reset operation, and the read operation in the method of the present invention is the memory cell of the device of the present invention employing the memory cell array configuration shown in FIG. The present invention can be applied to a memory cell array configuration other than the device of the present invention described in the embodiment.
[0093]
FIG. 16 shows another memory cell array configuration to which the method of the present invention can be applied. In the configuration of the memory cell array 50, unlike the memory cell array 1 of the first embodiment (see FIG. 3), the memory cells 30 adjacent to each other in the row direction are not arranged mirror-inverted, and the bit lines are not sandwiched. The memory cells 30 adjacent to each other in the row direction do not share a bit line but have independent bit lines. The memory cells A0 and A1 in the memory cell array 50 are adjacent to each other in the row direction, but the gates of the select transistors in each memory cell are connected to the same word line W0. The memory cells 30 adjacent to each other in the row direction with the common source line interposed therebetween share a common common source line and are connected to the same common source line.
[0094]
This connection is developed in the row direction and the column direction to configure the memory cell array 50, thereby realizing a memory cell array configuration capable of simplifying access control of the method of the present invention, similarly to the configuration shown in FIG. Can be. With respect to the integration density of the memory cell array, the required number of word lines is reduced by half while the required number of bit lines is approximately doubled. The memory cell array configuration of the second embodiment may be more suitable for high integration.
[0095]
FIG. 17 corresponds to FIG. 6 of the first embodiment, and FIG. 18 corresponds to the voltage relationship applied to each signal line at the time of the write operation to the memory cell and the reset operation corresponding to FIG. 7 of the first embodiment. On the other hand, it is a diagram in which time elements are added, and current paths in a write operation and a reset operation in the memory cell array 50 are schematically shown by arrows.
[0096]
Since the current paths during the write operation and the reset operation in FIGS. 17 and 18 are formed by applying voltages to the same signal lines as in FIGS. 6 and 7, even in the memory cell array 50, the current paths shown in FIGS. In addition, the access control method of the method of the present invention according to the first embodiment can be used. That is, a voltage pulse is applied to the bit line during a period P1 (see FIGS. 8 to 13) in which a high-level potential is applied to the word line connected to the selected memory cell, and the voltage pulse is applied according to the voltage level of the common source line. This is the same as the first embodiment in that either the write operation or the reset operation can be performed.
[0097]
Since the memory cell array 50 has an independent bit line for each memory cell, the control of the bit line to which the pulse voltage is applied is different from that of the memory cell array 1 in the first embodiment. 1) may be changed. Also in this case, the function of the column decoder 6 for selecting the bit line connected to the memory cell to be accessed based on the address information input from the outside is the same, so that the special circuit does not become complicated.
[0098]
In the second embodiment, the positional relationship between the common source line and the bit line may be reversed in the memory cell array configuration shown in FIGS. In this case, the two memory cells are adjacent to each other in the row direction by sharing the bit line. Therefore, the two memory cells are simultaneously selected and simultaneously selected according to the voltage level of the common source line independently provided. The writing operation or the resetting operation may be performed.
[0099]
Next, another embodiment of the device of the present invention will be described. In the memory cell array configuration shown in FIG. 3 of the first embodiment, even if the positional relationship between the common source line and the bit line is reversed, the same functions and effects of the device of the present invention and the method of the present invention can be obtained. Alternatively, the control method of the common source line and the bit line may be changed during one or both of the writing operation and the resetting operation or the reading operation while the positional relationship between the common source line and the bit line remains unchanged. . However, when the control method of the signal line is changed, the peripheral circuits connected to the signal lines also need to be changed so that the respective control methods can be changed.
[0100]
【The invention's effect】
As described in detail above, according to the apparatus and method of the present invention, the following effects can be obtained.
[0101]
(1) By using the memory cell array configuration employed in the device of the present invention, it is possible to reduce current consumption and reset operation time during a reset operation.
[0102]
(2) Since the access control of each signal line related to the read operation of the method of the present invention is performed, no load transistor is required, so that the time constant in the read current path can be reduced, and the read speed can be reduced. Can be speeded up.
[0103]
(3) By performing access control of each signal line related to the write operation and the reset operation of the method of the present invention, a voltage pulse can be input to the bit line without distinction between the write operation and the reset operation. The operation and the reset operation can be performed. Therefore, unlike the related art, there is no need for a control circuit for discriminating between the write operation and the reset operation and then inputting the voltage level applied to the bit line separately, and the control circuit can be simplified accordingly.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing a circuit configuration in an embodiment of a nonvolatile semiconductor memory device according to the present invention;
FIG. 2 is an equivalent circuit diagram of a 1T1R type nonvolatile memory cell having a variable resistance element used in the nonvolatile semiconductor memory device according to the present invention.
FIG. 3 is a circuit diagram showing a configuration example of a memory cell array of the nonvolatile semiconductor memory device according to the present invention.
FIG. 4 is an explanatory diagram for explaining a write operation to a memory cell array and a control method thereof in the nonvolatile semiconductor memory device according to the present invention;
FIG. 5 is an explanatory diagram for explaining a reset operation for a memory cell array of the nonvolatile semiconductor memory device according to the present invention and a control method thereof;
FIG. 6 is an explanatory diagram for explaining a write operation to a memory cell array of the nonvolatile semiconductor memory device according to the present invention and a control method thereof by adding a time element;
FIG. 7 is an explanatory diagram for explaining a reset operation for a memory cell array of the nonvolatile semiconductor memory device according to the present invention and a control method thereof by adding a time element;
FIG. 8 is a timing chart for explaining a method of controlling voltage application to each signal line connected to a memory cell in the first embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention;
FIG. 9 is a timing chart for explaining a method of controlling voltage application to each signal line connected to a memory cell in the first embodiment of the reset method of the nonvolatile semiconductor memory device according to the present invention.
FIG. 10 is a timing chart for explaining a method of controlling voltage application to each signal line connected to a memory cell in a second embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention;
FIG. 11 is a timing chart for explaining a method for controlling voltage application to each signal line connected to a memory cell in a second embodiment of the reset method of the nonvolatile semiconductor memory device according to the present invention.
FIG. 12 is a timing chart for explaining a method of controlling voltage application to each signal line connected to a memory cell in a third embodiment of the writing method of the nonvolatile semiconductor memory device according to the present invention;
FIG. 13 is a timing chart for explaining a method of controlling voltage application to each signal line connected to a memory cell in a third embodiment of the reset method of the nonvolatile semiconductor memory device according to the present invention.
FIG. 14 is a circuit diagram illustrating a method for controlling the application of a voltage to each signal line according to the reading method of the nonvolatile semiconductor memory device according to the present invention.
FIG. 15 is a timing chart showing signal waveforms of respective signal lines according to the reading method of the nonvolatile semiconductor memory device according to the present invention.
FIG. 16 is a circuit diagram showing another memory array configuration to which a write method, a reset method, and a read method of the nonvolatile semiconductor memory device according to the present invention can be applied;
FIG. 17 is an explanatory diagram for explaining a write operation and a control method for the memory cell array shown in FIG. 16 by adding a time element;
18 is an explanatory diagram for explaining a reset operation and a control method for the memory cell array shown in FIG. 16 by adding a time element;
FIG. 19 is an equivalent circuit diagram of a 1T1R type nonvolatile memory cell including a variable resistance element used in a conventional nonvolatile semiconductor memory device.
FIG. 20 is a circuit diagram showing a configuration example of a memory cell array of a 1T1R type nonvolatile memory cell including a variable resistance element used in a conventional nonvolatile semiconductor memory device.
FIG. 21 is an explanatory diagram for explaining a write operation to a memory cell array and a control method thereof in the conventional nonvolatile semiconductor memory device shown in FIG. 20;
FIG. 22 is an explanatory diagram for explaining a reset operation for the memory cell array of the conventional nonvolatile semiconductor memory device shown in FIG. 20 and a control method thereof;
FIG. 23 is an explanatory diagram showing a flow of signals including non-selected memory cells at the time of resetting the memory cell array of the conventional nonvolatile semiconductor memory device shown in FIG. 20;
24 is a circuit diagram illustrating a read operation on a memory cell array of the conventional nonvolatile semiconductor memory device shown in FIG.
[Explanation of symbols]
1,20: Memory cell array
2: Row decoder
3: Data driver
4: Bit line driver
5: Column decoder
6,41: Select transistor
7, 42: variable resistance element
8, W0, W1, W2, W3, W4, W5, W6, Wi: row selection line (word line)
9, C0, C1, Cj: 1st column selection line (common source line)
10, B0, B1, B2, B3, B4, Bk: first column selection line (bit line)
21: Load transistor
22: Sense amplifier
30, 40, A, A0, A1, A2, A3, A4: memory cell
43: Word line
44: Common source line
45: Bit line
N1: Connection node
V _REF : Reference voltage

Claims (12)

A plurality of nonvolatile memory cells are arranged in each of the row direction and the column direction, and a plurality of row selection lines are arranged in the row direction to select a predetermined memory cell or a memory cell group from the plurality of nonvolatile memory cells. A nonvolatile semiconductor memory device having a memory cell array in which a plurality of first column selection lines and a plurality of second column selection lines are arranged,
Each of the memory cells includes a variable resistive element for storing information by a change in electric resistance due to an electric stress and a select transistor, and connects one end of the variable resistive element and a drain of the select transistor to each other. The other end of the element and the source of the select transistor form two column connection terminals of the memory cell, and the gate of the select transistor forms a row connection terminal;
In the memory cell array, the memory cell is connected to another memory cell adjacent to one side in the row direction and one of the column connection terminals to a common first column selection line, and the other in the row direction. The other of the memory cells adjacent to the side and the other of the column connection terminals are connected to a common second column selection line,
Two row select lines are provided in each row of the memory cells arranged in the row direction, and in two memory cells adjacent in the row direction, the row connection terminals of one of the memory cells are connected to the two of the two memory cells. A nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device is connected to one side of a row selection line, and the row connection terminal of the other memory cell is connected to the other side of the two row selection lines. Writing or resetting of data to the selected memory cell is performed by writing predetermined data between the two column connection terminals while applying a voltage to the row connection terminal so that the selection transistor is turned on. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said nonvolatile semiconductor memory device is executed by applying a voltage required for resetting. During at least one operation of writing and resetting data, a voltage corresponding to the value of the data related to the writing or resetting operation is applied to the first column selection line connected to the selected memory cell, 3. The nonvolatile semiconductor memory device according to claim 2, wherein a voltage pulse required for the write or reset operation is applied to the second column selection line connected to the selected memory cell. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the same voltage pulse is applied as the voltage pulse during the write operation and during the reset operation. At the time of data reading, one of the first column selection line and the second column selection line connected to the selected memory cell communicates with a sense amplifier for data reading, and the other side performs the reading operation. The nonvolatile semiconductor memory device according to claim 1, wherein a required voltage is applied. The nonvolatile semiconductor memory device according to claim 1, wherein the variable resistance element is formed of an oxide having a perovskite crystal structure containing manganese. 2. A method for performing at least one of a data write operation and a reset operation on one or a plurality of selected memory cells of the nonvolatile semiconductor memory device according to claim 1,
Applying a row selection voltage for turning on the selection transistor to the row selection line connected to the selected one or more memory cells;
Applying a write voltage or a reset voltage according to the value of the data related to the write or reset operation to the first column select line connected to the selected one or more memory cells;
While the row selection voltage is being applied to the second column selection line connected to the selected one or more memory cells, a low voltage level to a high voltage level or a high voltage level to a low voltage level Applying a voltage pulse of a predetermined voltage amplitude that transitions at least once to
In the case where the write voltage is applied to the first column select line, when the voltage level of the voltage pulse is different from the write voltage during the row select voltage application period, the write operation is performed. Done,
In the case where the reset voltage is applied to the first column selection line, when the voltage level of the voltage pulse is at a voltage level different from the reset voltage during the application period of the row selection voltage, the reset operation is performed. A write / reset method for a nonvolatile semiconductor memory device, the method being performed. A plurality of nonvolatile memory cells are arranged in each of the row direction and the column direction, and a plurality of row selection lines are arranged in the row direction to select a predetermined memory cell or a memory cell group from the plurality of nonvolatile memory cells. A non-volatile semiconductor memory device having a memory cell array in which a plurality of first column selection lines and a plurality of second column selection lines are arranged, wherein each of the memory cells is changed by a change in electrical resistance due to electrical stress. A variable resistance element for storing information and a selection transistor; one end of the variable resistance element and the drain of the selection transistor are connected; and the other end of the variable resistance element and the source of the selection transistor are connected to the memory cell. Two column connection terminals are formed, and a gate of the selection transistor forms a row connection terminal, and in the memory cell array, the memory cells are arranged in a row. The other of the memory cells adjacent to one side in the row direction and one of the column connection terminals connected to a common first column select line, and the other of the memory cells adjacent to the other side in the row direction; In a nonvolatile semiconductor memory device in which the other of the column connection terminals is connected to the common second column selection line, at least one operation of writing and resetting data to the selected one or a plurality of memory cells A method of performing
Applying a row selection voltage for turning on the selection transistor to the row selection line connected to the selected one or more memory cells;
Applying a write voltage or a reset voltage according to the value of the data related to the write or reset operation to the first column select line connected to the selected one or more memory cells;
While the row selection voltage is being applied to the second column selection line connected to the selected one or more memory cells, a low voltage level to a high voltage level or a high voltage level to a low voltage level Applying a voltage pulse of a predetermined voltage amplitude that transitions at least once to
In the case where the write voltage is applied to the first column select line, when the voltage level of the voltage pulse is different from the write voltage during the row select voltage application period, the write operation is performed. Done,
In the case where the reset voltage is applied to the first column selection line, when the voltage level of the voltage pulse is at a voltage level different from the reset voltage during the application period of the row selection voltage, the reset operation is performed. A write / reset method for a nonvolatile semiconductor memory device, the method being performed. The voltage pulse is one or more voltage pulses that transition from a low voltage level to a high voltage level and return to a low voltage level, or that transition from a high voltage level to a low voltage level and return to a high voltage level. 9. The method for writing / resetting a nonvolatile semiconductor memory device according to claim 7, wherein: A method for reading data from one or more selected memory cells of the nonvolatile semiconductor memory device according to claim 1,
Applying a row selection voltage for turning on the selection transistor to the row selection line connected to the selected one or more memory cells;
Precharging one side of the first column selection line and the second column selection line connected to the selected one or more memory cells to a predetermined precharge voltage;
Applying a predetermined read voltage to the other side of the first column selection line and the second column selection line connected to the selected one or more memory cells after the precharge;
In a transient state in which the voltage level of the first column selection line changes from the precharge voltage to the read voltage, it is detected that the voltage change varies depending on the resistance state of the variable resistance element of the memory cell. A method for reading a nonvolatile semiconductor memory device, comprising: A plurality of nonvolatile memory cells are arranged in each of the row direction and the column direction, and a plurality of row selection lines are arranged in the row direction to select a predetermined memory cell or a memory cell group from the plurality of nonvolatile memory cells. A non-volatile semiconductor memory device having a memory cell array in which a plurality of first column selection lines and a plurality of second column selection lines are arranged, wherein each of the memory cells is changed by a change in electrical resistance due to electrical stress. A variable resistance element for storing information and a selection transistor; one end of the variable resistance element and the drain of the selection transistor are connected; and the other end of the variable resistance element and the source of the selection transistor are connected to the memory cell. Two column connection terminals are formed, and a gate of the selection transistor forms a row connection terminal, and in the memory cell array, the memory cells are arranged in a row. The other of the memory cells adjacent to one side in the row direction and one of the column connection terminals connected to a common first column select line, and the other of the memory cells adjacent to the other side in the row direction; A method of reading data from one or a plurality of selected memory cells in a nonvolatile semiconductor memory device in which the other one of the column connection terminals is connected to a common second column selection line,
Applying a row selection voltage for turning on the selection transistor to the row selection line connected to the selected one or more memory cells;
Precharging one side of the first column selection line and the second column selection line connected to the selected one or more memory cells to a predetermined precharge voltage;
Applying a predetermined read voltage to the other side of the first column selection line and the second column selection line connected to the selected one or more memory cells after the precharge;
In a transient state in which the voltage level of the first column selection line changes from the precharge voltage to the read voltage, it is detected that the voltage change varies depending on the resistance state of the variable resistance element of the memory cell. A method for reading a nonvolatile semiconductor memory device, comprising: In a transient state in which the voltage level of the first column selection line changes from the precharge voltage to the read voltage, a reference node whose voltage level similarly changes from the precharge voltage to the read voltage is provided. Setting the voltage change of the reference node to be an intermediate voltage change between different voltage changes according to the resistance state of the variable resistance element of the memory cell of the first column selection line;
12. The nonvolatile semiconductor memory according to claim 10, wherein a voltage level of said first column selection line and a voltage level of said reference node are compared during said transient state to read data of said memory cell. How to read the device.

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