JP2004348466A - Clock signal distribution circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To average the accumulation value of the peak value of a feedthrough current generated in each circuit block, and to avoid noise having an inherent phase, in a semiconductor integrated circuit having a plurality of circuit blocks. <P>SOLUTION: In the semiconductor integrated circuit 1, a selection signal generation random number generation circuit 42 generates a selection signal S that changes randomly in a set range each time when an inverted signal U rises, a selector 43 switches input and output ends, where delay clock signals C<SB>1</SB>, C<SB>2</SB>, and C<SB>3</SB>are inputted according to details instructed by the selection signal S, and randomly supplies delay clock signal each having a different delay time for each circuit block. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock signal distribution circuit that distributes a clock signal to a plurality of circuit blocks and a semiconductor integrated circuit including the clock signal distribution circuit.
[0002]
[Prior art]
Generally, a semiconductor integrated circuit such as an ASIC (Application Specific Integrated Circuit) configured with a synchronous circuit and having a plurality of independent functional blocks is connected to the same clock signal supply source in each functional block. The number of all flip-flops (hereinafter referred to as “FF”) (fan-out) is checked, the clock skew is adjusted, and the clock tree is adjusted so that the delay of the clock signal supplied to each FF is equal. With this configuration, the semiconductor integrated circuit is designed to maintain synchronization. Such a circuit configuration is particularly effective when the main purpose is to improve the maximum operating frequency.
[0003]
However, since each functional block driven by the same clock signal operates simultaneously by switching of the supplied clock signal, as the integration of the multifunctional ASIC progresses, the penetration generated in the cell of each functional block occurs. There is a problem that the currents are summed up and a large amount of through current is generated in a very short time. The generation of the through current causes a decrease in the power supply voltage in the ASIC, which causes an increase in power consumption and a malfunction of another circuit provided on the same circuit board as the ASIC. In addition, the harmonic component of the through current may be a noise source, and may cause radiated electromagnetic noise (Electromagnetic Inference) to other circuits or devices. For this reason, the radiated electromagnetic noise must be reduced to a value less than a standard value defined by a domestic standard such as VCCI or an international standard such as IEC.
[0004]
As a method for solving such a problem, in Patent Document 1, a basic clock signal and a delayed clock signal generated from the basic clock signal are supplied to each functional block (referred to as “mega cell” in Patent Document 1). In addition, a method is disclosed in which simultaneous switching noise is suppressed by performing switching as needed. Further, in Patent Document 2, the effect of simultaneous switching noise is reduced by inserting a delay element in a clock tree within a range that guarantees hold in a register to which each delayed clock signal is input between clock buffers. A method for doing so is disclosed.
[0005]
FIG. 3 shows an example of such a conventional semiconductor integrated circuit. The semiconductor integrated circuit of FIG. 3 shows a case where there are three functional blocks (circuit blocks A, B, and C), and three delay elements for delaying a clock signal C supplied from a clock signal supply source are connected in series. A delay clock signal generation unit is provided to connect the delay clock signal C _X output from the third-stage delay element to the circuit block A and the delay block signal C _Y output from the second-stage delay element to the circuit block A the block B, and is configured to provide a delayed clock signal C _Z output from the delay elements of the first stage to the circuit block C.
[0006]
Since the delay values of the respective delayed clock signals C _X , C _Y , and C _Z are different from each other, the timings at which the operations of the circuit blocks A, B, and C start are also shifted. As a result, as shown in FIG. 4, the timing at which a through current is generated in each of the circuit blocks A, B, and C differs according to the timing of each of the delayed clock signals C _X , C _Y , and C _Z , The peak value of the generation amount can be greatly reduced.
[0007]
However, in the semiconductor integrated circuit shown in FIG. 3, the delay clock signal C _X is supplied to the circuit block A, the delay clock signal C _Y to the circuit block B, and the delay clock signal C _Z to the circuit block C. Since the delayed clock signal supplied to each circuit block is fixed, as shown in FIG. 4, every time a clock signal is supplied from the clock signal supply source to the semiconductor integrated circuit, a through current always occurs in the same phase. Will be. As described above, in the semiconductor integrated circuit shown in FIG. 3, since the through current generated in each circuit block depends on the cycle of the delayed clock signal input to each circuit block, the simultaneous switching generated in each functional block is performed. The noise has a unique phase for each delayed clock signal input to each functional block. Accordingly, peaks of the same energy are accumulated, and simultaneous switching noise itself can be reduced, but there is a problem that generation of noise having a unique phase is not suppressed.
[0008]
As a method of solving this problem, there is a method of changing a phase in which a through current occurs by rotating a delay clock signal supplied to each circuit block using a counter. In order to realize this method, for example, as shown in FIG. 5, in the semiconductor integrated circuit shown in FIG. 3, a selection signal generation for generating a selection signal for selecting a delayed clock signal to be output to each circuit block is performed. What is necessary is just to provide the counter and the selector which distributes and supplies the delay clock signal to each circuit block according to the selection signal.
[0009]
In FIG. 5, there are three types of selection signals S generated by the selection signal generation counter, 0, 1, and 2, and delayed clock signals output from the selector to the circuit blocks A, B, and C are D ₁ , D ₂ , respectively. , and _{D 3.} When S = 0, D ₁ = C _Z , D ₂ = C _Y , D ₃ = C _X , and when S = 1, D ₁ = C _Y , D ₂ = C _X , D ₃ = C _Z When S = 2, D ₁ = C _X , D ₂ = C _Z , and D ₃ = C _Y.
[0010]
FIG. 6 shows a through current generated at the rising edge of the delay clock signal when the selection signal S is rotated as 0 → 1 → 2 → 0 in the selection signal generation counter. When the delay clock signal supplied to each circuit block is rotated, as shown in FIG. 6, the delay clock signal supplied to each circuit block is not fixed, and a specific noise corresponding to the cycle of the delay clock signal is generated. Can be suppressed.
[0011]
[Patent Document 1]
JP 10-91274 A [Patent Document 2]
JP-A-11-111854
[Problems to be solved by the invention]
However, in the semiconductor integrated circuit as shown in FIG. 5, although it is possible to suppress the generation of inherent noise corresponding to the cycle of the delayed clock signal, since the delayed clock signal is rotated using a counter, As shown in the figure, since the rotation period of the counter is fixed, the through current always occurs in the same phase during the rotation period of the counter, and the inherent phase noise is not completely suppressed. was there.
[0013]
It is an object of the present invention to suppress the noise having a unique phase by averaging the cumulative value of the peak values of the through current generated in each circuit block in a semiconductor integrated circuit including a plurality of circuit blocks.
[0014]
[Means for Solving the Problems]
In order to solve the above problem, the invention according to claim 1 is a clock signal distribution circuit that distributes a clock signal supplied from a clock signal supply source to a plurality of circuit blocks operating in synchronization with a clock signal. A delay clock signal generator that delays a clock signal supplied from a clock signal supply source to generate a plurality of delay clock signals having different delay values; and a plurality of delay clock signals generated by the delay clock signal generator. And a distribution unit for randomly switching and distributing to each of the plurality of circuit blocks.
[0015]
According to a second aspect of the present invention, in the clock signal distribution circuit according to the first aspect, each of the plurality of circuit blocks is synchronized with an inverted signal of a delayed clock signal having a maximum delay value. The method is characterized in that a plurality of delay clock signals to be distributed to the random number are switched at random.
[0016]
The invention according to claim 3 includes a plurality of circuit blocks that operate in synchronization with a clock signal, and a clock signal distribution circuit that distributes a clock signal supplied from a clock signal supply source to the plurality of circuit blocks. In the semiconductor integrated circuit, the clock signal distribution circuit delays a clock signal supplied from the clock signal supply source and generates a plurality of delayed clock signals having different delay values from each other; A distribution unit that randomly switches the plurality of delayed clock signals generated by the signal generation unit and distributes the delayed clock signals to each of the plurality of circuit blocks.
[0017]
According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, the distribution unit synchronizes with each of the plurality of circuit blocks in synchronization with an inverted signal of a delayed clock signal having a maximum delay value. It is characterized in that a plurality of delay clock signals to be distributed are switched at random.
[0018]
According to the present invention, by randomly distributing delayed clock signals having different delay times for each circuit block provided in a semiconductor integrated circuit, each circuit block is compared with a case where the same clock signal is supplied to all circuit blocks. The cumulative value of the peak values of the through current generated in the block is averaged, and the phase of the noise is dispersed, so that the noise can be reduced from a macro viewpoint. Therefore, the reliability of the semiconductor integrated circuit can be improved.
[0019]
In addition, the distribution unit randomly switches the delay clock signal to be supplied to each circuit block in synchronization with the inverted signal of the delay clock signal having the maximum delay value. The timing at which each circuit block starts operating in response to the delayed clock signal can be shifted, and malfunction of each circuit block can be prevented.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the configuration will be described.
[0021]
FIG. 1 shows an ASIC 1 as a semiconductor integrated circuit according to the present embodiment. ASIC1 is an integrated circuit designed for use in a particular application of a particular user, a plurality of circuit blocks A, B, and C, and the clock signal C ₀ supplied from the clock signal supply source (not shown) The clock signal distribution circuit 2 distributes and supplies the clock signals to the circuit blocks A, B and C.
[0022]
Each of the circuit blocks A, B, and C includes AND, OR, NOT, a theoretical cell of a flip-flop that operates in synchronization with a clock signal, and the like. The circuit blocks A, B, and C operate in synchronization with the rising edge of the input delayed clock signal. In the present embodiment, as schematically shown in FIG. 1, it is assumed that there is a difference in the degree of integration (scale) of each of the circuit blocks A, B, and C. Description will be made on the assumption that the circuit block A> the circuit block B.
[0023]
The clock signal distribution circuit 2 includes a delay clock signal generator 3 that delays the clock signal C ₀ to generate a plurality of delay clock signals C ₁ , C ₂ , and C ₃ having different delay values, and a delay clock signal generator 3. The generated delay clock signals C ₁ , C ₂ , and C ₃ are composed of distribution units 4 that distribute the internal clock signals (D ₁ , D ₂ , and D ₃ ) to the circuit blocks A, B, and C, respectively.
[0024]
The delay clock signal generator 3 is configured by three delay elements 31, 32, and 33 connected in series. Clock signal _{C 0} is supplied to the delay element 31 of the first stage of the three delay elements 31, 32 and 33.
[0025]
The delay element 31 delays the clock signal C ₀ to generate a _first delayed clock signal C _1, and outputs the first delayed clock signal C ₁ to the second-stage delay element 32 and the distribution unit 4. The second-stage delay element 32 further delays the first delayed clock signal C ₁ to generate a _second delayed clock signal C _2, and outputs the second delayed clock signal C ₂ to the third-stage delay element 33 and the distribution unit 4. The third-stage delay element 33 further delays the second delayed clock signal C ₂ to generate a _third delayed clock signal C _3, and outputs the third delayed clock signal C ₃ to the distribution unit 4.
[0026]
The delay values of the delayed clock signals C ₁ , C ₂ , and C _{3 from} the clock signal C ₀ are C ₁ <C ₂ <C ₃ , and all are provided in the circuit blocks A, B, and C. It is set within a range that satisfies the setup time and the hold time of the flip-flop.
[0027]
The distribution unit 4 includes an inverter 41 that generates an inverted signal U of the _third delayed clock signal C3, a selection signal generation random number generation circuit 42 that generates a selection signal S in response to the input of the inverted signal U, and a selection signal S , The selector 43 is configured to randomly switch the delay clock signals C ₁ , C ₂ , and C ₃ distributed to the circuit blocks A, B, and C according to the above and to distribute and supply the delayed clock signals to the circuit blocks.
[0028]
The inverter 41 is connected between the output terminal of the third-stage delay element 33 and the input terminal of the selection signal generation random number generation circuit 42. Inverter 41 inverts the third delayed clock signal C ₃ supplied from the delay element 33, and outputs the generated inverted signal U to the selection signal generating random number generating circuit 42.
[0029]
The selection signal generation random number generation circuit 42 generates a random number (pseudo random number) within a set range in synchronization with the rising edge of the input inverted signal U, and outputs a selection signal S corresponding to the random number to the selector 43. . The selection signal S indicates one of 0, 1, and 2 and instructs the selector 43 to which circuit block the delay clock signals C ₁ , C ₂ , and C ₃ are to be distributed.
[0030]
The selector 43 has an input terminal to which the delay clock signals C ₁ , C ₂ , C ₃ and the selection signal S are input, and an output terminal connected to each input terminal of the circuit blocks A, B, C. . The selector 43 switches the connection between the input terminal to which the delayed clock signals C ₁ , C ₂ , and C ₃ are input and the output terminal in accordance with the content indicated by the selection signal S.
[0031]
In this embodiment, the output signal supplied to the circuit block A and selected delayed clock signal D ₁ from the selector 43, the output signal supplied to the circuit block B as selected delayed clock signal D ₂ from the selector 43, the selector 43 and selecting the delayed clock signal D ₃ an output signal supplied to the circuit block C from.
[0032]
Further, in the present embodiment, when the selection signal S = 0, D ₁ = C ₁ , D ₂ = C ₂ , D ₃ = C _3, and when the selection signal S = 1, D ₁ = C ₂ , D ₂ = C ₃ , D ₃ = C _1, and when the selection signal S = 2, D ₁ = C ₃ , D ₂ = C ₁ , and D ₃ = C ₂ .
[0033]
Next, the operation of the ASIC 1 will be described.
When the clock signal C ₀ is supplied from the clock signal supply source to the clock signal distribution circuit 2, the delay elements 31, 32, and 33 of the delayed clock signal generation unit 3 have different delay values from each other as shown in FIG. One delayed clock signal C ₁ , second delayed clock signal C ₂ , and third delayed clock signal C ₃ are generated. These delayed clock signals C ₁ , C ₂ , and C ₃ are input to the selector 43.
[0034]
The third delayed clock signal _{C 3} is input to the inverter 41 with the selector 43. Inverter 41 inverts _third delayed clock signal C3 to generate inverted signal U as shown in FIG. The generated inverted signal U is output to the selection signal generation random number generation circuit 42.
[0035]
In the selection signal generation random number generation circuit 42, a random number within the set range is generated in synchronization with the rising edge of the inverted signal U, and the selection signal S corresponding to the random number is output to the selector 43.
[0036]
When the selection signal S = 0, the selector 43, the circuit block A, the first delayed clock signal C ₁ is supplied to the circuit block B, the second delayed clock signal C ₂ is supplied, the circuit block C is supplied with a _third delayed clock signal C3. The circuit block A operates in synchronization with the rising edge of the _first delayed clock signal C1, the circuit block B operates in synchronization with the rising edge of the second delayed clock signal C2, and the circuit block C operates in synchronization with the rising edge of the _second delayed clock signal C2. operates in synchronization with the third rising edge of the delayed clock signal C ₃ of. With the operation of each of the circuit blocks A, B, and C, a through current is generated in the order of the circuit blocks A, B, and C.
[0037]
When the selection signal S = 1, the selector 43, the circuit block A, the second delayed clock signal C ₂ is supplied to the circuit block B, the third delayed clock signal C ₃ is supplied, the circuit block C is supplied with a _first delayed clock signal C1. The circuit block A operates in synchronization with the rising edge of the _second delayed clock signal C2, the circuit block B operates in synchronization with the rising edge of the third delayed clock signal C3, and the circuit block C operates in synchronization with the rising edge of the _third delayed clock signal C3. operates in synchronization with the first rising edge of the delayed clock signal C _1. With the operation of each of the circuit blocks A, B, and C, a through current is generated in the order of the circuit blocks C, A, and B.
[0038]
When the selection signal S = 2, the selector 43, the circuit block A, the third delayed clock signal C ₃ is supplied to the circuit block B, the first delayed clock signal C ₁ is supplied, the circuit block C is supplied with a _second delayed clock signal C2. The circuit block A operates in synchronization with the rising edge of the _third delayed clock signal C3, the circuit block B operates in synchronization with the rising edge of the first delayed clock signal C1, and the circuit block C operates in synchronization with the rising edge of the _first delayed clock signal C1. operates in synchronization with the second rising edge of the delayed clock signal C _2. With the operation of each of the circuit blocks A, B, and C, a through current is generated in the order of the circuit blocks B, C, and A.
[0039]
FIG. 2 shows a case where the selection signal S is generated in the order of 0, 2, 0, 1, 2, 2, 1, 0, 1,... According to a random number generated in synchronization with the rising edge of the inverted signal U. 2 shows a through current generated in each circuit block.
[0040]
According to the ASIC 1 described above, since the delay clock signal input to each circuit block changes randomly by using the selection signal generation random number generation circuit 42, it is generated for each circuit block as shown in FIG. The cumulative value of the peak values of the through current is averaged and the phase of the noise is dispersed, so that the noise can be reduced from a macro viewpoint. Therefore, the reliability of the ASIC 1 can be improved.
[0041]
Further, by generating the selection signal S delay value selection signal generating random number generating circuit 42 in synchronism with the inverted signal U of the third delayed clock signal C ₃ having the maximum respective delayed clock signals C _1, C ₂ , by switching the internal connection of the selector 43 when the signal level of C ₃ is Low, the circuit blocks a, B, and switching the delayed clock signal supplied to the C. Therefore, it is possible to prevent the selector 43 from malfunctioning when switching the connection, and to convert the respective delayed clock signals C ₁ , C ₂ , C ₃ input to the input terminals into a circuit block corresponding to the content of the selection signal S. Can be reliably distributed.
[0042]
In addition, the timing of switching the connection inside the selector 43 and the timing of starting the operation of each of the circuit blocks A, B, and C by the delayed clock signal can be shifted, so that generation of noise due to simultaneous switching can be prevented. In addition, malfunction of each of the circuit blocks A, B, and C can be prevented.
[0043]
The delay value of each of the delayed clock signals C ₁ , C ₂ , and C ₃ is within a range that satisfies the setup time and the hold time of the flip-flop provided in each of the circuit blocks A, B, and C. , B, and C, the synchronization of the entire ASIC 1 can be maintained.
[0044]
The description in the present embodiment can be appropriately changed without departing from the spirit of the present invention.
[0045]
For example, the number of circuit blocks included in the ASIC 1 and the number of delay elements included in the delayed clock signal generation unit 3 are not limited. The configuration of the delayed clock signal generator 3, as long as the clock signal C ₀ supplied from the clock signal supply source can generate a plurality of delayed clock signals having different delay values, are limited to the above structure Not something.
[0046]
【The invention's effect】
According to the present invention, by randomly distributing delayed clock signals having different delay times for each circuit block included in the semiconductor integrated circuit, each circuit block is compared with a case where the same clock signal is supplied to all circuit blocks. The cumulative value of the peak values of the through current generated in the block is averaged, and the phase of the noise is dispersed, so that the noise can be reduced from a macro viewpoint. Therefore, the reliability of the semiconductor integrated circuit can be improved.
[0047]
In addition, the distribution unit randomly switches the delay clock signal supplied to each circuit block in synchronization with the inverted signal of the delay clock signal having the maximum delay value. The timing at which each circuit block starts operating in response to the delayed clock signal can be shifted, and malfunction of each circuit block can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a circuit configuration of a clock signal distribution circuit 2 and an ASIC (semiconductor integrated circuit) 1 according to the present invention.
FIG. 2 is a diagram showing waveforms of various signals generated by a clock signal distribution circuit 2 in FIG. 1 and a through current generated in each circuit block.
FIG. 3 is a block diagram showing an example of a circuit configuration of a conventional semiconductor integrated circuit.
4 is a diagram showing a waveform of a delayed clock signal output from each delay element of the semiconductor integrated circuit of FIG. 3 and a through current generated in each circuit block.
FIG. 5 is a block diagram showing another example of the circuit configuration of a conventional semiconductor integrated circuit.
FIG. 6 is a view showing waveforms of various signals generated in each section of the semiconductor integrated circuit of FIG. 5;
[Explanation of symbols]
1 ASIC (semiconductor integrated circuit)
2 clock signal distribution circuit 3 delay clock signal generation unit 31 delay element 32 delay element 33 delay element 4 distribution unit 41 inverter 42 selection signal generation random number generation circuit 43 selector C ₀ clock signal C ₁ delay clock signal C ₂ delay clock signal C ₃ Delay clock signal D ₁ Select delay clock signal D ₂ Select delay clock signal D ₃ Select delay clock signal S Select signal

Claims (4)

A clock signal distribution circuit that distributes a clock signal supplied from a clock signal supply source to a plurality of circuit blocks operating in synchronization with the clock signal,
A delayed clock signal generation unit that delays a clock signal supplied from the clock signal supply source and generates a plurality of delayed clock signals having different delay values from each other;
A distribution unit that randomly switches a plurality of delay clock signals generated by the delay clock signal generation unit and distributes the plurality of delay clock signals to each of the plurality of circuit blocks;
A clock signal distribution circuit comprising: 2. The method according to claim 1, wherein the distributing unit randomly switches a plurality of delayed clock signals distributed to each of the plurality of circuit blocks in synchronization with an inverted signal of the delayed clock signal having a maximum delay value. A clock signal distribution circuit according to any one of the preceding claims. A semiconductor integrated circuit comprising: a plurality of circuit blocks operating in synchronization with a clock signal; and a clock signal distribution circuit that distributes a clock signal supplied from a clock signal supply source to the plurality of circuit blocks.
The clock signal distribution circuit,
A delayed clock signal generation unit that delays a clock signal supplied from the clock signal supply source and generates a plurality of delayed clock signals having different delay values from each other;
A distribution unit that randomly switches a plurality of delay clock signals generated by the delay clock signal generation unit and distributes the plurality of delay clock signals to each of the plurality of circuit blocks;
A semiconductor integrated circuit comprising: 4. The distribution unit according to claim 3, wherein the distribution unit randomly switches a plurality of delay clock signals distributed to each of the plurality of circuit blocks in synchronization with an inverted signal of the delay clock signal having a maximum delay value. A semiconductor integrated circuit as described in the above.

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