JP2004343521A

JP2004343521A - Differential amplifier

Info

Publication number: JP2004343521A
Application number: JP2003138874A
Authority: JP
Inventors: Makoto Hanshimoseki; 誠半下石
Original assignee: Ricoh Co Ltd
Current assignee: Ricoh Co Ltd
Priority date: 2003-05-16
Filing date: 2003-05-16
Publication date: 2004-12-02
Anticipated expiration: 2023-05-16
Also published as: JP4532847B2

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a complementary differential amplifier capable of receiving an input of a wide voltage range and obtaining an output of a wide voltage range. <P>SOLUTION: Each noninverted input port and each inverted input port of a differential output type first differential amplifier circuit 2 and a second differential amplifier circuit 3 are connected corresponding to a noninverted input port IN+ and an inverted input port IN-, a pair of output ports of the first differential amplifier circuit 2 is connected corresponding to conflicting input ports of a signal end type third differential amplifier circuit 4, a pair of the second differential amplifier circuit 3 is connected corresponding to conflicting input ports of a single end type fourth differential amplifier circuit 5, and each output port of the third differential amplifier circuit 4 and a fifth differential amplifier circuit 5 is connected to an output circuit 6 constituting a push-pull circuit configuration. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、入力電圧範囲が広く、広範囲な出力電圧範囲が得られるコンプリメンタリ型の差動増幅器に関する。
【０００２】
【従来の技術】
従来、逆導電型の差動対を有する２つの差動増幅回路と基本的で簡単な出力回路の構成にて出力駆動能力の高いプッシュプル出力とした差動増幅器があった（例えば、特許文献１参照。）。しかし、このような構成では、例えば無負荷時の状態で入力信号が電源電圧付近までなるような場合、出力トランジスタの一方がオンしにくくなることで電流が流れなくなり、出力が不安定になっていた。差動増幅器又は電圧比較器における入力電圧と比較して電源電圧範囲は広いために動作上問題はなかったが、近年は電源電圧の低電圧化に伴い、電源電圧付近までの入力電圧範囲が要求されている。
【０００３】
図４は、入出力範囲が広範囲な差動増幅器の従来例を示した図である。
図４では、極性が異なる２つの差動対を用いることで入力電圧範囲を広くとれ、２つの差動増幅回路１０１及び１０２の出力信号をいずれもフォールデッドカスコード回路１０３により折り返す。更に、フォールデッドカスコード回路１０３からの各出力信号は、プッシュプル回路構成をなして出力電圧範囲を大きくした出力回路１０４で合成して出力される。
【０００４】
【特許文献１】
特開昭６１−１４８９０６号公報
【０００５】
【発明が解決しようとする課題】
このような差動増幅器を使用すれば、所望の入出力電圧範囲の広い特性が得られるが、回路を設計する上で次のような問題がある。フォールデッドカスコード回路において、複数のバイアス電圧Ｖａ〜Ｖｄが必要であるため、バイアス電圧発生回路が必要になり、フォールデッドカスコード回路の最適なトランジスタサイズを決めるのが困難である。
【０００６】
また、差動増幅回路１０１，１０２及びフォールデッドカスコード回路１０３の電流を決めるのが複雑で難しく、特に、トランジスタサイズが不適当であれば、フォールデッドカスコード回路１０３内のトランジスタ動作状態が３極間領域及び５極間領域が入り混じった状態になる場合があった。一方、出力回路１０４においては、広範囲なプッシュプル出力構成を得るようにすれば、図４のＰＭＯＳトランジスタ及びＮＭＯＳトランジスタの両方を駆動する必要があり、フォールデッドカスコード回路からの出力信号を合成して該ＰＭＯＳトランジスタ及びＮＭＯＳトランジスタの両方を制御するための出力制御回路が必要になる。これらのことから、回路規模が大きくなり、レイアウト面積が大きくなるという問題があった。
【０００７】
本発明は、上記のような問題を解決するためになされたものであり、広電圧範囲の入力が可能で、広電圧範囲の出力が得られるコンプリメンタリ型の差動増幅器を得ることを目的とする。
【０００８】
【課題を解決するための手段】
この発明に係る差動増幅器は、１対の第１入力端及び第２入力端に対応して入力された第１入力信号及び第２入力信号を差動増幅して所定の出力端から出力する差動増幅器において、
非反転入力端に前記第１入力信号が入力されると共に反転入力端に前記第２入力信号が入力される差動出力型の第１差動増幅回路と、
非反転入力端に前記第１入力信号が入力されると共に反転入力端に前記第２入力信号が入力される差動出力型の第２差動増幅回路と、
前記第１差動増幅回路からの１対の出力信号が対応する入力端に入力されるシングルエンド型の第３差動増幅回路と、
前記第２差動増幅回路からの１対の出力信号が対応する入力端に入力されるシングルエンド型の第４差動増幅回路と、
前記第３差動増幅回路及び該第４差動増幅回路の各出力信号を合成して前記所定の出力端に出力する出力回路と、
を備え、
前記第１差動増幅回路及び第２差動増幅回路の各差動対は逆導電型をなすと共に、前記第３差動増幅回路及び第４差動増幅回路の各差動対は逆導電型をなすものである。
【０００９】
また、前記第１差動増幅回路及び第３差動増幅回路の各差動対は同導電型をなすと共に、前記第２差動増幅回路及び第４差動増幅回路の各差動対は同導電型をなすようにした。
【００１０】
具体的には、前記第１差動増幅回路は、反転出力端が第３差動増幅回路の反転入力端に接続されると共に非反転出力端が第３差動増幅回路の非反転入力端に接続され、前記第２差動増幅回路は、反転出力端が第４差動増幅回路の反転入力端に接続されると共に非反転出力端が第４差動増幅回路の非反転入力端に接続されるようにした。
【００１１】
また、前記第１差動増幅回路及び第２差動増幅回路は、差動対に接続された負荷回路が該差動対をなす各トランジスタにそれぞれ順方向に対応して接続されたダイオードで形成されるようにしてもよい。
【００１２】
また、前記第３差動増幅回路及び第４差動増幅回路は、差動対に接続された負荷回路がカレントミラー回路を形成してなるようにしてもよい。
【００１３】
【発明の実施の形態】
次に、図面に示す実施の形態に基づいて、本発明を詳細に説明する。
第１の実施の形態．
図１は、本発明の第１の実施の形態における差動増幅器の構成例を示した図である。
図１において、差動増幅器１は、非反転入力端ＩＮ＋及び反転入力端ＩＮ−に入力された１対の入力信号Ｓ１及びＳ２に対して差動増幅を行い出力端ＯＵＴから出力するものであり、差動出力型の第１差動増幅回路２及び第２差動増幅回路３、シングルエンド型の第３差動増幅回路４及び第４差動増幅回路５、並びにプッシュプル回路構成をなした出力回路６で構成されている。
【００１４】
差動増幅器１の非反転入力端ＩＮ＋には、第１差動増幅回路２及び第２差動増幅回路３の各非反転入力端がそれぞれ接続され、差動増幅器１の反転入力端ＩＮ−には、第１差動増幅回路２及び第２差動増幅回路３の各反転入力端がそれぞれ接続されている。第１差動増幅回路２において、反転出力端ｏ−は第３差動増幅回路４の反転入力端に接続され、非反転出力端ｏ＋は第３差動増幅回路４の非反転入力端に接続されている。同様に、第２差動増幅回路３において、反転出力端ｏ−は第４差動増幅回路５の反転入力端に接続され、非反転出力端ｏ＋は第４差動増幅回路５の非反転入力端に接続されている。第３差動増幅回路４及び第４差動増幅回路５の各出力端は出力回路６に接続され、出力回路６の出力端が差動増幅器１の出力端ＯＵＴに接続されている。
【００１５】
入力された１対の入力信号Ｓ１，Ｓ２は、第１差動増幅回路２及び第２差動増幅回路３の対応する入力端に入力され、入力信号Ｓ１，Ｓ２の電圧差は第１差動増幅回路２及び第２差動増幅回路３でそれぞれ増幅され、第１差動増幅回路２及び第２差動増幅回路３の各差動出力信号の電圧差は、対応する第３差動増幅回路４及び第４差動増幅回路５でそれぞれ増幅されて出力回路６にそれぞれ出力される。出力回路６は、第３差動増幅回路４及び第４差動増幅回路５の各出力信号を合成して、出力端ＯＵＴに出力し、広い電圧範囲の入力が可能であり、高い利得を得ることができる。
【００１６】
図２は、図１の各差動増幅回路の内部構成例を示したブロック図である。
図２において、差動増幅器１は、第１電源電圧Ｖ１と第２電源電圧Ｖ２を電源として作動している。第１差動増幅回路２は、第１の差動対２１、該第１の差動対２１に接続された第１の負荷回路２２、及び第１の差動対２１に電流を供給する第１の定電流源２３で構成されている。第１電源電圧Ｖ１と第１の差動対２１との間に第１の定電流源２３が接続され、第２電源電圧Ｖ２と第１の差動対２１との間に第１の負荷回路２２が接続されている。第１の差動対２１の各信号入力端は、入力信号Ｓ１及びＳ２が対応して入力されており、第１の差動対２１と第１の負荷回路２２との各接続部が第１差動増幅回路２の各出力端ｏ＋及びｏ−をそれぞれなしている。
【００１７】
第２差動増幅回路３は、第２の差動対３１、該第２の差動対３１に接続された第２の負荷回路３２、及び第２の差動対３１に電流を供給する第２の定電流源３３で構成されている。第２電源電圧Ｖ２と第２の差動対３１との間に第２の定電流源３３が接続され、第１電源電圧Ｖ１と第２の差動対３１との間に第２の負荷回路３２が接続されている。第２の差動対３１の各信号入力端は、入力信号Ｓ１及びＳ２が対応して入力されており、第２の差動対３１と第２の負荷回路３２との各接続部が第２差動増幅回路３の各出力端ｏ＋及びｏ−をそれぞれなしている。
【００１８】
第３差動増幅回路４は、第３の差動対４１、該第３の差動対４１に接続された第３の負荷回路４２、及び第３の差動対４１に電流を供給する第３の定電流源４３で構成されている。第１電源電圧Ｖ１と第３の差動対４１との間に第３の定電流源４３が接続され、第２電源電圧Ｖ２と第３の差動対４１との間に第３の負荷回路４２が接続されている。第３の差動対４１の各信号入力端は、第１差動増幅回路２からの１対の差動出力信号が対応して入力されており、第３の差動対４１と第３の負荷回路４２との一方の接続部が第３差動増幅回路４の出力端をなし、出力回路６に接続されている。
【００１９】
第４差動増幅回路５は、第４の差動対５１、該第４の差動対５１に接続された第４の負荷回路５２、及び第４の差動対５１に電流を供給する第４の定電流源５３で構成されている。第２電源電圧Ｖ２と第４の差動対５１との間に第４の定電流源５３が接続され、第１電源電圧Ｖ１と第４の差動対５１との間に第４の負荷回路５２が接続されている。第４の差動対５１の各信号入力端は、第２差動増幅回路３からの１対の差動出力信号が対応して入力されており、第４の差動対５１と第４の負荷回路５２との一方の接続部が第４差動増幅回路５の出力端をなし、出力回路６に接続されている。
【００２０】
ここで、第１差動増幅回路２及び第３差動増幅回路４は、第１及び第３の各差動対が同導電型であるため、入力信号Ｓ１及びＳ２が第１差動増幅回路２の入力電圧の許容範囲を超えた場合でも、第１差動増幅回路２の差動出力信号は、第３差動増幅回路４の入力電圧の許容範囲となる。同様に、第２差動増幅回路２及び第４差動増幅回路５は、第２及び第４の各差動対が同導電型であるため、入力信号Ｓ１及びＳ２が第２差動増幅回路３の入力電圧の許容範囲を超えた場合でも、第２差動増幅回路３の差動出力信号は、第４差動増幅回路５の入力電圧の許容範囲となる。これらのことから、出力回路６に入力される第３差動増幅回路４及び第４差動増幅回路５の各出力信号は、入力信号Ｓ１及びＳ２が正しく伝わったものとなり、出力回路６で合成されて出力端ＯＵＴに出力される。
【００２１】
図３は、図２で示した差動増幅器１の回路例を示した図である。
図３において、第１電源電圧Ｖ１は、正側電源電圧ＶＤＤをなし、第２電源電圧Ｖ２は負側電源電圧ＶＳＳ、例えば接地電圧をなしている。第１差動増幅回路２は、ＰＭＯＳトランジスタＭ１，Ｍ２、ＮＭＯＳトランジスタＭ３，Ｍ４及び第１の定電流源２３で構成されており、ＰＭＯＳトランジスタＭ１及びＭ２は、第１の差動対２１をなし、ＮＭＯＳトランジスタＭ３及びＭ４は第１の負荷回路２２をなしている。
【００２２】
ＰＭＯＳトランジスタＭ１及びＭ２の各ソースは接続され、該接続部と正側電源電圧ＶＤＤとの間に第１の定電流源２３が接続されている。ＰＭＯＳトランジスタＭ１のドレインと負側電源電圧ＶＳＳとの間にはＮＭＯＳトランジスタＭ３が接続され、ＰＭＯＳトランジスタＭ２のドレインと負側電源電圧ＶＳＳとの間にはＮＭＯＳトランジスタＭ４が接続されている。ＰＭＯＳトランジスタＭ１のゲートは差動増幅器１の反転入力端をなし、ＰＭＯＳトランジスタＭ２のゲートは差動増幅器１の非反転入力端をなしている。
【００２３】
ＮＭＯＳトランジスタＭ３のゲートはＮＭＯＳトランジスタＭ３のドレインに接続され、ＮＭＯＳトランジスタＭ４のゲートはＮＭＯＳトランジスタＭ４のドレインに接続され、ＮＭＯＳトランジスタＭ３及びＭ４はそれぞれダイオードをなしている。ＰＭＯＳトランジスタＭ１とＮＭＯＳトランジスタＭ３の接続部が、第１差動増幅回路２の出力端ｏ＋をなし、ＰＭＯＳトランジスタＭ２とＮＭＯＳトランジスタＭ４の接続部が、第１差動増幅回路２の出力端ｏ−をなしている。
【００２４】
第２差動増幅回路３は、ＰＭＯＳトランジスタＭ５，Ｍ６、ＮＭＯＳトランジスタＭ７，Ｍ８及び第２の定電流源３３で構成されており、ＮＭＯＳトランジスタＭ７及びＭ８は、第２の差動対３１をなし、ＰＭＯＳトランジスタＭ５及びＭ６は第２の負荷回路３２をなしている。ＮＭＯＳトランジスタＭ７及びＭ８の各ソースは接続され、該接続部と負側電源電圧ＶＳＳとの間に第２の定電流源３３が接続されている。
【００２５】
正側電源電圧ＶＤＤとＮＭＯＳトランジスタＭ７のドレインとの間にはＰＭＯＳトランジスタＭ５が接続され、電源電圧ＶＤＤとＮＭＯＳトランジスタＭ８のドレインとの間にはＰＭＯＳトランジスタＭ６が接続されている。ＮＭＯＳトランジスタＭ７のゲートは第２差動増幅回路３の反転入力端をなし、ＮＭＯＳトランジスタＭ８のゲートは第２差動増幅回路３の非反転入力端をなしている。ＰＭＯＳトランジスタＭ５のゲートはＰＭＯＳトランジスタＭ５のドレインに接続され、ＰＭＯＳトランジスタＭ６のゲートはＰＭＯＳトランジスタＭ６のドレインに接続され、ＰＭＯＳトランジスタＭ５及びＭ６はそれぞれダイオードをなしている。ＰＭＯＳトランジスタＭ５とＮＭＯＳトランジスタＭ７の接続部が第２差動増幅回路３の出力端ｏ＋をなし、ＰＭＯＳトランジスタＭ６とＮＭＯＳトランジスタＭ８の接続部が、第２差動増幅回路３の出力端ｏ−をなしている。
【００２６】
第３差動増幅回路４は、ＰＭＯＳトランジスタＭ９，Ｍ１０、ＮＭＯＳトランジスタＭ１１，Ｍ１２及び第３の定電流源４３で構成されており、ＰＭＯＳトランジスタＭ９及びＭ１０は、第３の差動対４１をなし、ＮＭＯＳトランジスタＭ１１及びＭ１２はカレントミラー回路を形成して第３の負荷回路４２をなしている。
【００２７】
ＰＭＯＳトランジスタＭ９及びＭ１０の各ソースは接続され、該接続部と正側電源電圧ＶＤＤとの間に第３の定電流源４３が接続されている。ＰＭＯＳトランジスタＭ９のドレインと負側電源電圧ＶＳＳとの間にはＮＭＯＳトランジスタＭ１１が接続され、ＰＭＯＳトランジスタＭ１０のドレインと負側電源電圧ＶＳＳとの間にはＮＭＯＳトランジスタＭ１２が接続されている。ＰＭＯＳトランジスタＭ９のゲートは第３差動増幅回路４の反転入力端をなし、ＰＭＯＳトランジスタＭ１０のゲートは第３差動増幅回路４の非反転入力端をなしている。ＮＭＯＳトランジスタＭ１１及びＭ１２の各ゲートは接続され、該接続部はＮＭＯＳトランジスタＭ１１のドレインに接続されている。ＰＭＯＳトランジスタＭ１０とＮＭＯＳトランジスタＭ１２の接続部が第３差動増幅回路４の出力端をなしている。
【００２８】
第４差動増幅回路５は、ＰＭＯＳトランジスタＭ１３，Ｍ１４、ＮＭＯＳトランジスタＭ１５，Ｍ１６及び第４の定電流源５３で構成されており、ＮＭＯＳトランジスタＭ１５及びＭ１６は、第４の差動対５１をなし、ＰＭＯＳトランジスタＭ１３及びＭ１４はカレントミラー回路を形成して第４の負荷回路５２をなしている。ＮＭＯＳトランジスタＭ１５及びＭ１６の各ソースは接続され、該接続部と負側電源電圧ＶＳＳとの間に第４の定電流源５３が接続されている。
【００２９】
正側電源電圧ＶＤＤとＮＭＯＳトランジスタＭ１５のドレインとの間にはＰＭＯＳトランジスタＭ１３が接続され、正側電源電圧ＶＤＤとＮＭＯＳトランジスタＭ１６のドレインとの間にはＰＭＯＳトランジスタＭ１４が接続されている。ＮＭＯＳトランジスタＭ１５のゲートは第４差動増幅回路５の反転入力端をなし、ＮＭＯＳトランジスタＭ１６のゲートは第４差動増幅回路５の非反転入力端をなしている。ＰＭＯＳトランジスタ１３及びＭ１４の各ゲートは接続され、該接続部はＰＭＯＳトランジスタＭ１３のドレインに接続されている。ＰＭＯＳトランジスタＭ１４とＮＭＯＳトランジスタＭ１６の接続部が、第４差動増幅回路５の出力端をなしている。
【００３０】
出力回路６は、ＰＭＯＳトランジスタＭ１７及びＮＭＯＳトランジスタＭ１８で構成されており、正側電源電圧ＶＤＤと負側電源電圧ＶＳＳとの間にＰＭＯＳトランジスタＭ１７及びＮＭＯＳトランジスタＭ１８が直列に接続されている。ＰＭＯＳトランジスタＭ１７のゲートは第４差動増幅回路５の出力端に接続され、ＮＭＯＳトランジスタＭ１８のゲートは第３差動増幅回路４の出力端に接続されている。ＰＭＯＳトランジスタＭ１７及びＮＭＯＳトランジスタＭ１８の接続部が出力端ＯＵＴに接続され、出力回路６はプッシュプル回路をなしている。
【００３１】
このような構成において、入力信号Ｓ１及びＳ２は、ＰＭＯＳトランジスタＭ１及びＭ２で構成された第１の差動対２１と、ＮＭＯＳトランジスタＭ７及びＭ８で構成された第２の差動対３１へそれぞれ入力される。次に、第１差動増幅回路２の差動出力信号Ｎ１及びＮ２は、ＰＭＯＳトランジスタＭ９及びＭ１０で構成された第３の差動対４１へそれぞれ入力され、第２差動増幅回路３の差動出力信号Ｎ３及びＮ４は、ＮＭＯＳトランジスタＭ１５及びＭ１６で構成された第４の差動対５１へそれぞれ入力される。
【００３２】
入力信号Ｓ１及びＳ２は、第１差動増幅回路２及び第２差動増幅回路３でそれぞれ差動増幅され、第１差動増幅回路２から差動出力信号Ｎ１及びＮ２が、第２差動増幅回路３から差動出力信号Ｎ３及びＮ４がそれぞれ出力され、次段の対応する第３差動増幅回路４及び第４差動増幅回路５へ対応して入力される。通常、図３で示したように各差動増幅回路２〜４をＣＭＯＳトランジスタで構成した場合の入力電圧範囲は、定電流源が持つ電位差と、差動対をなすトランジスタが持つゲートソース間電圧Ｖｇｓ、負荷回路が持つ電位差によって制約を受ける。
【００３３】
したがって、ＰＭＯＳトランジスタＭ１及びＭ２で構成される第１差動増幅回路２とＰＭＯＳトランジスタＭ９及びＭ１０で構成される第３差動増幅回路４は、共にＰチャネルトランジスタ差動入力構成であることから、第１差動増幅回路２及び第３差動増幅回路４の各入力電圧範囲は同様の制約を受ける。一方、ＰＭＯＳトランジスタＭ１及びＭ２を有する第１差動増幅回路２の差動出力信号Ｎ１及びＮ２をＰＭＯＳトランジスタＭ９及びＭ１０に対応して入力する。
【００３４】
このようにすることにより、Ｐチャネルトランジスタ差動入力構成において、正側電源電圧ＶＤＤ付近の電圧が反転入力端ＩＮ−及び非反転入力端ＩＮ＋に入力されても、差動出力信号Ｎ１及びＮ２の電圧は負側電源電圧ＶＳＳ付近に低下して第３差動増幅回路４の入力電圧の許容範囲となり、ＰＭＯＳトランジスタＭ９及びＭ１０を含む第３差動増幅回路４の出力信号Ｎ５には、入力信号Ｓ１及びＳ２が正しく伝達された信号となる。
【００３５】
同様に、ＮＭＯＳトランジスタＭ７及びＭ８で構成される第２差動増幅回路３とＮＭＯＳトランジスタＭ１５及びＭ１６で構成される第４差動増幅回路５は、共にＮチャネルトランジスタ差動入力構成であることから、第２差動増幅回路３及び第４差動増幅回路５の各入力電圧範囲は同様の制約を受ける。一方、ＮＭＯＳトランジスタＭ７及びＭ８を有する第２差動増幅回路３の差動出力信号Ｎ３及びＮ４をＮＭＯＳトランジスタＭ１５及びＭ１６に対応して入力する。
【００３６】
このようにすることにより、Ｎチャネルトランジスタ差動入力構成において、負側電源電圧ＶＳＳ付近の電圧が反転入力端ＩＮ−及び非反転入力端ＩＮ＋に入力されても、差動出力信号Ｎ３及びＮ４の電圧は正側電源電圧ＶＤＤ付近に上昇して第４差動増幅回路５の入力電圧の許容範囲となり、ＮＭＯＳトランジスタＭ１５及びＭ１６を含む第４差動増幅回路５の出力信号Ｎ６には、入力信号Ｓ１及びＳ２が正しく伝達された信号となる。
【００３７】
すなわち、出力信号Ｎ５は、相対する信号レベルをなす１対の入力信号Ｓ１及びＳ２が第１差動増幅回路２によって差動増幅され、更に第３差動増幅回路４によって増幅された信号となって出力回路６のＮＭＯＳトランジスタＭ１８のゲートに入力される。同様に、出力信号Ｎ６は、相対する信号レベルをなす１対の入力信号Ｓ１及びＳ２が第２差動増幅回路３によって差動増幅され、更に第４差動増幅回路５によって増幅された信号となって出力回路６のＰＭＯＳトランジスタＭ１７のゲートに入力される。
【００３８】
ＰＭＯＳトランジスタＭ１７及びＮＭＯＳトランジスタＭ１８はそれぞれオープンドレインであるため、出力回路６は、プッシュプル回路構成となって駆動能力の高い出力回路となる。また、出力端ＯＵＴがオープンになる無負荷時において、出力信号Ｎ５は、入力信号Ｓ１及びＳ２が正側電源電圧ＶＤＤから負側電源電圧ＶＳＳの範囲で振幅しても、第１差動増幅回路２及び第３差動増幅回路４を通ることによって負側電源電圧ＶＳＳ付近にはならない。同様に、出力端ＯＵＴがオープンになる無負荷時において、出力信号Ｎ６は、入力信号Ｓ１及びＳ２が正側電源電圧ＶＤＤから負側電源電圧ＶＳＳの範囲で振幅しても、第１差動増幅回路２及び第３差動増幅回路４を通ることによって正側電源電圧ＶＤＤ付近にはならない。これらのことから、出力端ＯＵＴから出力される信号は、電圧範囲の広い入力信号Ｓ１及びＳ２に追従した広電圧範囲の信号になる。
【００３９】
また、利得に関しても、第１差動増幅回路２から第４差動増幅回路５及び出力回路６によって高い利得を得ることができ、動作速度に関しても、第１差動増幅回路２及び第２差動増幅回路３の各負荷回路２２，３２を、ダイオード接続したＭＯＳトランジスタで形成するようにしたことから、第１差動増幅回路２及び第２差動増幅回路３における入力トランジスタのミラー効果による寄生容量を低減させることができるため、高速動作が可能になる。
【００４０】
また、第３差動増幅回路４におけるＮＭＯＳトランジスタＭ１２及び第４差動増幅回路５におけるＰＭＯＳトランジスタＭ１４をダイオード接続せずにカレントミラー回路を形成するようにした。このことは、第３差動増幅回路４及び第４差動増幅回路５が１出力構成であるシングルエンド型の差動増幅回路であり、出力回路６のＰＭＯＳトランジスタＭ１７及びＮＭＯＳトランジスタＭ１８を駆動させるためにダイナミックレンジを広げることに起因する。なお、本第１の実施の形態では、図中に位相補償用の容量等は付加しておらず、差動増幅器の使用用途によっては、適切な値の容量を回路内、又は外部に付加することで所望の特性を満足できるようにする。
【００４１】
このように、本第１の実施の形態における差動増幅器は、非反転入力端ＩＮ＋及び反転入力端ＩＮ−に、差動出力型の第１差動増幅回路２及び第２差動増幅回路３の各非反転入力端及び各反転入力端が対応して接続され、第１差動増幅回路２の１対の出力端がシングルエンド型の第３差動増幅回路４の相反する入力端に対応して接続され、第２差動増幅回路３の１対の出力端がシングルエンド型の第４差動増幅回路５の相反する入力端に対応して接続され、第３差動増幅回路４及び第５差動増幅回路５の各出力端がプッシュプル回路構成をなす出力回路６に接続されるようにした。このことから、高利得で、電圧範囲の広い相対する信号レベルの１対の入力信号に追従した広電圧範囲の出力信号を得ることができる。
【００４２】
【発明の効果】
上記の説明から明らかなように、本発明の差動増幅器によれば、１対の第１入力端及び第２入力端に制御電極がそれぞれ対応して接続された、互いに逆導電型の第１差動増幅回路及び第２差動増幅回路を備え、第１差動増幅回路及び第２差動増幅回路の各差動出力が、逆導電型の第３差動増幅回路及び第４差動増幅回路へ対応して入力され、第３差動増幅回路及び第４差動増幅回路の各出力信号を合成して出力するようにし、具体的には、前記第１差動増幅回路及び第３差動増幅回路の各差動対は同導電型をなすと共に、前記第２差動増幅回路及び第４差動増幅回路の各差動対は同導電型をなすようにした。このことから、広い電圧範囲の入出力が可能であり、利得も高く、簡単な構成でプッシュプル出力を行うことができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態における差動増幅器の構成例を示した図である。
【図２】図１の各差動増幅回路の内部構成例を示したブロック図である。
【図３】図２で示した差動増幅器１の回路例を示した図である。
【図４】従来の差動増幅器の例を示した回路図である。
【符号の説明】
１差動増幅器
２第１差動増幅回路
３第２差動増幅回路
４第３差動増幅回路
５第４差動増幅回路
６出力回路
２１第１の差動対
２２第１の負荷回路
２３第１の定電流源
３１第２の差動対
３２第２の負荷回路
３３第２の定電流源
４１第３の差動対
４２第３の負荷回路
４３第３の定電流源
５１第４の差動対
５２第４の負荷回路
５３第４の定電流源[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a complementary differential amplifier capable of obtaining a wide input voltage range and a wide output voltage range.
[0002]
[Prior art]
Conventionally, there has been a differential amplifier that has a push-pull output with a high output driving capability by using two differential amplifier circuits having opposite conductive differential pairs and a basic and simple output circuit configuration (for example, see Patent Document 1). 1). However, in such a configuration, for example, when the input signal is close to the power supply voltage in a no-load state, one of the output transistors becomes difficult to turn on, so that no current flows and the output becomes unstable. Was. There was no problem in operation because the power supply voltage range was wider than the input voltage of the differential amplifier or the voltage comparator, but in recent years, with the reduction of the power supply voltage, the input voltage range up to near the power supply voltage has been required. Have been.
[0003]
FIG. 4 is a diagram showing a conventional example of a differential amplifier having a wide input / output range.
In FIG. 4, the input voltage range is widened by using two differential pairs having different polarities, and the output signals of the two differential amplifier circuits 101 and 102 are both folded back by the folded cascode circuit 103. Further, the output signals from the folded cascode circuit 103 are combined and output by the output circuit 104 having a push-pull circuit configuration and an increased output voltage range.
[0004]
[Patent Document 1]
JP-A-61-148906
[Problems to be solved by the invention]
If such a differential amplifier is used, a wide characteristic of a desired input / output voltage range can be obtained, but there are the following problems in designing a circuit. Since a plurality of bias voltages Va to Vd are required in the folded cascode circuit, a bias voltage generation circuit is required, and it is difficult to determine an optimal transistor size of the folded cascode circuit.
[0006]
Also, it is complicated and difficult to determine the currents of the differential amplifier circuits 101 and 102 and the folded cascode circuit 103. In particular, if the transistor size is inappropriate, the operating state of the transistors in the folded cascode circuit 103 becomes three poles. There was a case where the region and the region between the five poles were mixed. On the other hand, in the output circuit 104, if a wide range of push-pull output configuration is obtained, it is necessary to drive both the PMOS transistor and the NMOS transistor in FIG. 4, and the output signal from the folded cascode circuit is synthesized. An output control circuit for controlling both the PMOS transistor and the NMOS transistor is required. For these reasons, there has been a problem that the circuit scale increases and the layout area increases.
[0007]
The present invention has been made in order to solve the above problems, and has as its object to obtain a complementary differential amplifier capable of inputting a wide voltage range and obtaining an output in a wide voltage range. .
[0008]
[Means for Solving the Problems]
A differential amplifier according to the present invention differentially amplifies a first input signal and a second input signal input corresponding to a pair of a first input terminal and a second input terminal and outputs the amplified signal from a predetermined output terminal. In a differential amplifier,
A first differential amplifier circuit of a differential output type in which the first input signal is input to a non-inverting input terminal and the second input signal is input to an inverting input terminal;
A differential output type second differential amplifier circuit in which the first input signal is input to a non-inverting input terminal and the second input signal is input to an inverting input terminal;
A single-ended third differential amplifier circuit in which a pair of output signals from the first differential amplifier circuit are input to corresponding input terminals;
A single-ended fourth differential amplifier circuit in which a pair of output signals from the second differential amplifier circuit are input to corresponding input terminals;
An output circuit that combines the output signals of the third differential amplifier circuit and the fourth differential amplifier circuit and outputs the combined signal to the predetermined output terminal;
With
Each differential pair of the first differential amplifier circuit and the second differential amplifier circuit has a reverse conductivity type, and each differential pair of the third differential amplifier circuit and the fourth differential amplifier circuit has a reverse conductivity type. It is what constitutes.
[0009]
Further, each differential pair of the first differential amplifier circuit and the third differential amplifier circuit has the same conductivity type, and each differential pair of the second differential amplifier circuit and the fourth differential amplifier circuit has the same conductivity type. It was made to be a conductive type.
[0010]
Specifically, the first differential amplifier circuit has an inverted output terminal connected to the inverted input terminal of the third differential amplifier circuit and a non-inverted output terminal connected to the non-inverted input terminal of the third differential amplifier circuit. The second differential amplifier circuit has an inverted output terminal connected to the inverted input terminal of the fourth differential amplifier circuit and a non-inverted output terminal connected to the non-inverted input terminal of the fourth differential amplifier circuit. It was to so.
[0011]
Further, the first differential amplifier circuit and the second differential amplifier circuit are formed by diodes in which load circuits connected to a differential pair are respectively connected in a forward direction to respective transistors forming the differential pair. May be performed.
[0012]
In the third differential amplifier circuit and the fourth differential amplifier circuit, a load circuit connected to a differential pair may form a current mirror circuit.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described in detail based on an embodiment shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a configuration example of the differential amplifier according to the first embodiment of the present invention.
In FIG. 1, a differential amplifier 1 differentially amplifies a pair of input signals S1 and S2 input to a non-inverting input terminal IN + and an inverting input terminal IN−, and outputs the amplified signal from an output terminal OUT. A differential output type first differential amplifier circuit 2 and a second differential amplifier circuit 3, a single-ended third differential amplifier circuit 4 and a fourth differential amplifier circuit 5, and a push-pull circuit. An output circuit 6 is provided.
[0014]
The non-inverting input terminal IN + of the differential amplifier 1 is connected to the non-inverting input terminals of the first differential amplifier circuit 2 and the second differential amplifier circuit 3, respectively. Are connected to respective inverting input terminals of the first differential amplifier circuit 2 and the second differential amplifier circuit 3. In the first differential amplifier circuit 2, the inverted output terminal o− is connected to the inverted input terminal of the third differential amplifier circuit 4, and the non-inverted output terminal o + is connected to the non-inverted input terminal of the third differential amplifier circuit 4. Have been. Similarly, in the second differential amplifier circuit 3, the inverted output terminal o− is connected to the inverted input terminal of the fourth differential amplifier circuit 5, and the non-inverted output terminal o + is the non-inverted input terminal of the fourth differential amplifier circuit 5. Connected to the end. Each output terminal of the third differential amplifier circuit 4 and the fourth differential amplifier circuit 5 is connected to the output circuit 6, and the output terminal of the output circuit 6 is connected to the output terminal OUT of the differential amplifier 1.
[0015]
The input pair of input signals S1 and S2 is input to corresponding input terminals of the first differential amplifier circuit 2 and the second differential amplifier circuit 3, and the voltage difference between the input signals S1 and S2 is the first differential signal. The voltage difference between the differential output signals of the first differential amplifier circuit 2 and the second differential amplifier circuit 3 is amplified by the amplifier circuit 2 and the second differential amplifier circuit 3, respectively. The signals are amplified by the fourth and fourth differential amplifier circuits 5 and output to the output circuit 6, respectively. The output circuit 6 combines the respective output signals of the third differential amplifier circuit 4 and the fourth differential amplifier circuit 5 and outputs the combined signal to the output terminal OUT, so that a wide voltage range can be input and a high gain is obtained. be able to.
[0016]
FIG. 2 is a block diagram showing an example of the internal configuration of each differential amplifier circuit of FIG.
In FIG. 2, the differential amplifier 1 operates using a first power supply voltage V1 and a second power supply voltage V2 as power supplies. The first differential amplifier circuit 2 supplies a current to the first differential pair 21, the first load circuit 22 connected to the first differential pair 21, and the first differential pair 21. One constant current source 23 is provided. A first constant current source 23 is connected between the first power supply voltage V1 and the first differential pair 21, and a first load circuit is connected between the second power supply voltage V2 and the first differential pair 21. 22 are connected. Input signals S1 and S2 are correspondingly input to each signal input end of the first differential pair 21, and each connection between the first differential pair 21 and the first load circuit 22 is connected to the first input terminal. The output terminals o + and o− of the differential amplifier circuit 2 are provided.
[0017]
The second differential amplifier circuit 3 supplies a current to the second differential pair 31, a second load circuit 32 connected to the second differential pair 31, and a second differential pair 31. And two constant current sources 33. A second constant current source 33 is connected between the second power supply voltage V2 and the second differential pair 31, and a second load circuit is connected between the first power supply voltage V1 and the second differential pair 31. 32 are connected. The input signals S1 and S2 are correspondingly input to each signal input end of the second differential pair 31, and each connection between the second differential pair 31 and the second load circuit 32 is connected to the second input terminal. The output terminals o + and o− of the differential amplifier circuit 3 are provided.
[0018]
The third differential amplifier circuit 4 supplies a current to the third differential pair 41, a third load circuit 42 connected to the third differential pair 41, and a third differential pair 41. 3 constant current sources 43. A third constant current source 43 is connected between the first power supply voltage V1 and the third differential pair 41, and a third load circuit is connected between the second power supply voltage V2 and the third differential pair 41. 42 are connected. To each signal input terminal of the third differential pair 41, a pair of differential output signals from the first differential amplifier circuit 2 are input correspondingly, and the third differential pair 41 and the third differential pair One connection to the load circuit 42 forms an output terminal of the third differential amplifier circuit 4 and is connected to the output circuit 6.
[0019]
The fourth differential amplifier circuit 5 supplies a current to the fourth differential pair 51, a fourth load circuit 52 connected to the fourth differential pair 51, and a fourth differential pair 51. 4 constant current sources 53. A fourth constant current source 53 is connected between the second power supply voltage V2 and the fourth differential pair 51, and a fourth load circuit is connected between the first power supply voltage V1 and the fourth differential pair 51. 52 are connected. To each signal input terminal of the fourth differential pair 51, a pair of differential output signals from the second differential amplifier circuit 3 is input correspondingly, and the fourth differential pair 51 and the fourth differential pair One connection to the load circuit 52 forms an output terminal of the fourth differential amplifier circuit 5 and is connected to the output circuit 6.
[0020]
Here, since the first and third differential pairs are of the same conductivity type, the input signals S1 and S2 of the first differential amplifier circuit 2 and the third differential amplifier circuit 4 are the first differential amplifier circuit. 2, the differential output signal of the first differential amplifier circuit 2 is within the allowable range of the input voltage of the third differential amplifier circuit 4. Similarly, in the second differential amplifier circuit 2 and the fourth differential amplifier circuit 5, since the second and fourth differential pairs are of the same conductivity type, the input signals S1 and S2 are the second differential amplifier circuit. Even when the input voltage exceeds the allowable range of the input voltage of the third differential amplifier circuit 3, the differential output signal of the second differential amplifier circuit 3 is within the allowable range of the input voltage of the fourth differential amplifier circuit 5. From these facts, the output signals of the third differential amplifier circuit 4 and the fourth differential amplifier circuit 5 input to the output circuit 6 are those in which the input signals S1 and S2 are correctly transmitted, and are synthesized by the output circuit 6. And output to the output terminal OUT.
[0021]
FIG. 3 is a diagram showing a circuit example of the differential amplifier 1 shown in FIG.
In FIG. 3, the first power supply voltage V1 forms a positive power supply voltage VDD, and the second power supply voltage V2 forms a negative power supply voltage VSS, for example, a ground voltage. The first differential amplifier circuit 2 includes PMOS transistors M1 and M2, NMOS transistors M3 and M4, and a first constant current source 23. The PMOS transistors M1 and M2 form a first differential pair 21. , NMOS transistors M3 and M4 form a first load circuit 22.
[0022]
The sources of the PMOS transistors M1 and M2 are connected, and a first constant current source 23 is connected between the connection and the positive power supply voltage VDD. An NMOS transistor M3 is connected between the drain of the PMOS transistor M1 and the negative power supply voltage VSS, and an NMOS transistor M4 is connected between the drain of the PMOS transistor M2 and the negative power supply voltage VSS. The gate of the PMOS transistor M1 forms the inverting input terminal of the differential amplifier 1, and the gate of the PMOS transistor M2 forms the non-inverting input terminal of the differential amplifier 1.
[0023]
The gate of the NMOS transistor M3 is connected to the drain of the NMOS transistor M3, the gate of the NMOS transistor M4 is connected to the drain of the NMOS transistor M4, and the NMOS transistors M3 and M4 each form a diode. The connection between the PMOS transistor M1 and the NMOS transistor M3 forms the output terminal o + of the first differential amplifier circuit 2, and the connection between the PMOS transistor M2 and the NMOS transistor M4 forms the output terminal o− of the first differential amplifier circuit 2. Has made.
[0024]
The second differential amplifier circuit 3 includes PMOS transistors M5 and M6, NMOS transistors M7 and M8, and a second constant current source 33. The NMOS transistors M7 and M8 form a second differential pair 31. , PMOS transistors M5 and M6 form a second load circuit 32. The sources of the NMOS transistors M7 and M8 are connected, and the second constant current source 33 is connected between the connection and the negative power supply voltage VSS.
[0025]
A PMOS transistor M5 is connected between the positive power supply voltage VDD and the drain of the NMOS transistor M7, and a PMOS transistor M6 is connected between the power supply voltage VDD and the drain of the NMOS transistor M8. The gate of the NMOS transistor M7 forms the inverting input terminal of the second differential amplifier circuit 3, and the gate of the NMOS transistor M8 forms the non-inverting input terminal of the second differential amplifier circuit 3. The gate of the PMOS transistor M5 is connected to the drain of the PMOS transistor M5, the gate of the PMOS transistor M6 is connected to the drain of the PMOS transistor M6, and the PMOS transistors M5 and M6 each form a diode. The connection between the PMOS transistor M5 and the NMOS transistor M7 forms the output terminal o + of the second differential amplifier circuit 3, and the connection between the PMOS transistor M6 and the NMOS transistor M8 forms the output terminal o- of the second differential amplifier circuit 3. No.
[0026]
The third differential amplifier circuit 4 includes PMOS transistors M9 and M10, NMOS transistors M11 and M12, and a third constant current source 43. The PMOS transistors M9 and M10 form a third differential pair 41. , NMOS transistors M11 and M12 form a current mirror circuit to form a third load circuit 42.
[0027]
The sources of the PMOS transistors M9 and M10 are connected, and a third constant current source 43 is connected between the connection and the positive power supply voltage VDD. An NMOS transistor M11 is connected between the drain of the PMOS transistor M9 and the negative power supply voltage VSS, and an NMOS transistor M12 is connected between the drain of the PMOS transistor M10 and the negative power supply voltage VSS. The gate of the PMOS transistor M9 forms an inverting input terminal of the third differential amplifier circuit 4, and the gate of the PMOS transistor M10 forms a non-inverting input terminal of the third differential amplifier circuit 4. The gates of the NMOS transistors M11 and M12 are connected, and the connection is connected to the drain of the NMOS transistor M11. The connection between the PMOS transistor M10 and the NMOS transistor M12 forms the output terminal of the third differential amplifier circuit 4.
[0028]
The fourth differential amplifier circuit 5 includes PMOS transistors M13 and M14, NMOS transistors M15 and M16, and a fourth constant current source 53. The NMOS transistors M15 and M16 form a fourth differential pair 51. , PMOS transistors M13 and M14 form a current mirror circuit to form a fourth load circuit 52. The sources of the NMOS transistors M15 and M16 are connected, and a fourth constant current source 53 is connected between the connection and the negative power supply voltage VSS.
[0029]
A PMOS transistor M13 is connected between the positive power supply voltage VDD and the drain of the NMOS transistor M15, and a PMOS transistor M14 is connected between the positive power supply voltage VDD and the drain of the NMOS transistor M16. The gate of the NMOS transistor M15 forms the inverting input terminal of the fourth differential amplifier circuit 5, and the gate of the NMOS transistor M16 forms the non-inverting input terminal of the fourth differential amplifier circuit 5. The gates of the PMOS transistors 13 and M14 are connected, and the connection is connected to the drain of the PMOS transistor M13. The connection between the PMOS transistor M14 and the NMOS transistor M16 forms the output terminal of the fourth differential amplifier circuit 5.
[0030]
The output circuit 6 includes a PMOS transistor M17 and an NMOS transistor M18. The PMOS transistor M17 and the NMOS transistor M18 are connected in series between the positive power supply voltage VDD and the negative power supply voltage VSS. The gate of the PMOS transistor M17 is connected to the output terminal of the fourth differential amplifier circuit 5, and the gate of the NMOS transistor M18 is connected to the output terminal of the third differential amplifier circuit 4. The connection between the PMOS transistor M17 and the NMOS transistor M18 is connected to the output terminal OUT, and the output circuit 6 forms a push-pull circuit.
[0031]
In such a configuration, the input signals S1 and S2 are input to a first differential pair 21 composed of PMOS transistors M1 and M2 and a second differential pair 31 composed of NMOS transistors M7 and M8, respectively. Is done. Next, the differential output signals N1 and N2 of the first differential amplifier circuit 2 are input to a third differential pair 41 composed of PMOS transistors M9 and M10, respectively. The dynamic output signals N3 and N4 are input to a fourth differential pair 51 including NMOS transistors M15 and M16, respectively.
[0032]
The input signals S1 and S2 are differentially amplified by a first differential amplifier circuit 2 and a second differential amplifier circuit 3, respectively, and the differential output signals N1 and N2 from the first differential amplifier circuit 2 are converted to a second differential amplifier circuit. The differential output signals N3 and N4 are output from the amplifier circuit 3 and input to the corresponding third and fourth differential amplifier circuits 4 and 5 at the next stage. Normally, as shown in FIG. 3, when each of the differential amplifier circuits 2 to 4 is constituted by CMOS transistors, the input voltage range is the potential difference of the constant current source and the gate-source voltage of the transistors forming the differential pair. Vgs is restricted by the potential difference of the load circuit.
[0033]
Therefore, the first differential amplifier circuit 2 including the PMOS transistors M1 and M2 and the third differential amplifier circuit 4 including the PMOS transistors M9 and M10 both have a P-channel transistor differential input configuration. Each input voltage range of the first differential amplifier circuit 2 and the third differential amplifier circuit 4 is similarly restricted. On the other hand, the differential output signals N1 and N2 of the first differential amplifier circuit 2 having the PMOS transistors M1 and M2 are input corresponding to the PMOS transistors M9 and M10.
[0034]
By doing so, in the P-channel transistor differential input configuration, even if a voltage near the positive power supply voltage VDD is input to the inverting input terminal IN− and the non-inverting input terminal IN +, the differential output signals N1 and N2 The voltage drops to the vicinity of the negative power supply voltage VSS and becomes an allowable range of the input voltage of the third differential amplifier circuit 4. The output signal N5 of the third differential amplifier circuit 4 including the PMOS transistors M9 and M10 includes the input signal. S1 and S2 are correctly transmitted signals.
[0035]
Similarly, the second differential amplifier circuit 3 composed of the NMOS transistors M7 and M8 and the fourth differential amplifier circuit 5 composed of the NMOS transistors M15 and M16 both have an N-channel transistor differential input configuration. , The respective input voltage ranges of the second differential amplifier circuit 3 and the fourth differential amplifier circuit 5 are similarly restricted. On the other hand, the differential output signals N3 and N4 of the second differential amplifier circuit 3 having the NMOS transistors M7 and M8 are input corresponding to the NMOS transistors M15 and M16.
[0036]
Thus, in the N-channel transistor differential input configuration, even if a voltage near the negative power supply voltage VSS is input to the inverting input terminal IN− and the non-inverting input terminal IN +, the differential output signals N3 and N4 The voltage rises to the vicinity of the positive power supply voltage VDD and becomes an allowable range of the input voltage of the fourth differential amplifier circuit 5, and the output signal N6 of the fourth differential amplifier circuit 5 including the NMOS transistors M15 and M16 includes the input signal. S1 and S2 are correctly transmitted signals.
[0037]
That is, the output signal N5 is a signal obtained by differentially amplifying the pair of input signals S1 and S2 having the opposite signal level by the first differential amplifier circuit 2, and further amplifying by the third differential amplifier circuit 4. And input to the gate of the NMOS transistor M18 of the output circuit 6. Similarly, the output signal N6 is a signal obtained by differentially amplifying a pair of input signals S1 and S2 having opposite signal levels by the second differential amplifier circuit 3 and further amplifying by the fourth differential amplifier circuit 5. The signal is input to the gate of the PMOS transistor M17 of the output circuit 6.
[0038]
Since each of the PMOS transistor M17 and the NMOS transistor M18 has an open drain, the output circuit 6 has a push-pull circuit configuration and is an output circuit having a high driving capability. Further, at the time of no load in which the output terminal OUT is open, the output signal N5 is the first differential amplifier circuit even if the input signals S1 and S2 oscillate in the range from the positive power supply voltage VDD to the negative power supply voltage VSS. By passing through the second and third differential amplifier circuits 4, the voltage does not become near the negative power supply voltage VSS. Similarly, at the time of no load when the output terminal OUT is open, the output signal N6 is the first differential amplification signal even if the input signals S1 and S2 have amplitudes in the range from the positive power supply voltage VDD to the negative power supply voltage VSS. By passing through the circuit 2 and the third differential amplifier circuit 4, the voltage does not become near the positive power supply voltage VDD. For these reasons, the signal output from the output terminal OUT is a signal in a wide voltage range that follows the input signals S1 and S2 in a wide voltage range.
[0039]
Further, with respect to the gain, a high gain can be obtained from the first differential amplifier circuit 2 to the fourth differential amplifier circuit 5 and the output circuit 6, and the operating speed can also be increased. Since each of the load circuits 22 and 32 of the dynamic amplifying circuit 3 is formed by a diode-connected MOS transistor, the parasitic effect of the input transistors in the first differential amplifying circuit 2 and the second differential amplifying circuit 3 due to the Miller effect. Since the capacity can be reduced, high-speed operation becomes possible.
[0040]
Further, a current mirror circuit is formed without connecting the NMOS transistor M12 in the third differential amplifier circuit 4 and the PMOS transistor M14 in the fourth differential amplifier circuit 5 with a diode. This means that the third differential amplifier circuit 4 and the fourth differential amplifier circuit 5 are single-ended type differential amplifier circuits having one output configuration, and drive the PMOS transistor M17 and the NMOS transistor M18 of the output circuit 6. To increase the dynamic range. In the first embodiment, a capacity for phase compensation is not added in the figure, and a capacity having an appropriate value is added inside or outside the circuit depending on the usage of the differential amplifier. Thus, desired characteristics can be satisfied.
[0041]
As described above, the differential amplifier according to the first embodiment includes a differential output type first differential amplifier circuit 2 and a second differential amplifier circuit 3 at the non-inverting input terminal IN + and the inverting input terminal IN−. Are connected correspondingly, and a pair of output terminals of the first differential amplifier circuit 2 correspond to opposing input terminals of the single-ended third differential amplifier circuit 4. And a pair of output terminals of the second differential amplifier circuit 3 are connected corresponding to the opposite input terminals of the single-ended fourth differential amplifier circuit 5, and the third differential amplifier circuit 4 Each output terminal of the fifth differential amplifier circuit 5 is connected to an output circuit 6 having a push-pull circuit configuration. From this, it is possible to obtain an output signal having a high gain and a wide voltage range following a pair of input signals having opposite signal levels in a wide voltage range.
[0042]
【The invention's effect】
As is apparent from the above description, according to the differential amplifier of the present invention, the first and second input terminals are respectively connected to the control electrodes in a corresponding manner. A differential amplifier circuit and a second differential amplifier circuit, wherein each differential output of the first differential amplifier circuit and the second differential amplifier circuit is a reverse conductive third differential amplifier circuit and a fourth differential amplifier circuit. The first differential amplifier circuit and the third differential amplifier circuit combine the output signals of the third differential amplifier circuit and the fourth differential amplifier circuit and output the combined signals. Each differential pair of the dynamic amplifier circuit has the same conductivity type, and each differential pair of the second differential amplifier circuit and the fourth differential amplifier circuit has the same conductivity type. Thus, input / output in a wide voltage range is possible, gain is high, and push-pull output can be performed with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a differential amplifier according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating an example of an internal configuration of each differential amplifier circuit of FIG. 1;
FIG. 3 is a diagram illustrating a circuit example of the differential amplifier 1 illustrated in FIG. 2;
FIG. 4 is a circuit diagram showing an example of a conventional differential amplifier.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 differential amplifier 2 first differential amplifier circuit 3 second differential amplifier circuit 4 third differential amplifier circuit 5 fourth differential amplifier circuit 6 output circuit 21 first differential pair 22 first load circuit 23 1 constant current source 31 second differential pair 32 second load circuit 33 second constant current source 41 third differential pair 42 third load circuit 43 third constant current source 51 fourth difference Dynamic pair 52 fourth load circuit 53 fourth constant current source

Claims

A differential amplifier that differentially amplifies a first input signal and a second input signal input corresponding to a pair of a first input terminal and a second input terminal and outputs the amplified signal from a predetermined output terminal,
A first differential amplifier circuit of a differential output type in which the first input signal is input to a non-inverting input terminal and the second input signal is input to an inverting input terminal;
A differential output type second differential amplifier circuit in which the first input signal is input to a non-inverting input terminal and the second input signal is input to an inverting input terminal;
A single-ended third differential amplifier circuit in which a pair of output signals from the first differential amplifier circuit are input to corresponding input terminals;
A single-ended fourth differential amplifier circuit in which a pair of output signals from the second differential amplifier circuit are input to corresponding input terminals;
An output circuit that combines the output signals of the third differential amplifier circuit and the fourth differential amplifier circuit and outputs the combined signal to the predetermined output terminal;
With
Each differential pair of the first differential amplifier circuit and the second differential amplifier circuit has a reverse conductivity type, and each differential pair of the third differential amplifier circuit and the fourth differential amplifier circuit has a reverse conductivity type. A differential amplifier.

Each differential pair of the first differential amplifier circuit and the third differential amplifier circuit has the same conductivity type, and each differential pair of the second differential amplifier circuit and the fourth differential amplifier circuit has the same conductivity type. 2. The differential amplifier according to claim 1, wherein:

The first differential amplifier circuit has an inverted output terminal connected to an inverted input terminal of a third differential amplifier circuit, and a non-inverted output terminal connected to a non-inverted input terminal of a third differential amplifier circuit. In the two differential amplifier circuit, the inverted output terminal is connected to the inverted input terminal of the fourth differential amplifier circuit, and the non-inverted output terminal is connected to the non-inverted input terminal of the fourth differential amplifier circuit. The differential amplifier according to claim 1, wherein

The first differential amplifier circuit and the second differential amplifier circuit are formed by diodes in which load circuits connected to a differential pair are respectively connected to respective transistors forming the differential pair in a forward direction. The differential amplifier according to claim 1, 2 or 3, wherein:

5. The third differential amplifier circuit and the fourth differential amplifier circuit, wherein a load circuit connected to a differential pair forms a current mirror circuit. Differential amplifier.