JP2004342806A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct an etching having an excellent reproducibility by using a trend at a previously measured etching rate regarding a manufacturing method for a semiconductor device. <P>SOLUTION: The etching conditions at the next treatment unit are determined on the basis of the result of an etching at the previously etching-treated treatment unit under specified conditions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【００２９】
次に、上記のモデルにより処理した場合のシミュレーション結果を図５を参照して説明する。
図５参照
図５は、５点の移動平均を取った場合のトレンチ深さＤの累積処理ロット数依存性のシミュレーション結果を示したものであり、比較のために図２に示した実データも併せて示している。
【００３０】
この場合のシミュレーションは、まず、
（１）直前の５つのロットのエッチングレートＲ_ｎ−５ 〜Ｒ_ｎ−１ の移動平均から、上記の式（１）によって、ｎ番目のロットの見なしエッチングレートＲ_ｎ を求める。
【００３１】
（２）次いで、求めた見なしエッチングレートＲ_ｎ と目標トレンチ深さＤ_{ｔａｒｇｅｔ}からエッチングＴ_ｎ を、
Ｔ_ｎ ＝Ｄ_{ｔａｒｇｅｔ}／Ｒ_ｎ
として求める。
【００３２】
（３）次いで、従来の実測値におけるｎ番目のロットにおけるエッチング時間Ｔ_{ａｃｔｕａｌ}（＝８２秒）と得られたトレンチ深さＤ_{ａｃｔｕａｌ}から、実際のエッチングレートＲ_{ａｃｔｕａｌ}を、
Ｒ_{ａｃｔｕａｌ}＝Ｄ_{ａｃｔｕａｌ}／Ｔ_{ａｃｔｕａｌ}＝Ｄ_{ａｃｔｕａｌ}／８２秒
として求める。
【００３３】
（４）次いで、求めたＲ_{ａｃｔｕａｌ}と、先に求めたＴ_ｎ とにより、ｎ番目のロットの予想トレンチ深さＤ_ｎ を、
Ｄ_ｎ ＝Ｔ_ｎ ×Ｒ_{ａｃｔｕａｌ}
として求める。
【００３４】
このようにして求めた予想トレンチ深さＤ_ｎ をプロットしたのが、図５のシミュレーション結果であり、図から明らかなように、トレンチ深さの下降トレンドはなくなり、また、ロット間のトレンチ深さのバラツキも低減していることが分かる。
【００３５】
このように、本発明の第１の実施の形態においては、ｎ番目のロットのエッチング処理を行う場合に、処理直近の３個以上のロットのエッチングにおける移動平均を求めて、ｎ番目のロットのエッチング時間を決定しているので、累積処理依存性をなくすとともに、各ロット間のバラツキを小さくすることができる。
【００３６】
また、本発明の第１の実施の形態においては、先行するエッチング部材を必要とすることがなく、エッチング装置と処理ロットとの最適合の組合せを検討する必要もなく、且つ、トレンチ深さの測定以外の測定が不要になるので、工程が簡素化され、スループットが向上する。
【００３７】
次に、図６を参照して、ウェハ毎のエッチング条件の設定に関する本発明の第２の実施の形態のエッチング方法を説明する。
図６参照
図６は、本発明の第２の実施の形態のエッチング方法の概念的構成図であり、あり、計測装置１０と、エッチング装置２０と、真空搬送機構３０と、制御装置４０とによって基本的なエッチングシステムが構成される。
【００３８】
なお、この場合の計測装置１０は、例えば、表面ＳＥＭ（走査型電子顕微鏡）観察装置であり、エッチング装置２０は、例えば、プラズマエッチング装置であり、真空搬送機構３０は、例えば、エッチング装置２０のロードロックと計測装置とを連結するゲートバルブを備えた真空搬送室である。
【００３９】
例えば、微細ポリシリコン配線のエッチング工程においては、レジストパターンの形成→レジストパターンの計測→エッチング処理→エッチングパターンの計測という手順で処理が行われる。
なお、この間の各工程の制御は、制御装置４０によって行う。
【００４０】
したがって、この場合には、微細ポリシリコン配線をエッチングするためのレジストパターンを形成した基板を表面ＳＥＭ観察装置でレジストパターンの形状を計測したのち、真空搬送室を介してプラズマエッチング装置に搬入し、プラズマエッチング装置においてエッチングを行い、次いで、エッチング処理終了後の基板を真空搬送室を介して表面ＳＥＭ観察装置に搬入してエッチングによって形成した微細ポリシリコン配線のパターンを計測する。
なお、従来においては、エッチング処理後のウェハは、一旦、大気中に取り出して計測装置に搬送していた。
【００４１】
次いで、レジストパターンの形状の計測結果と、エッチング後の微細ポリシリコン配線のパターンの計測結果との比較を行い、所定の微細ポリシリコン配線パターンが得られるように次のウェハのエッチング条件を決定して、同じサイクルを繰り返す。
【００４２】
例えば、微細ポリシリコン配線のエッチング工程においては、その線幅Ｗと微調整エッチング時間ΔＴとの間には、Ｗ_０ を微調整エッチング時間なしの線幅、ａ（＞０）を比例係数とした場合、
Ｗ＝Ｗ_０ −ａΔＴ
の関係がある。
【００４３】
したがって、ある１枚のウェハのエッチングの終了後に線幅Ｗを表面ＳＥＭ観察装置で計測し、所望の線幅Ｗ_{ｔａｒｇｅｔ}との差ΔＷ（＝Ｗ_{ｔａｒｇｅｔ}−Ｗ）を求め、
ΔＷ＝ａΔＴ、即ち、ΔＴ＝ΔＷ／ａ
となる微調整エッチング時間ΔＴを求め、次のウェハをΔＷ＞０の場合には微調整エッチング時間ΔＴだけ余分にエッチングを行う。
また、ΔＷ＜０の場合には、微調整エッチング時間ΔＴだけ短くエッチングを行う。
【００４４】
なお、エッチングするウェハにおけるレジストパターンにおける線幅が、直近処理ウェハにおけるレジストパターンにおける線幅と異なっている場合には、この変動分も考慮して微調整エッチング時間ΔＴを決定する必要がある。
【００４５】
この本発明の第２の実施の形態においては、直近処理ウェハの計測を行う場合に、計測装置１０とエッチング装置２０との間を真空搬送機構３０によって結合しているので、エッチング後のウェハを取り出して計測装置１０に搬送する際に、エッチング装置２０のロードロックのベントと計測装置１０を真空排気する必要がなく、エッチング装置２０で次のウェハを処理を開始するまでの待ち時間も不要になるので、スループットを向上することができる。
【００４６】
以上、本発明の各実施の形態を説明してきたが、本発明は各実施の形態に記載した構成に限られるものではなく、各種の変更が可能である。
例えば、上記の第１の実施の形態においては、トレンチの形成工程として説明してきたが、トレンチの形成工程に限られるものではない。
【００４７】
即ち、ドライエッチング工程においては、エッチング残渣や反応生成物がチャンバーの内壁に付着し、処理ロットが累積するに連れてエッチングレートが低下する傾向となる場合があるので、このような累積処理数がエッチング結果に影響を与える各エッチング工程に適用されるものである。
【００４８】
また、上記の第１の実施の形態においては、処理単位をロットとしたが、ロットに限られるものではなく、ウェハを処理単位としても良いものであり、その場合には、直近の３枚以上ウェハのエッチングレートの移動平均を、処理ウェハの見なしエッチングレートとしてエッチング時間を決定すれば良いものである。
【００４９】
また、上記の第２の実施の形態においては、直前の１枚の処理結果によって、次のウェハのエッチング処理条件を決定しているが、上記の第１の実施の形態と同様に、直近の３枚以上ウェハの処理結果の移動平均によりエッチング条件を決定しても良いものである。
【００５０】
この場合、参照する処理結果は、直近の処理結果に限らず、エッチング装置の洗浄直後は、必要に応じて前回のエッチング装置の洗浄処理直後の処理結果も移動平均に加えエッチング条件を決定しても良いものである。
【００５１】
また、上記の第２の実施の形態においては、レジストパターンの計測→エッチング処理→エッチングパターンの計測のサイクルで処理を行っているが、レジストパターンの計測は事前に一括して行っても良いものである。
【００５２】
この場合、エッチング処理→エッチングパターンの計測→次のウェハエッチング処理・・・という連続処置を待ち時間なしで行うことができるので、さらに所定の線幅と出来上がり線幅との差ΔＷを減少させることが可能になる。
【００５３】
また、上記の各実施の形態においては、決定する処理条件をエッチング時間としているが、エッチング時間に限られるものではなく、エッチング時における基板温度、或いは、エッチングガスの流量等の他のエッチング条件を微変更しても良いものである。
【００５４】
また、上記の各実施の形態においては、シリコン基板に対するトレンチの形成工程或いは、シリコン基板上に設けるポリシリコン配線のパターニング工程として説明しているが、基板はシリコンに限られるものではなく、ＧａＡｓ等の化合物半導体基板にも適用されるものである。
【００５５】
ここで、再び図１を参照して、本発明の詳細な特徴を説明する。
再び、図１参照
（付記１） 所定の条件で既にエッチング処理された処理単位のエッチング結果を基にして、次の処理単位のエッチング条件を決定することを特徴とする半導体装置の製造方法。
（付記２） 直近の３処理単位以上のエッチング結果の移動平均値を、次の処理単位のエッチング結果と見なして次の処理単位のエッチング条件を決定することを特徴とする付記１記載の半導体装置の製造方法。
（付記３） 上記エッチング結果がエッチング深さであって、上記次の処理単位のエッチング条件として、エッチング時間を決定することを特徴とする付記２記載の半導体装置の製造方法。
（付記４） 上記処理単位が、ロットまたはウェハのいずれかであることを特徴とする付記１乃至３のいずれか１に記載の半導体装置の製造方法。
（付記５） 上記エッチング処理が、トレンチの形成工程であることを特徴とする付記１乃至４のいずれか１に記載の半導体装置の製造方法。
（付記６） 上記処理単位がウェハであり、パターン形状の計測装置とエッチング装置との間を真空搬送し、ウェハ毎のパターン形状の計測結果を基にウェハ毎にエッチング条件を決定することを特徴とする付記１記載の半導体装置の製造方法。
【００５６】
【発明の効果】
本発明によれば、直近のエッチング結果を反映させて次のエッチング処理の条件を決定しているので、処理装置の洗浄後の累積処理数や処理装置の状態に依存することなく、所定のトレンチ深さや線幅等の設定目標を精度良く達成することができ、半導体装置の信頼性の向上と低コスト化に寄与するところが大きい。
【図面の簡単な説明】
【図１】本発明の原理的構成の説明図である。
【図２】トレンチ深さＤの累積処理ロット数依存性の説明図である。
【図３】トレンチ深さＤのエッチング時間依存性の説明図である。
【図４】移動平均値を用いた場合のトレンチ深さＤの累積処理ロット数依存性の説明図である。
【図５】５点の移動平均を取った場合のトレンチ深さＤの累積処理ロット数依存性のシミュレーション結果の説明図である。
【図６】本発明の第２の実施の形態のエッチング方法の概念的構成図である。
【図７】エッチング時間を８２秒に設定した場合の実際のトレンチ深さの累積処理ロット数依存性の説明図である。
【符号の説明】
１０ 計測装置
２０ エッチング装置
３０ 真空搬送手段
４０ 制御装置[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device characterized by a method of determining etching conditions for performing highly reproducible etching without depending on the number of accumulated processes. is there.
[0002]
[Prior art]
2. Description of the Related Art An etching process occupies an important position in a pattern forming process of a semiconductor device.
[0003]
With such miniaturization, at present, plasma etching is generally used in an etching process, and in this plasma etching, an etching time considered appropriate for obtaining a predetermined etching depth is tried. The etching is performed by mistake and the etching is performed for the set constant etching time.
[0004]
For example, even when trenches for element isolation are formed in a silicon wafer by an etching process, a plurality of lots are continuously processed for a predetermined constant etching time.
For example, when a trench having a predetermined depth (D _t : target value) is formed, the etching time is set to 82 seconds.
[0005]
In such an etching process, there is a phenomenon that the etching rate is reduced depending on the number of processed wafers after the cleaning (wet cleaning) of the plasma etching apparatus, and the depth of the trench is gradually reduced by the etching method for a fixed time. Therefore, this situation will be described with reference to FIG.
[0006]
FIG. 7 shows the dependence of the actual trench depth on the cumulative number of processed lots when the etching time is set to 82 seconds when forming a trench having a predetermined depth (D _t : target value). It is a thing.
As is clear from the figure, there is a trend in which the trench depth becomes shallower, that is, a lowering trend in which the etching rate decreases, depending on the number of processing lots after cleaning of the plasma etching apparatus.
[0007]
Therefore, in the process of forming such a trench, when the etching rate fluctuates due to various differences in the etching environment, the etching rate of the silicon substrate is converted from the etching rate in the etching step of the polycrystalline silicon layer provided on the silicon substrate. It has also been proposed to set the etching time by setting (for example, see Patent Document 1).
[0008]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 08-064579
[Problems to be solved by the invention]
However, when there is no member to be etched in advance on the silicon substrate, there is a problem that the above method cannot be applied, and further, it is necessary to measure the etching rate of the preceding etching member in real time. There is a problem.
[0010]
In addition, when the etching rate for processing a certain lot is predicted from the simple fluctuation trend shown in FIG. Since the square of the correlation coefficient (R ² ) is as small as R ² = 0.6211 in the case of FIG. 7, there is a problem that the obtained trench depth varies greatly.
[0011]
In the oxide film etching process, the performance of the processing apparatus is evaluated based on the processing result of the previous lot, and a moving average of CD (Critical Dimension) loss in the oxide film etching, that is, a decrease in a minute length such as a line width. It has been proposed to determine an optimal combination of a processing apparatus and a lot to be processed from a moving average of the processing apparatus (see, for example, JP-A-2001-189247).
[0012]
For example, the exposure amount is adjusted according to the variation in the resist film thickness before processing. This is performed by measuring the resist film thickness of the preceding pilot wafer in the lot to be processed, which has been conventionally performed, and according to the value. In this case, the method of adjusting the exposure amount is applied, and the etching condition is not changed.
[0013]
In this case, in addition to the measurement of the trench depth for confirming the etching result, various measurements such as the measurement of the resist film thickness are required in advance, and there is a problem that the number of steps is increased.
[0014]
Therefore, an object of the present invention is to perform etching with good reproducibility using a trend of an etching rate measured in advance.
[0015]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the basic configuration of the present invention. Here, means for solving the problem in the present invention will be described with reference to FIG.
Referring to FIG. 1, in order to achieve the above object, according to the present invention, in a method of manufacturing a semiconductor device, an etching condition of a next processing unit is determined based on an etching result of a processing unit already etched under predetermined conditions. It is characterized by the following.
[0016]
As described above, by determining the etching condition of the next processing unit based on the etching result of the processing unit that has already been subjected to the etching processing, it is possible to obtain a processing result with little variation even if the cumulative processing unit increases.
[0017]
In this case, by using the moving average value of the etching results of the latest three processing units or more as the etching results of the processing units already etched, the square of the sample correlation coefficient (R ² ) Can be made large, for example, close to 0.9, whereby a processing result with little variation can be obtained.
[0018]
In this case, the etching time of the next processing unit is the most typical condition.
As a processing unit, either a lot or a wafer is a typical processing unit.
[0019]
Such a method can be applied to a process of forming a trench whose depth becomes shallower as the number of processing units is accumulated after the cleaning of the etching apparatus, whereby a trench depth with less variation can be obtained.
[0020]
Alternatively, the processing unit may be a wafer, and a vacuum transfer may be performed between the pattern shape measuring device and the etching device, and the etching conditions may be determined for each wafer based on the pattern shape measurement result for each wafer.
[0021]
In this way, by performing vacuum transfer between the pattern shape measuring device and the etching device, vacuum evacuation before the measurement of the pattern shape after processing becomes unnecessary, so that continuous processing becomes possible. Throughput can be improved.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Here, an etching method according to the first embodiment of the present invention will be described with reference to FIGS.
First, a trench for element isolation by STI (Shallow Trench Isolation) is formed by plasma etching, and the dependence of the trench depth on the number of processed lots is examined.
The processing conditions at this time are as follows: when etching a silicon substrate with a plasma of a mixed gas containing HBr + Cl _{2 as a} main component, the etching time is set to 82 seconds, and a trench having a target depth (D _t : target value) is formed. I do.
[0023]
FIG. 2 is a diagram in which the average values of the trench depths D for each processing lot are arranged in the order of the processing lots. In this case as well, as in the case of FIG. There is a trend in which D decreases.
[0024]
Here, a change in the trench depth D when the etching time is slightly changed was examined, and will be described with reference to FIG.
FIG. 3 is a diagram showing the etching time dependency of the trench depth D. As is clear from the drawing, the trench depth D increases with the etching time.
In this case, if the trench depth D and the etching time are D _i , the etching rate is R _i , and the etching time is T _i ,
D _i = R _i × T _i , or R _i = D _i / T _i
Can be approximated by a linear expression represented by the following expression, and it has been found that the trench depth can be adjusted by about 3 nm by adjusting the etching time by about 1 second.
[0025]
Thus, it has been proved that the trench depth can be adjusted by adjusting the etching time.
[0026]
4 (a) and 4 (b). FIG. 4 (a) is a diagram showing the dependence of the trench depth D on the number of cumulative processing lots when the number of moving average points is 2 to 6 points. FIG. 4B is a diagram showing the square (R ² ) of the sample correlation coefficient in each moving average.
[0027]
FIG 4 (b) the sample correlation coefficient squared shown as seen from the values of ^{(R 2),} the moving average of the two points _R ^MA2 2 = 0.78, and the but variation increases, the three or more points taking a moving average, R ² can be suppressed to about 0.9, and the variation of the trench depth less.
[0028]
Accordingly, regarded as the etching rate R _n of the n-th lot comprising a moving average value of the etching rate of the last three lots or more of the m lot as etched, in cases where the target trench depth D _target,
T _n = D _target / R _n
In the etching time T _n may be performed an etching process resulting in.
Here, R _n is represented by the following equation (1), and the notation of Σ in the equation (1) denotes nm which is m-m before the (n−1) -th lot immediately before the n-th lot. Means the sum up to the lot.
(Equation 1)

[0029]
Next, a simulation result when processing is performed using the above model will be described with reference to FIG.
FIG. 5 shows a simulation result of the dependence of the trench depth D on the number of accumulated processing lots when a moving average of five points is taken. For comparison, the actual data shown in FIG. Also shown.
[0030]
The simulation in this case, first,
(1) From the moving average of the etching rates R _{n−5 to} R _n−1 of the immediately preceding five lots, the deemed etching rate R _n of the n-th lot is obtained by the above equation (1).
[0031]
(2) Next, the etching T _n is _calculated from the determined assumed etching rate R _n and the target trench depth D _target ,
T _n = D _target / R _n
Asking.
[0032]
(3) Next, from the etching time T _actual (= 82 seconds) and the obtained trench depth D _actual in the n-th lot in the conventional actual measurement value, the actual etching rate R _actual is _calculated as follows:
R _actual = D _actual / T _actual = D _actual / 82 seconds.
[0033]
(4) Next, by using the obtained R _actual and the previously obtained T _n , the expected trench depth D _n of the n-th lot is _{calculated as} follows:
D _n = T _n × R _actual
Asking.
[0034]
This way, a plot of predicted trench depth D _n found by is the simulation results of FIG. 5, as is apparent from the figure, no longer downward trend of the trench depth and trench depth between lots It can be seen that the variation in the number is also reduced.
[0035]
As described above, in the first embodiment of the present invention, when performing the etching process on the n-th lot, the moving average in the etching of the three or more lots immediately after the processing is obtained, and the n-th lot is etched. Since the etching time is determined, the dependence on the cumulative processing can be eliminated, and the variation between lots can be reduced.
[0036]
Further, in the first embodiment of the present invention, there is no need for a preceding etching member, there is no need to consider an optimal combination of an etching apparatus and a processing lot, and the trench depth is not required. Since no measurement other than the measurement is required, the process is simplified, and the throughput is improved.
[0037]
Next, an etching method according to the second embodiment of the present invention relating to setting of etching conditions for each wafer will be described with reference to FIG.
FIG. 6 is a conceptual configuration diagram of an etching method according to the second embodiment of the present invention. The etching method includes a measuring device 10, an etching device 20, a vacuum transfer mechanism 30, and a control device 40. A basic etching system is configured.
[0038]
The measuring device 10 in this case is, for example, a surface SEM (scanning electron microscope) observing device, the etching device 20 is, for example, a plasma etching device, and the vacuum transfer mechanism 30 is, for example, It is a vacuum transfer chamber provided with a gate valve connecting the load lock and the measuring device.
[0039]
For example, in the etching process of the fine polysilicon wiring, processing is performed in the order of forming a resist pattern → measuring a resist pattern → etching processing → measuring an etching pattern.
The control of each step during this time is performed by the control device 40.
[0040]
Therefore, in this case, the substrate on which the resist pattern for etching the fine polysilicon wiring is formed is measured for the shape of the resist pattern by a surface SEM observation device, and then is loaded into a plasma etching device via a vacuum transfer chamber. Etching is performed in a plasma etching apparatus, and then the substrate after the etching processing is carried into a surface SEM observation apparatus via a vacuum transfer chamber, and a pattern of fine polysilicon wiring formed by etching is measured.
Conventionally, the wafer after the etching process is once taken out into the atmosphere and transported to a measuring device.
[0041]
Next, the measurement result of the shape of the resist pattern is compared with the measurement result of the pattern of the fine polysilicon wiring after etching, and the etching condition of the next wafer is determined so as to obtain a predetermined fine polysilicon wiring pattern. And repeat the same cycle.
[0042]
For example, in the etching process of the fine polysilicon wiring, between the line width W and the fine adjustment etching time ΔT, W ₀ is a line width without the fine adjustment etching time, and a (> 0) is a proportional coefficient. If
W = W ₀ −aΔT
There is a relationship.
[0043]
Therefore, after the etching of a certain wafer is completed, the line width W is measured by the surface SEM observation device, and the difference ΔW from the desired line width W _target (= W _target −W) is obtained.
ΔW = aΔT, that is, ΔT = ΔW / a
A fine adjustment etching time ΔT is obtained, and when the next wafer is ΔW> 0, an extra etching is performed by the fine adjustment etching time ΔT.
When ΔW <0, the etching is performed for a short time by the fine adjustment etching time ΔT.
[0044]
If the line width of the resist pattern on the wafer to be etched is different from the line width of the resist pattern on the most recently processed wafer, it is necessary to determine the fine adjustment etching time ΔT in consideration of this variation.
[0045]
In the second embodiment of the present invention, when measuring the most recently processed wafer, the measurement apparatus 10 and the etching apparatus 20 are connected by the vacuum transfer mechanism 30. There is no need to evacuate the load lock of the etching device 20 and evacuate the measuring device 10 when removing and transporting the same to the measuring device 10, and there is no need to wait for the etching device 20 to start processing the next wafer. Therefore, the throughput can be improved.
[0046]
The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible.
For example, in the above-described first embodiment, the description has been given as the trench forming step, but the present invention is not limited to the trench forming step.
[0047]
That is, in the dry etching process, etching residues and reaction products may adhere to the inner wall of the chamber, and the etching rate tends to decrease as the number of processing lots increases. This is applied to each etching step that affects the etching result.
[0048]
In the first embodiment, the processing unit is a lot. However, the present invention is not limited to the lot, and a wafer may be used as a processing unit. In this case, the last three or more wafers may be used. What is necessary is just to determine the etching time using the moving average of the etching rate of the wafer as the assumed etching rate of the processing wafer.
[0049]
Further, in the above-described second embodiment, the etching processing conditions for the next wafer are determined based on the processing result of the immediately preceding sheet. However, similar to the above-described first embodiment, the latest wafer etching processing conditions are used. The etching conditions may be determined by a moving average of the processing results of three or more wafers.
[0050]
In this case, the processing result to be referred to is not limited to the latest processing result. Immediately after the cleaning of the etching apparatus, the processing result immediately after the cleaning processing of the previous etching apparatus is determined in addition to the moving average as needed, and the etching conditions are determined. Is also good.
[0051]
Further, in the above-described second embodiment, processing is performed in a cycle of measurement of a resist pattern → etching processing → measurement of an etching pattern. However, measurement of a resist pattern may be collectively performed in advance. It is.
[0052]
In this case, since a continuous treatment of etching processing → measurement of etching pattern → next wafer etching processing can be performed without waiting time, the difference ΔW between the predetermined line width and the completed line width is further reduced. Becomes possible.
[0053]
Further, in each of the above embodiments, the processing condition to be determined is the etching time. However, the processing time is not limited to the etching time. It may be slightly changed.
[0054]
Further, in each of the above-described embodiments, the description is given as a process of forming a trench in a silicon substrate or a process of patterning a polysilicon wiring provided on a silicon substrate. However, the substrate is not limited to silicon, and may be GaAs or the like. The present invention is also applicable to the compound semiconductor substrate of (1).
[0055]
Here, the detailed features of the present invention will be described with reference to FIG. 1 again.
Again referring to FIG. 1 (Supplementary Note 1) A method of manufacturing a semiconductor device, comprising: determining an etching condition of a next processing unit based on an etching result of a processing unit already etched under predetermined conditions.
(Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the moving average value of the latest etching results of three or more processing units is regarded as the etching result of the next processing unit, and the etching condition of the next processing unit is determined. Manufacturing method.
(Supplementary Note 3) The method of manufacturing a semiconductor device according to Supplementary Note 2, wherein the etching result is an etching depth, and an etching time is determined as an etching condition of the next processing unit.
(Supplementary Note 4) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the processing unit is one of a lot and a wafer.
(Supplementary Note 5) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the etching process is a trench forming process.
(Supplementary Note 6) The processing unit is a wafer, a vacuum transfer is performed between a pattern shape measuring device and an etching device, and etching conditions are determined for each wafer based on a pattern shape measurement result for each wafer. 4. The method for manufacturing a semiconductor device according to claim 1, wherein
[0056]
【The invention's effect】
According to the present invention, since the conditions of the next etching process are determined by reflecting the latest etching result, a predetermined trench can be formed without depending on the accumulated number of processes after the cleaning of the processing apparatus or the state of the processing apparatus. Setting targets such as depth and line width can be achieved with high accuracy, which greatly contributes to improvement in reliability and cost reduction of a semiconductor device.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of the dependence of a trench depth D on the number of accumulated processing lots.
FIG. 3 is an explanatory diagram of an etching time dependency of a trench depth D.
FIG. 4 is an explanatory diagram of the dependence of the trench depth D on the number of cumulative processing lots when a moving average value is used.
FIG. 5 is an explanatory diagram of a simulation result of the dependence of the trench depth D on the cumulative number of processed lots when a moving average of five points is obtained.
FIG. 6 is a conceptual configuration diagram of an etching method according to a second embodiment of the present invention.
FIG. 7 is an explanatory diagram of the dependence of the actual trench depth on the number of accumulated processing lots when the etching time is set to 82 seconds.
[Explanation of symbols]
Reference Signs List 10 measuring device 20 etching device 30 vacuum transfer means 40 control device

Claims (5)

A method for manufacturing a semiconductor device, comprising: determining an etching condition for a next processing unit based on an etching result of a processing unit already etched under a predetermined condition. 2. The method according to claim 1, wherein a moving average value of etching results of three or more latest processing units is regarded as an etching result of the next processing unit, and an etching condition of the next processing unit is determined. . 3. The method according to claim 2, wherein the etching result is an etching depth, and an etching time is determined as an etching condition for the next processing unit. 4. The method according to claim 1, wherein the processing unit is one of a lot and a wafer. The processing unit is a wafer, and vacuum transfer is performed between a pattern shape measuring device and an etching device, and an etching condition is determined for each wafer based on a measurement result of a pattern shape for each wafer. 2. The method for manufacturing a semiconductor device according to claim 1.

Images