JP2004342718A - Semiconductor device and converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for which a bidirectional current switching can be performed with a high withstand voltage, and to provide a converter using the device. <P>SOLUTION: The semiconductor device to be provided is provided with a first-conductivity first semiconductor layer (12), a second-conductivity second semiconductor layer (16) provided on the first semiconductor layer (12), and first-conductivity first and second semiconductor regions (18) selectively provided on the surface of the second semiconductor layer (16). The device is also provided with first main electrodes (28A) connected to the first semiconductor region (18), second main electrodes (28B) connected to the second semiconductor region (18), and a first gate insulating film (24) provided on the second semiconductor layer (16) adjacently to the first semiconductor region (18). In addition, the device is also provided with a first gate electrode (26A) provided on the gate insulating film (24). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a converter, and more particularly, to a semiconductor device as a switching element having bidirectional current characteristics and high withstand voltage, and a converter using the same.
[0002]
[Prior art]
Power (power) semiconductor devices capable of switching relatively high power include various types of power supply devices such as AC motor drive circuits and uninterruptible power supply devices, and various types of devices such as high-frequency oscillation output devices and broadband power amplifier devices. Used for applications. A typical example of such a power semiconductor device is an IGBT (Insulated Gate Bipolar Transistor).
[0003]
FIG. 29 is a cross-sectional view schematically illustrating the structure of the IGBT. FIG. 30 shows the circuit symbol.
[0004]
To outline this structure, p ⁺ Type emitter layer 102 and n ⁻ A p-type base region 106 is formed in a planar shape on the surface of the semiconductor substrate on which the mold base layer 104 is laminated, and an n-type source region 108 is formed therein in a planar shape. The emitter electrode E is connected to the source region 108.
[0005]
Further, a gate insulating film 110 is provided so as to straddle these planar regions, and a gate voltage can be applied by the gate electrode G. On the other hand, on the back side of the substrate, the collector electrode C is connected to the emitter layer 102.
[0006]
The operation will be described. When a voltage is applied between the gate and the emitter (positive bias), the FET is turned on and the base current of the pnp transistor is supplied, so that the IGBT is turned on and the current I flows. On the other hand, when the gate-emitter voltage is set to a zero-bias or negative-bias state, the IGBT is turned off and the current I is cut off.
[0007]
The IGBT described above is a semiconductor device having both high input impedance characteristics of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and low saturation voltage characteristics of a bipolar transistor.
[0008]
[Problems to be solved by the invention]
However, in such an IGBT, since the direction of the current that can be switched is limited to a single direction, there is room for improvement in that the circuit configuration becomes complicated and the number of mounted elements increases depending on the application. For example, if an AC motor driving converter is configured using IGBTs, there is room for further improvement in terms of circuit size, power loss, and the like.
[0009]
First, a drive circuit for an AC motor using a DC power supply will be described.
[0010]
FIG. 31 is a schematic diagram illustrating a main part of a drive circuit of an AC motor using an IGBT. That is, the input capacitor C1 is connected in parallel to the DC power supplies + V and -V. Then, three sets of switching elements are connected to the power supply + V side, and three sets of switching elements are connected to the power supply -V side. Each switching element is configured by connecting an IGBT (BT1) and a diode D1 in parallel. Then, power is supplied to the three-phase motor M from the connection node between the three pairs of switching elements.
[0011]
In such a configuration, the three-phase motor M can be driven by adjusting the switching timing of each of the six switching elements.
[0012]
On the other hand, there is a demand for driving a three-phase regenerative motor using an AC power supply.
[0013]
FIG. 32 is a schematic diagram illustrating a converter for driving a regenerative motor using an AC power supply. In this figure, the same elements as those described above with reference to FIG. 31 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0014]
In the case of this converter, the three-phase AC power supply AC is once subjected to DC conversion by the first switching element group SE1. Then, this DC voltage is converted into AC again by the second switching element group SE2, and drives each phase line of the regenerative motor M. Also, the regenerative electric power from the motor M is recovered to the power supply side through the same process in the reverse direction.
[0015]
However, this AC converter has the following improvements.
[0016]
First, there is a problem that power loss is large. That is, power is always transmitted between the AC power supply AC and each phase line of the motor M via the two IGBTs (BT1). Here, in the case of a normal IGBT, a voltage of about 0.6 volt to 0.8 volt is required because a current flows through a pn junction formed inside the element in an on state. Therefore, the voltage loss through two IGBTs is between 1.2 volts and 1.6 volts, which lowers the transfer conversion efficiency.
[0017]
Second, there is a problem that the circuit configuration of the converter is complicated and large, and the number of mounted elements is large. That is, a total of 12 IGBTs (BT1) and diodes (D1) are required when the first and second switching element groups are combined. Therefore, the size of the converter increases and the cost increases.
[0018]
In addition, the input capacitor C1 often requires a large-sized capacitor such as a so-called chemical capacitor in terms of capacity, and there is room for further improvement in terms of size, cost, reliability, and the like.
[0019]
The various problems described above are due to the fact that the current switching characteristics of the IGBT are unidirectional. That is, if there is a bidirectional power switching semiconductor device, a compact and high-speed converter can be realized.
[0020]
The present invention has been made based on the recognition of such a problem, and an object of the present invention is to provide a semiconductor device capable of bidirectional current switching having a high withstand voltage and capable of performing current switching, and a converter using the same.
[0021]
[Means for Solving the Problems]
To achieve the above object, according to a first aspect of the present invention, a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer are provided. A first semiconductor region of the first conductivity type and a second semiconductor region of the first conductivity type provided apart from each other on the surface of the second semiconductor layer; A third semiconductor region of a second conductivity type selectively provided on a surface of the region, a first main electrode connected to the first semiconductor region and the third semiconductor region, A second main electrode connected to a semiconductor region, a first gate insulating film provided on a part of the first semiconductor region and the second semiconductor layer adjacent thereto, and the gate insulating film A first gate electrode provided on the semiconductor device, wherein the first gate insulation When no inversion layer is formed on the surface of the first semiconductor region under the first gate electrode, substantially no current flows between the first and second main electrodes, and In a state in which a voltage is applied to the first gate electrode so that an inversion layer is formed on the surface of the first semiconductor region, the second main electrode moves from the second main electrode toward the first main electrode. A semiconductor device is provided in which a current can substantially flow.
[0022]
According to a second aspect of the present invention, there is provided a converter for connecting an AC power supply having a plurality of phases and an AC motor having a plurality of input terminals, wherein each of the plurality of phases is connected to the plurality of phases. The semiconductor device according to the first aspect is connected in a matrix between each of the input terminals and is capable of performing a switching operation.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0024]
FIG. 1 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to an embodiment of the present invention. That is, an n-type semiconductor layer (n-type buffer layer) 14 and an n-type base layer 16 are laminated on a p-type semiconductor layer (p-type emitter layer) 12 in this order. A plurality of p-type base regions 18 are formed in a planar shape. In the p-type base region 18, an n-type source region 20 is also formed in a planar shape.
[0025]
A gate insulating film 24 is provided so as to straddle adjacent base regions 18, and a gate voltage can be applied by gate electrodes 26A and 26B provided thereon. Further, emitter (collector) electrodes 28A and 28B are connected to the n-type source region 20. Further, a p-type guard ring 22 is formed between these emitter (collector) regions.
[0026]
A typical carrier concentration of each part is, for example, 10 p-type semiconductor layers. ¹⁸ -10 ¹⁹ cm ^-3 , The n-type semiconductor layer 14 ¹⁸ -10 ¹⁹ cm ^-3 , N-type base layer 16 is 4 × 10 ^Thirteen ~ 3 × 10 ¹⁴ cm ^-3 , P-type base region 18 is 1 × 10 ¹⁷ cm ^-3 , N-type source region 20 ¹⁹ -10 ²⁰ cm ^-3 Degree.
[0027]
In the semiconductor device of this specific example described above, a current is caused to flow in any direction between the emitter (collector) electrodes 28A and 28B by appropriately applying a bias to one of the gate electrodes 26A and 26B. Can be. That is, bidirectional switching in which both of the electrodes 28A and 28B function as both an emitter electrode and a collector electrode is possible.
[0028]
Hereinafter, the operation of the semiconductor device of the present invention will be described.
[0029]
2 and 3 are schematic diagrams illustrating the operation of the semiconductor device of the present invention.
[0030]
In the semiconductor device of this embodiment, as shown in these drawings, three or more emitter (collector) regions are arranged on the surface of the n-type base layer 16, and the gate electrodes 26A and 26B are alternately arranged in these adjacent regions. A wired structure can be adopted. At the end of the semiconductor device, an n-type field stopper 40 may be provided as shown in the figure to prevent the depletion region D from reaching the chip end.
[0031]
The operation will be described first. FIG. 2A shows a blocking (off) state in which a positive voltage is applied to the main electrode 28B. At this time, 0 (zero) volts or a negative bias (referred to as “off bias”) is applied to the gate 26A with respect to the main electrode 28A. The gate 26B may be applied with an off-bias (with respect to the main electrode 26B) or a positive bias (referred to as “on-bias”).
[0032]
At this time, the depletion layer D extends from the p-type base region 18 on the side of the main electrode 28A as shown. In order to alleviate the electric field at the end of the p-type base region, it is necessary to extend the depletion layer in the lateral direction. For this purpose, the guard ring 22 is arranged in a region between the p-type base regions 18 on both main electrode sides.
[0033]
As will be described later using a specific example, a “RESURF (Reduced SURface Field) structure” or a “field plate structure” may be provided instead of the guard ring 22, or an insulator 1 may be embedded. One or a plurality of trench grooves (provided that they have a depth not to completely cut the buried n-layer and have a depth of half or more of the N base layer) may be provided. In the case of a trench, it is not necessary to provide a large area such as a guard ring in order to secure a withstand voltage by an insulator inside the trench.
[0034]
To turn on the device from the state shown in FIG. 2A, an on-bias is applied to the gate 26A. Then, as shown in FIG. 2B or FIG. 1, electrons are formed on the surface of the p-type base region 18 by the bias voltage of the channel (gate bias) in the MOS structure (18, 20, 16, 24, 26). Is injected into the n-type base layer 16 through the channel, and passes through the buried n-type layer 14 (partially through the n-type base layer 16). ), And reaches the p-type base region 18 on the main electrode 28B side.
[0035]
Due to this electron current, the junction between the p-type base region 18 on the main electrode 28B side and the n-type base layer 16 is positively biased, and holes (holes) are injected from the p-type base region 18 connected to the main electrode 26B. The holes flow through the p-type semiconductor layer 12 (partially through the plasma in the n-type base layer 16) to the p-type base region 18 on the main electrode 28A side while forming a plasma state with electrons.
[0036]
As a result, conductivity modulation similar to the operation state of the IGBT occurs, and the conduction resistance decreases. The buried n-type layer 14 preferably has a structure in which “holes” and “slits” are provided in the vicinity of the p-type base region 18 and the gate 26B in order to create a path through which holes flow. . This will be described in detail later with specific examples.
[0037]
Contrary to FIG. 2, when a positive voltage is applied to the main electrode 28A, the depletion layer D expands as shown in FIG. 3A, and the operation is the reverse of that described with reference to FIG. . That is, FIG. 3A shows a blocking (off) state in which the depletion layer D is expanded, and FIG. 3B shows an on state. As compared with the state described in FIG. 2, the emitter and the collector operate in reverse.
[0038]
As described above, this element can perform an ON / OFF switching operation regardless of which of the main electrodes 28A and 28B receives a positive voltage. That is, the device of the present embodiment operates as a so-called “AC switch”, and furthermore, since two main electrodes and two gate electrodes are exposed on the chip surface, the mounting method widely used conventionally can be used as it is. It also has advantages.
[0039]
Further, in this element structure, the spread of the depletion layer is stopped by the n-type buffer layer 14, so that at the time of turn-off, it is not necessary to discharge the accumulated carriers extra due to the spread of the depletion layer, and a high-speed turn-off can be provided.
[0040]
Further, since the amount of holes injected from the p-type base region 18 can be controlled by applying a voltage to the gate electrode (26B), the characteristics in the operating state, such as increasing the switching speed or reducing the on-voltage, can be obtained. There is also an advantage that the control can be performed dynamically.
[0041]
More specifically, a voltage applied to the gate electrode (26B) is applied to the bias (positive gate bias) for forming the n-channel at or immediately before the turn-off (1 to 10 microseconds), thereby turning off the device. Speed can be increased. Also, if the gate electrode is biased (0 or negative gate bias) to a voltage that does not allow the channel, the on-voltage decreases. When a negative gate bias is applied at the time of turn-on or immediately before (1 to 10 microseconds), the turn-on is accelerated. Further, when the gate is biased positively at the time of off, the leak current can be reduced. By combining these features and performing dynamic control, the loss generated by the element can be further reduced.
[0042]
Further, the element of the present embodiment also has a diode built therein. That is, when the gate 26A is off-biased and the gate 26B is on-biased, the main electrode 28B functions as an IGBT when the main electrode 28B has a positive voltage. The n-type base is connected to the main electrode 26B, and functions as a pn diode between the n-type base and the p emitter on the 26A side. As a result, when a matrix converter is actually constructed using the device of the present embodiment, unlike the case of an IGBT, there is no need to connect diodes in series. Therefore, the number of elements in the matrix converter can be reduced, and the loss can be reduced. As a result, as described later in detail, it is possible to provide a compact and highly reliable semiconductor device for power control in various power control applications such as motor control.
[0043]
Returning to FIG. 1 again, as exemplified by the arrows, the p-type semiconductor layer 12 functions as a main path for flowing holes, whereas the n-type semiconductor layer 14 functions as a main path for electrons. Act as a pathway. The n-type base layer 16 cannot increase the carrier concentration so much that the depletion region D from the gate is expanded. Therefore, the carrier concentration is set to 10 ¹⁸ -10 ¹⁹ cm- ³ (Dose 10 for ion implantation ¹⁴ -10 ¹⁶ cm ^-2 (Corresponding to the above) is provided to secure a path through which electrons flow. The n-type semiconductor layer 14 may be formed on the p-type semiconductor layer 12 by epitaxial growth, or may be formed by ion implantation or a diffusion method.
[0044]
That is, in the case of the semiconductor device of the present invention, the on-resistance of the semiconductor device can be reduced by appropriately adjusting the carrier concentration and the layer thickness of the p-type semiconductor layer 12 and the n-type semiconductor layer 14.
[0045]
Further, as described above, when the bias is applied to the gate electrode 26A or 26B to expand the depletion region D, the breakdown of the p-type guard ring 22 is caused by the concentration of the electric field on the surface of the n-type base layer 16. It has the role of suppressing what happens.
[0046]
FIG. 4 is another schematic diagram illustrating the operation of the semiconductor device of the present embodiment. That is, FIG. 1A is a conceptual diagram in which the semiconductor device of the present invention is divided into two for convenience, and is vertically illustrated. FIG. 2B shows an electric field distribution when a bias is applied to the gate electrode 26A, and FIG. 2C shows an electric field distribution when a bias is applied to the gate electrode 26B.
[0047]
As shown in FIG. 4B, when a positive voltage is applied to the main electrode 28B in the off state, the junction between the p-type base region 18 on the main electrode 28A side and the n-type base layer 16 in contact therewith depletes the depletion region. D extends into the semiconductor layer. Then, the voltage applied by the depletion region D is held.
[0048]
On the other hand, when a positive voltage is applied to the main electrode 28A, the depletion layer spreads from the junction between the p-type base region 18 and the n-type base layer 16 on the opposite side as shown in FIG.
[0049]
FIG. 4A shows the flow of holes and electrons at this time with respect to the current flowing from the main electrode 28B to the other main electrode 28A when an on-bias is applied to the gate 26A, respectively. . The holes flowing out of the lower p-type base region 18 flow into the n-type base layer 16 of the upper device via the p-type emitters 12 of the upper and lower devices. In addition, the electrons flowing out of the MOS channel of the upper device flow into the p-type base region 18 via the n-type buffer 14.
[0050]
As described above, in the element according to the present embodiment, the flow of electrons and the flow of holes are electrically independent from each other in the portion connected in series, while being configured to be connected in series. In other words, the connection is such that the pseudo Fermi potentials of holes and electrons can take different potentials, and the p-type layer (in this case, the p-type emitter 12) and the n-type layer (in this case, the n-type buffer) Layer 14) is not connected to the same electrode. Since holes and electrons flow with different potentials, the built-in potential between these main electrodes 28A and 28B is generated only for a single pn junction. For this reason, there is no increase in the voltage drop due to the built-in potential even though it appears to be connected in series. In particular, since the paths where holes and electrons flow are separated at the connection portion, the concentrations of the p-type emitter layer 12 and the n-type buffer layer 14 are increased, so that the voltage drop can be further suppressed.
As described above, in the case of the semiconductor device of the present invention, a current can flow in any direction between the electrodes 28A and 28B by selectively applying a bias to one of the gate electrodes 26A and 26B. Is possible. Moreover, the on-states in these two directions can be made completely equivalent.
[0051]
Furthermore, in a state where a bias is applied to one of the gate electrodes 26A and 26B and a current flows in a predetermined direction, the withstand voltage in the reverse direction can be increased.
[0052]
At the same time, the breakdown voltage in the off state where no bias is applied to both of the gate electrodes 26A and 26B can be maintained high.
[0053]
Next, a modified example of the semiconductor device of the present invention will be described.
[0054]
FIG. 5 is a schematic diagram illustrating a first modification of the semiconductor device of the present invention. In this figure, the same elements as those described above with reference to FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0055]
In the case of this modification, the n-type semiconductor layer 14 is selectively provided only between adjacent emitter (collector) regions. In this case, as indicated by the arrow in the drawing, the holes can easily flow, and the effect of reducing the on-resistance can be obtained.
[0056]
Further, in this case, in order to ensure the ease of electron flow, the n-type semiconductor layer 14 is provided partially or selectively (for example, in a stripe shape or a pattern having holes) as shown by a broken line. Is also good.
[0057]
FIG. 6 is a schematic diagram illustrating the operation of the semiconductor device of the present modification. That is, FIG. 7A shows a state where an on-bias is applied to the gate electrode 26A, and FIG. 7B shows a state where an on-bias is applied to the gate electrode 26B. On the other hand, as shown in FIG. 6, when the n-type semiconductor layer 14 on the path is eliminated, the pn junction in the reverse direction is eliminated, so that the effect of reducing the on-resistance can be obtained.
[0058]
FIG. 7 is another schematic diagram illustrating the operation and effect of this modification. That is, FIGS. 7A and 7B both show a state in which a bias is applied to the gate electrode 26A. When the n-type semiconductor layer 14 is provided continuously, a pn junction in the reverse direction is formed in the path through which holes flow, so that the on-resistance increases accordingly. In addition, the current-voltage characteristics have a snapback characteristic, and the current may be non-uniform.
[0059]
On the other hand, as shown in FIG. 7B, when the opening OP is provided in the n-type semiconductor layer 14, the opening OP becomes a hole path through which holes flow, and the on-resistance can be reduced. . As a method of forming the n-type semiconductor layer 14 that is not continuous in this way, for example, a method of patterning the n-type semiconductor layer 14 after epitaxially growing it, a method of selectively burying and growing the n-type semiconductor layer 14, or A method of selectively introducing a p-type impurity into the n-type semiconductor layer 14 by ion implantation, diffusion, or the like can be given.
[0060]
FIG. 8 is a schematic diagram illustrating a second modification of the semiconductor device of the present invention. This modification also has a structure suitable for lowering the on-resistance.
[0061]
That is, in the case of this modified example, a plurality of openings OP are provided in the n-type semiconductor layer 14 below the emitter (collector) region. These openings OP function as hole paths and play a role of reducing the on-resistance of the hole current.
[0062]
On the other hand, electrons flow through the low-concentration n-type base layer 16 at these openings OP, but since these portions are also n-type, the increase in the on-resistance of the electron current is relatively low.
[0063]
In other words, by appropriately adjusting the size and the number of the openings OP provided in the n-type semiconductor layer 14, the advantage that the hole current decreases rather than the loss that the on-resistance of the electron current increases can be relatively increased. it can.
[0064]
FIG. 9 is a schematic view illustrating a third modification of the semiconductor device of the present invention. This modification also has a structure suitable for lowering the on-resistance.
[0065]
That is, in the case of this modification, a low concentration region 14A in which the impurity concentration of the n-type semiconductor layer 14 is reduced is provided below the emitter (collector) region. The impurity concentration of the low-concentration region 14A is a concentration between the high-concentration n-type semiconductor layer 14 and the low-concentration n-type base layer 16.
[0066]
For example, the impurity concentration of the low concentration region 14A is sufficient if the dose is in the order of 10 12 to 10 13. This is because, in order to prevent the electric field from reaching the p-type emitter, the region of the low-concentration portion can be made wider, and it becomes easier to flow holes.
[0067]
By providing the low-concentration region 14A below the emitter (collector) region, holes easily flow into the p-type semiconductor layer 12. That is, the low concentration region 14A functions as a hole path.
[0068]
Therefore, in a case where it is desired to reduce the overall on-resistance while preventing the loss of the electron current in accordance with the design parameters and required characteristics of the semiconductor device, this modification may be adopted.
[0069]
FIG. 10 is a schematic diagram illustrating a fourth modification of the semiconductor device of the present invention. This modification also has a structure suitable for lowering the on-resistance.
[0070]
That is, FIG. 1A is a cross-sectional view of a main part thereof, and FIGS. 2B and 2C are partially enlarged views of a cross section taken along line AA of FIG. 1A.
[0071]
In the present modification, a p / n buried layer 44 is provided between the p-type semiconductor layer 12 and the n-type base layer 16. FIGS. 10B and 10C are schematic diagrams showing two specific examples of the cross-sectional structure of the p / n buried layer 44. FIG.
[0072]
In the case of the structure shown in FIG. ⁺ Mold buried region 44A and p ⁺ The mold embedding regions 44B are provided alternately. Each of these buried regions 44A and 44B extends in a stripe shape below the adjacent emitter (collector) region. The carrier concentration is, for example, 10 ¹⁸ -10 ¹⁹ cm ^-3 Degree.
[0073]
In the case of the structure shown in FIG. ⁺ The holes flow through the mold buried region 44A, and the holes mainly flow through the p + buried region 44B. Further, some of the holes may leak from the buried region 44B and flow through the p-type semiconductor layer 12 therebelow.
[0074]
Thus, the stripe-shaped n ⁺ Type and p ⁺ By providing the mold buried regions 44A and 44B, both the electron current and the hole current can flow with low loss, and the on-resistance of the semiconductor device can be effectively reduced.
[0075]
On the other hand, in the case of the structure shown in FIG. 10C, an n-type semiconductor region 44C is provided below the buried regions 44A and 44B. In this case, a sufficient electron path can be secured, and avalanche breakdown does not occur even when a voltage is applied between the p-type layer and the n-type layer (44A, 44B) during operation. This is because the depletion layer spreads at 44C. When a gap is slightly provided between the n-type layer and the p-type layer (that is, to a thickness of 44C or less), the depletion layer between the p-type layer and the n-type layer is easily stretched, and is more resistant to breakdown. .
[0076]
As above, as the first to fourth modified examples of the present invention, the structure effective for reducing the on-resistance of the semiconductor device has been described.
[0077]
Next, a structure suitable for controlling the expansion of the depletion region D will be described.
[0078]
FIG. 11 is a schematic sectional view showing a fifth modification of the semiconductor device of the present invention. Also in this figure, the same elements as those described above with reference to FIGS. 1 to 10 are denoted by the same reference numerals, and detailed description will be omitted.
[0079]
In the case of the structure described above with reference to FIG. 1, a p-type guard ring 22 is provided between adjacent emitter (collector) regions to suppress breakdown on the surface of the n-type base layer 16.
[0080]
However, in this case, there is a concern that the depletion layer may spread too much to reach the p-type base region 18 on the opposite side and be destroyed. In particular, when the concentration of the n-type base layer 16 is low, it is necessary to widely open the respective p-type base regions 18 that are in contact with the first and second main electrodes. However, by increasing the interval, the chip area increases, and the current path becomes longer, which is disadvantageous in terms of cost and current conduction loss.
[0081]
On the other hand, in the case of this modification shown in FIG. ⁺ By providing the mold field stopper 40, the expansion of the depletion region D can be controlled more reliably.
[0082]
In other words, when the bias is applied to the gate electrode 26A, if the depletion region D extends below the adjacent gate electrode 26B, a sufficient electric field difference cannot be secured between the adjacent emitter region and the collector region. .
[0083]
On the other hand, in this modified example, n ⁺ By providing the mold field stopper 40, the expansion of the depletion region D is reliably prevented, and the electric field distribution can be properly maintained.
[0084]
In the case of this modified example, n ⁺ If a floating electrode (not shown) is connected to the mold field stopper 40, the expansion of the depletion region D can be more reliably prevented. In this way, the area where the guard ring 22 is formed can be reduced.
[0085]
FIG. 12 is a schematic sectional view showing a sixth modification of the semiconductor device of the present invention. This modified example also has a structure suitable for suppressing the expansion of the depletion region D.
[0086]
In the case of this modification, a groove G having a V-shaped (or U-shaped) cross section is formed between adjacent emitter (collector) regions, and is buried with an insulator 50. The groove G penetrates through the p-type base layer 16 to reach the n-type semiconductor layer 14 and is formed at the opening end over the p-type base region 18. It may be covered by. In this way, it is possible to reliably prevent the depletion region D from spreading while suppressing a problem such as a decrease in withstand voltage due to a current leak on the inner wall surface of the groove G. However, if the oxide film interface is good, the p-type region 52 is not necessarily required.
[0087]
The groove G in this modified example can be formed by either wet etching or dry etching. For example, a groove whose cross section is almost U-shaped may be formed by RIE (Reactive Ion Etching).
[0088]
Further, as a material of the insulating film 50 filling the groove G, for example, an oxide such as silicon oxide, a nitride, or the like can be used.
[0089]
FIG. 13 is a schematic sectional view showing a seventh modification of the semiconductor device of the present invention. This modified example also has a structure suitable for suppressing the expansion of the depletion region D.
[0090]
That is, in the case of this modified example, a trench T having a substantially vertical cross section reaching the n-type semiconductor layer 14 is formed between the adjacent emitter (collector) regions, and the inside thereof is filled with the insulator 50.
[0091]
Even in this case, the expansion of the depletion region D can be reliably prevented. Further, if p-type or n-type impurities are introduced into the side wall surface of trench T, current leakage on the side wall surface can be reduced.
[0092]
Note that the left and right p-type base regions 18 may be close to each other with the trench interposed therebetween, and the extension of the p-type base region may be in contact with the insulating film 50. In this way, the chip size can be reduced, and the current path can be shortened to reduce conduction loss.
[0093]
Also in this modified example, as a material of the insulating film 50 filling the trench T, for example, an oxide such as silicon oxide, a nitride, or the like can be used.
[0094]
FIG. 14 is a schematic diagram illustrating an eighth modification of the semiconductor device of the present invention. This modification also has a structure suitable for controlling the expansion of the depletion region D.
[0095]
That is, in the case of this modification, a p-type RESURF (RESDURF: REDURED SURFACE FIELD) region 46 is provided between adjacent emitter (collector) regions so as to extend from these p-type base regions 18. N between the resurf regions 46 ⁺ A mold field stopper 40 is provided.
[0096]
Like the p-type guard ring 22, the p-type RESURF region 46 has a role of suppressing breakdown near the surface when the depletion region D extends in the p-type base layer 16. It is desirable that the concentration of the p-type resurf region 46 be lower than that of the p-type base region 18.
[0097]
Also, n ⁺ The mold field stopper 40 has a role of more reliably preventing the expansion of the depletion region D as described above with reference to FIG. Also in this modified example, n ⁺ The mold field stopper 40 may be provided with a floating electrode (not shown).
[0098]
Further, by adding a field plate 26C to the electrodes 26A and 26B in the emitter (collector) region, a termination structure can be formed, and the breakdown voltage can be maintained.
[0099]
FIG. 15 is a schematic sectional view illustrating a ninth modification of the semiconductor device of the present invention. This modified example is a preferred specific example regarding the connection relationship of the electrodes.
[0100]
That is, in the semiconductor device of the present invention, when the p-type semiconductor layer 12 and the electrode 32 provided on the back surface thereof are in a floating state, malfunction may occur due to charge-up or the like. Therefore, in the case of this modified example, the electrode 32 on the back surface and the electrodes 28A and 28B are connected by the diode 60. The diode 60 has a role of suppressing current leakage to an external connection circuit.
[0101]
Therefore, it is preferable to use a diode in which a plurality of diodes 60A, 60B, 60C,... Are connected in series, because the leakage current to the connection circuit is reduced.
[0102]
FIG. 16 is a schematic sectional view showing a tenth modification of the semiconductor device of the present invention. This modification is a specific example in which a terminal electrode is provided separately for an emitter electrode and a collector electrode.
[0103]
That is, in the case of the structure shown in FIG. 16, a p-type base region 18 and an n-type source region 20 are formed at one end of the n-type base layer 16 in a planar shape, and a gate is provided so as to straddle these. The electrode 26A is connected. The emitter electrode 28A is connected to the n-type source region 20.
[0104]
On the other hand, a p-type emitter region 62 is formed at the other end of the n-type base layer 16, and the collector electrode 28B is connected to this.
[0105]
In this structure, when a positive bias is applied to the collector electrode 28B, the depletion region D expands on the emitter side. When a gate voltage is applied to the gate electrode 26A in this state, electrons flow from the emitter electrode 28A toward the collector electrode 28B inside the semiconductor device, as shown by the arrows, and holes flow in the opposite direction. Flows. That is, this structure functions as a unidirectional switching element.
[0106]
Also, in the case of this semiconductor device, as in the case described above with reference to FIG. 1, in the blocking (off) state, even if a voltage is applied in a direction in which either the emitter electrode or the collector electrode is positive, a high breakdown voltage is applied. Can be obtained. That is, a high breakdown voltage can be obtained in both directions.
[0107]
When switching currents in both forward and reverse directions, this semiconductor device may be connected in parallel in the reverse direction.
[0108]
FIG. 17 is a schematic diagram showing a semiconductor device having a structure in which the semiconductor devices of this modification are connected in parallel in opposite directions. That is, in the figure, the elements 10A and 10B each have the structure shown in FIG. These elements 10A and 10B may be formed as separate elements and connected by wiring, or may be formed monolithically as the same semiconductor chip.
[0109]
FIG. 18 is an equivalent circuit diagram of the semiconductor device shown in FIG.
[0110]
That is, in the elements 10A and 10B, the respective emitter electrodes 28A and collector electrodes 28B are connected in opposite directions. When a bias is applied to the gate electrode 26A, the element 10A is turned on and the current Ia flows. When a bias is applied to the gate electrode 26B, the element 10B is turned on and the current Ib flows.
[0111]
In the case of this modification, by providing the emitter electrode and the collector electrode of the semiconductor device separately, it is easy to further increase the current capacity.
[0112]
FIG. 19 is a schematic diagram illustrating an eleventh modification of the present invention. These drawings are explanatory views showing an example of the planar structure of the semiconductor device of the present invention.
[0113]
That is, FIG. 19A is a cross-sectional view of the semiconductor device of the present modification, FIG. 19B is a plan view of the electrode surface, and FIG. 19C is a plan view of the semiconductor portion. Here, FIG. 19A shows a cross section taken along line AA of FIGS. 19B and 19C.
[0114]
First, the structure of the semiconductor surface will be described with reference to FIGS. 19A and 19C. In the emitter (collector) regions at both ends of the n-type base layer 16, a p-type base region 18 is formed on the surface in the left and right directions in the figure. It is formed in a stripe shape in the direction. In the p-type base region 18, an n-type source region 20 is formed in a stripe shape in the left-right direction.
A p-type guard ring 22 is formed vertically between the emitter (collector) regions in the figure, and an n-type field stopper 40 is formed near the center in the vertical direction in the figure.
[0115]
Next, the structure of the electrode will be described with reference to FIGS. 19A and 19B. First, in the emitter (collector) region, gate insulation is performed so as to straddle the p-type base region 18 formed in a stripe shape. A film 24 is formed, on which gate electrodes 26A and 26B made of polysilicon or the like are formed. The gate electrodes 26A and 26B are connected to the gate wiring G and are led out.
[0116]
On the other hand, in the emitter (collector) region, the emitter (collector) electrodes 28A and 28B are connected to the n-type source region 20 via a gap between the gate electrodes 26A and 26B formed in a stripe shape. These electrodes 28A, 28B and the gate electrodes 26A, 26B are insulated by an interlayer insulating film (not shown). In FIG. 19B, a part of the emitter (collector) electrode is omitted.
[0117]
On the other hand, a floating electrode 70 is connected to the field stopper 40 via the polysilicon electrode 25.
[0118]
With the planar configuration described above, it becomes easy to apply a bias from the gate electrodes 26A and 26B to a wide range of the emitter (collector) region to spread the depletion region D evenly. Also, it is easy to secure the connection area of the emitter (collector) electrodes 28A and 28B and reduce the element resistance.
[0119]
FIG. 20 is a schematic diagram illustrating a twelfth modification of the present invention. That is, the present modified example is a specific example of the planar structure of the n-type semiconductor layer 14.
[0120]
20A is a cross-sectional view of the semiconductor device of the present modified example, FIG. 20B is a schematic diagram showing the planar structure of the n-type semiconductor layer 14, and FIG. It is a schematic diagram showing another specific example of the planar structure of FIG.
[0121]
First, the structure shown in FIGS. 20A and 20B will be described. The buried n-type semiconductor layer 14 is formed continuously in a portion between the adjacent emitter (collector) regions, and the emitter ( Below the (collector) region, it is formed in a stripe shape extending in the left-right direction in the figure. That is, the opening OP is formed in the n-type semiconductor layer 14 below the emitter (collector) region. As described above with reference to FIGS. 5 to 7, this opening OP has a role as a hole path for facilitating the flow of holes.
[0122]
Next, the structure shown in FIG. 20C will be described. The buried n-type semiconductor layer 14 is formed in a plurality of stripes extending continuously in the left-right direction in the figure. That is, a plurality of stripes are formed between adjacent emitter (collector) regions. With such a structure, the width of the path through which electrons flow is slightly narrowed, but there is an advantage that the trouble of mask alignment can be omitted in the manufacturing process.
[0123]
That is, as shown in FIG. 20B, when the n-type semiconductor layer 14 is continuously formed between the adjacent emitter (collector) regions, the patterning is performed along the left-right direction in the drawing when patterning the n-type semiconductor layer 14. It is necessary to adjust the mask alignment so that "displacement" does not occur.
[0124]
On the other hand, when the n-type semiconductor layer 14 is formed in a uniform stripe shape as shown in FIG. 20C, such a troublesome work of mask alignment is unnecessary. Therefore, manufacturing becomes easy, and variations in characteristics of the obtained semiconductor device can be eliminated.
[0125]
FIG. 21 is a schematic diagram showing a thirteenth modification of the present invention. That is, FIG. 1 is a conceptual diagram illustrating an example of a planar pattern of a semiconductor device.
[0126]
In the case of this specific example, a substantially rectangular chip is provided with a pair of substantially emitter-collector regions EC and collector (emitter) regions CE combined in a comb shape. A field stopper (not shown) is provided between them, and the floating electrode 70 is connected. Further, the gate electrodes 26A and 26B are led out from the gate pads GP1 and GP2 via an interlayer insulating film, respectively.
[0127]
As described above, when the emitter (collector) regions are combined in a comb shape or nest shape, it is easy to realize a large current capacity with a small size.
[0128]
FIG. 22 is a schematic diagram illustrating a fourteenth modification of the present invention. That is, this figure is also a conceptual diagram illustrating an example of a plane pattern of the semiconductor device.
[0129]
The semiconductor device of this specific example has a pattern shown in FIG. 21 and further has a circuit system for driving a gate electrode integrated therein. That is, the gate electrode 26A (not shown) is driven by the gate drive circuit GD1, and the gate electrode 26B (not shown) is driven by the gate drive circuit GD2.
[0130]
These gate drive circuits GD1 and GD2 are controlled by the logic circuit LG via the level shifters LS1 and LS2. FIG. 22 shows a state in which the level shifters LS1 and LS2 are provided below the floating electrode 70.
[0131]
As described above, by integrating the logic circuit LG, the level shifters LS1 and LS2, and the gate drive circuits GD1 and GD2 on the same chip, it is possible to realize a semiconductor device suitable for AC control, particularly for use in a frequency-variable inverter.
[0132]
The semiconductor device of the present invention has been described above with reference to FIGS.
[0133]
Next, a matrix converter using the semiconductor device of the present invention will be described.
[0134]
FIG. 23 is a conceptual diagram showing a matrix converter according to the present invention. That is, the matrix converter MC has a structure in which the semiconductor devices 10 of the present invention described above with reference to FIGS. 1 to 22 are connected in parallel in a matrix. In the case of this specific example, a total of nine semiconductor devices 10 from (1, 1) to (3, 3) are connected in parallel between the three-phase alternating current AC and the three-phase line of the regenerative motor M. Although each of the semiconductor devices 10 is represented as a simple switch in FIG. 1, they actually have two gates as described above with reference to FIGS. And selectively turn on one of these two gates.
[0135]
These semiconductor devices 10 are switched at predetermined timing by control means (not shown) to supply power from the three-phase AC to the motor M and regenerate power from the motor M to the three-phase AC. it can. Here, in the case of the conventional driving circuit described above with reference to FIGS. 29 to 32, there is a problem that a loss due to a voltage drop is large because two semiconductor devices pass between the AC AC and the motor M.
[0136]
On the other hand, in the case of the matrix converter of the present invention, the switching between the AC AC and the motor M is switched by one semiconductor device, and the loss due to the voltage drop can be reduced. In particular, by employing the first to fourth modified examples of the present invention, the on-resistance of the semiconductor device can be further reduced, so that the power loss can be more effectively reduced.
[0137]
Further, in the case of the matrix converter of the present invention, the number of semiconductor devices is reduced to half and the large-capacity capacitor C is not required as compared with the conventional drive circuit shown in FIG. As a result, a converter that is more compact, lighter and more reliable than before can be realized.
[0138]
FIG. 24 is a block diagram illustrating an example of a main configuration of a gate drive system of the semiconductor device 10 in the matrix converter of the present invention.
[0139]
That is, the gate drive system 200 of this specific example includes a pulse-width modulation (PWM) signal generator 210, a gate pattern consistency check circuit 212, and a gate functional unit provided for each of the semiconductor devices 10. 220. The PWM signal output from the PWM signal generator 210 is supplied to each of the gate function units 220 via the gate pattern consistency check circuit 212.
[0140]
FIG. 25 is a block diagram illustrating the configuration of the gate function unit 220. That is, the gate function unit 220 includes a current direction detection / prediction circuit 221, a gate delay time calculation circuit (gate pattern calculation circuit) 222, a delay circuit (gate pattern generation circuit) 223, and first and second level shifters 224. 226 (corresponding to LS1 and LS2 in FIG. 22), and first and second gate drive circuits 225 and 227.
[0141]
Signals from the terminal electrodes T1 and T2 (corresponding to the emitter / collector electrodes 28A and 28B) of the semiconductor device are input to the current direction detection / prediction circuit 221, and the direction of the current flowing through each of the semiconductor devices is detected. is expected. The delay time calculation circuit 222 calculates the ON delay timing of the gates G1, G2 (corresponding to the gate electrodes 26A, 26B) of the semiconductor device based on the detection / prediction result and the PWM signal.
[0142]
The delay circuit 223 generates a gate driving pattern based on the result of the calculation and the trigger of the PWM signal. This drive pattern is checked at the logic level in the consistency check circuit 212 and supplied to the gate drive circuits 225 and 227 via the level shifters 224 and 226, respectively.
[0143]
Then, each of the gate drive circuits 225 and 227 drives a pair of gates G1 and G2 (corresponding to the gate electrodes 26A and 26B) of the semiconductor device.
[0144]
FIG. 26 is a list showing overvoltage protection means in the matrix converter of the present invention. That is, as means for preventing an overvoltage load on the semiconductor device 10, a voltage sensing means 310 between T1 and T2, that is, a means for detecting a voltage between the terminal electrodes T1 and T2 of the semiconductor device 10, and a main current detecting means 320, Means for detecting the main current flowing through the semiconductor device 10, dV / dt detecting means 330 between T1 and T2, ie means for detecting the rate of change of the voltage between the terminal electrodes T1 and T2 of the semiconductor device 10, main current dI / dt G1 voltage control means 350, that is, means for controlling the voltage applied to the gate G1, G2 voltage control means 360, that is, the voltage applied to the gate G2 Means for controlling the applied voltage.
[0145]
In order to prevent the semiconductor device 10 from being overloaded, one of these protection means 310 to 360 may be used, or a plurality of protection means may be combined.
[0146]
FIGS. 27A to 27C are circuit diagrams illustrating specific examples of the overvoltage protection circuit for the semiconductor device 10. That is, in these specific examples, an overvoltage on the semiconductor device 10 is prevented by appropriately combining the diode D, the Zener diode ZD, the protection resistor R, and the protection transistor TR.
[0147]
FIG. 28 is a perspective view illustrating the appearance of the matrix converter of the present invention.
[0148]
That is, the package PG is provided on the heat sink HS, and the input / output terminals AC1 to AC3 to the three-phase AC, the input / output terminals M1 to M3 to the motor M, and the gate control board GC Is provided.
[0149]
The semiconductor device 10 and the gate drive system 200 thereof described above with reference to FIGS. 24 and 25 are provided on the gate control substrate GC.
[0150]
According to the present invention, a bidirectional converter with high power can be realized in such a very compact manner.
[0151]
The embodiments of the invention have been described with reference to examples. However, the present invention is not limited to these specific examples.
[0152]
For example, the arrangement relationship, dimensions, shape, conductivity type, impurity concentration, material, etc. of each semiconductor layer or each semiconductor region in the semiconductor device of the present invention are appropriately selected from those known by those skilled in the art, and are the same as those of the present invention. Those which can provide the function and effect are also included in the scope of the present invention.
[0153]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a semiconductor device capable of bidirectional high-voltage power switching, and to make a converter or the like using the semiconductor device much more compact and highly reliable than before. The industrial benefits are enormous.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating an operation of the semiconductor device of the present invention.
FIG. 3 is a schematic diagram illustrating an operation of the semiconductor device of the present invention.
FIG. 4 is another schematic diagram illustrating the operation of the semiconductor device of the present invention.
FIG. 5 is a schematic diagram illustrating a first modification of the semiconductor device of the present invention.
FIG. 6 is a schematic diagram illustrating an operation of a semiconductor device according to a first modification of the present invention.
FIG. 7 is another schematic diagram illustrating the operation and effect of the first modified example of the present invention.
FIG. 8 is a schematic diagram illustrating a second modification of the present invention.
FIG. 9 is a schematic diagram illustrating a third modified example of the present invention.
FIG. 10 is a schematic diagram illustrating a fourth modification of the present invention.
FIG. 11 is a schematic view illustrating a fifth modification of the present invention.
FIG. 12 is a schematic view illustrating a sixth modification of the present invention.
FIG. 13 is a schematic diagram illustrating a seventh modification of the present invention.
FIG. 14 is a schematic view illustrating an eighth modification of the present invention.
FIG. 15 is a schematic view illustrating a ninth modification of the present invention.
FIG. 16 is a schematic view illustrating a tenth modified example of the present invention.
FIG. 17 is a schematic diagram showing a semiconductor device having a structure in which semiconductor devices of a tenth modification of the present invention are connected in parallel in the reverse direction.
18 is an equivalent circuit diagram of the semiconductor device shown in FIG.
FIG. 19 is a schematic view illustrating an eleventh modification of the present invention.
FIG. 20 is a schematic view illustrating a twelfth modification of the present invention.
FIG. 21 is a schematic view illustrating a thirteenth modification of the present invention.
FIG. 22 is a schematic view illustrating a fourteenth modification of the present invention.
FIG. 23 is a conceptual diagram showing a matrix converter of the present invention.
FIG. 24 is a block diagram illustrating an example of a main configuration of a gate drive system of the semiconductor device in the matrix converter of the present invention.
FIG. 25 is a block diagram illustrating the configuration of a gate function unit 220.
FIG. 26 is a list showing overvoltage protection means in the matrix converter of the present invention.
FIG. 27 is a circuit diagram illustrating a specific example of an overvoltage protection circuit for the semiconductor device 10.
FIG. 28 is a perspective view illustrating the appearance of the matrix converter of the present invention.
FIG. 29 is a cross-sectional view schematically illustrating the structure of an IGBT.
FIG. 30 shows a circuit symbol of the IGBT.
FIG. 31 is a schematic diagram illustrating a main part of a drive circuit of an AC motor using an IGBT.
FIG. 32 is a schematic diagram showing a converter for driving a regenerative motor using an AC power supply.
[Explanation of symbols]
10, 10A, 10B semiconductor device
12 p-type semiconductor layer (substrate)
14 n-type semiconductor layer
14A low concentration area
16 n-type base layer
18 p-type base region
20 n-type source region
22 Guard Ring
24 Gate insulating film
25 polysilicon electrode
26, 26A, 26B Gate electrode
28A, 28B Emitter electrode (collector electrode)
26C field plate
32 Back electrode
40 Field Stopper
44 n-type semiconductor layer
44A n ⁺ Embedding area
44B p ⁺ Embedding area
44C n-type semiconductor region
46 RESURF area
50 insulating film
52 p-type region
60, 60A-60D diode
62 p-type emitter region
70 floating electrode
102 Emitter layer
106 p-type base region
108 source area
110 Gate insulating film
200 Gate drive system
210 signal generator
212 Gate pattern consistency check circuit
212 Consistency Check Circuit
220 Gate function unit
221 Prediction circuit
222 delay time calculation circuit
223 delay circuit
224,226 level shifter
225,227 Gate drive circuit
AC1 to AC3 input / output terminals
C1 Input capacitor
D Depletion region
OP opening
SE1, SE2 Switching element group
T trench
ZD diode

Claims (11)

A first semiconductor layer of a first conductivity type;
A second conductivity type second semiconductor layer provided on the first semiconductor layer;
A first conductivity type first semiconductor region and a first conductivity type second semiconductor region provided apart from each other on a surface of the second semiconductor layer;
A third semiconductor region of a second conductivity type selectively provided on a surface of the first semiconductor region;
A first main electrode connected to the first semiconductor region and the third semiconductor region;
A second main electrode connected to the second semiconductor region;
A first gate insulating film provided on a part of the first semiconductor region and the second semiconductor layer adjacent thereto;
A first gate electrode provided on the gate insulating film,
A semiconductor device comprising:
When no inversion layer is formed on the surface of the first semiconductor region below the first gate insulating film, substantially no current flows between the first and second main electrodes,
When a voltage is applied to the first gate electrode so that an inversion layer is formed on the surface of the first semiconductor region below the first gate insulating film, the second main electrode A semiconductor device, wherein a current can substantially flow toward the first main electrode. The first conductivity type is a p-type;
The second conductivity type is an n-type;
The state in which the current easily flows is such that electrons flow from the first main electrode to the second main electrode via the second semiconductor layer, and from the second main electrode to the second semiconductor layer via the first semiconductor region. 2. The semiconductor device according to claim 1, wherein holes flow through said first main electrode. The first conductivity type is a p-type;
The second conductivity type is an n-type;
When the gate voltage is applied to the first gate voltage, electrons are injected from the first main electrode into the second semiconductor layer through a channel formed in the first semiconductor region. Positively biases a pn junction between the second semiconductor region and the second semiconductor layer, whereby holes are injected from the second semiconductor region into the first semiconductor region, 2. The semiconductor device according to claim 1, wherein a state in which the current easily flows is formed. A second gate insulating film provided on a part of the second semiconductor region and the second semiconductor layer adjacent thereto;
A second gate electrode provided on the second gate insulating film;
A fourth semiconductor region of a second conductivity type selectively provided on a surface of the second semiconductor region;
Further comprising
The second main electrode is connected to the second semiconductor region and the fourth semiconductor region,
When no inversion layer is formed on the surface of the second semiconductor region below the second gate insulating film, substantially no current flows between the first and second main electrodes,
When a voltage is applied to the second gate electrode so that an inversion layer is formed on the surface of the second semiconductor region below the second gate insulating film, the first main electrode The semiconductor device according to any one of claims 1 to 3, wherein a current can substantially flow toward the second main electrode. A third semiconductor layer of a second conductivity type having a lower specific resistance than the second semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. Item 5. The semiconductor device according to any one of Items 1 to 4. 6. The semiconductor device according to claim 5, wherein said third semiconductor layer has an opening provided below said first and second semiconductor regions. A fifth semiconductor region of the first conductivity type provided on the surface of the second semiconductor layer so as to extend from the first semiconductor region toward the second semiconductor region;
A sixth semiconductor region of the first conductivity type provided extending from the second semiconductor region toward the first semiconductor region;
The semiconductor device according to claim 1, further comprising: A concentration of the first conductivity type impurity contained in the fifth semiconductor region is lower than a concentration of the first conductivity type impurity contained in the first semiconductor region;
The concentration of the first conductivity type impurity contained in the sixth semiconductor region is lower than the concentration of the first conductivity type impurity contained in the second semiconductor region. 8. The semiconductor device according to 7. 9. The semiconductor device according to claim 1, wherein an insulator that separates the second semiconductor layer is inserted between the first semiconductor region and the second semiconductor region. 13. The semiconductor device according to claim 1. On the surface of the second semiconductor layer, there is further provided a seventh semiconductor region of the second conductivity type selectively provided between the first semiconductor region and the second semiconductor region. The semiconductor device according to claim 1, wherein: A converter that connects an AC power supply having a plurality of phases and an AC motor having a plurality of input terminals,
11. The semiconductor device according to claim 1, wherein each of the plurality of phases and each of the plurality of input terminals are connected in a matrix to enable a switching operation. And a converter.

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