JP2004342260A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for achieving the speed increase and electric power consumption reduction of the operation. <P>SOLUTION: When one of the regular memory mats (301-0 to 301-3) is selected by memory mat selection signals (MSB 0 to 3) obtained based on a row address signal, a redundancy memory mat (302) is activated in synchronization with the mat selection by a redundancy memory mat activation signal (RMACTB) and the comparison of the row address signal and the redundancy address information is performed in parallel with the mat selection. The speed increase of the operation is achieved by having the bit line of the selection memory mat or the bit line of the redundancy memory mat selected based on the result of the comparison. Also, the memory mat of the side where the bit line is not selected is non-activated, by which the reduction of the electric power consumption is achieved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device provided with a redundant memory mat for relieving defects of memory cells, and relates to a technique which is effective when applied to, for example, a DRAM (Dynamic Random Access Memory).
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor memory device, with an increase in integration degree and an increase in chip area, failures due to various causes occur at a high probability, resulting in a decrease in yield. As a means for solving the problem, a technique for repairing a defective memory cell portion is indispensable. According to this technique, a spare memory cell (redundant bit) is provided in advance in addition to a regular memory cell, and when a defective memory cell that does not operate normally is found in an inspection process, the spare memory cell is replaced with a normal memory cell. It is used in place of a defective memory cell that does not operate quickly, and such a repair technique is called redundancy repair.
[0003]
In a semiconductor memory device requiring particularly high-speed operation, such as a semiconductor memory device used as a cache memory or the like, a full-size redundant memory mat is provided. When the row address signal matches the preset redundant address information (this state is called "hit"), the column selection system on the redundant memory mat side is activated, while the input address signal is When the address does not match the selected redundant address information (this state is referred to as a “miss hit”), the column repair system on the side of the normal memory mat is activated, so that the defect relief that does not have a redundant comparison time effectively is performed. Methods are known. However, in this defect remedy method, since each sub-word line in the redundant memory mat can be replaced only with a sub-word line of the same address in a single normal memory mat, a defect occurs at the same address in a plurality of normal memory mats. In such a case, a data conflict occurs in the replacement with the redundant memory mat. Therefore, in order to avoid this data conflict, a plurality of redundant elements are provided in at least two of the plurality of memory cell arrays, the plurality of memory arrays are divided by sense amplifier banks, and the sense amplifier banks are shared between adjacent memory arrays. There is known a technique for avoiding the above-mentioned data conflict by preventing the same sense amplifier bank from being used simultaneously in defect relief (for example, Patent Document 1).
[0004]
[Patent Document 1]
JP-A-2000-222898 (FIGS. 4 and 5)
[0005]
[Problems to be solved by the invention]
The inventors of the present application have studied the defect relief of a semiconductor memory device that requires particularly high-speed operation, such as a semiconductor memory device used as a cache memory or the like. Since both redundant memory mats are activated at the same time, the power consumption increases. Particularly, in a semiconductor memory device that is on-chip in a system LSI or the like, improvement is strongly desired. In Patent Document 1, although data competition can be avoided by preventing the same sense amplifier bank from being used at the same time in defect relief, no consideration is given to reducing current consumption.
[0006]
An object of the present invention is to provide a technique for achieving high-speed operation and low power consumption.
[0007]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0009]
That is, a plurality of normal memory mats that can be selected by a mat selection signal formed based on a row address signal and activated in synchronization with the mat selection by the mat selection signal, and the normal memory mats are activated in predetermined repair units. A redundant memory mat that can be replaced, a redundant address storage unit that can store redundant address information to be rescued by the redundant memory mat, and the row address signal and the redundant address storage unit in parallel with the mat selection by the mat selection signal. A redundant address comparing unit that can compare the redundant address information with the redundant address information, and a column that can select either a bit line in the normal memory mat or a bit line in the redundant memory mat according to a comparison result of the redundant address comparing unit. According to the comparison result of the selection circuit and the redundant address comparison unit, the column Bit lines 択回 path constituting a semiconductor memory device and a mat controller deactivates the memory mats are unselected.
[0010]
According to the above means, the activated redundant memory mat is activated in synchronization with the mat selection by the mat selection signal, and in parallel with the mat selection by the mat selection signal, the row address signal and the redundant address storage section are activated. And the bit line in the normal memory mat or the bit line in the redundant memory mat is selected according to the address comparison result. This achieves high-speed operation. Then, the mat controller inactivates the memory mat in which the bit line is not selected by the column selection circuit according to the comparison result of the redundant address comparison unit, and suppresses current consumption there. This achieves a reduction in current consumption.
[0011]
At this time, a first sense amplifier arranged corresponding to the normal memory mat and dedicated to the normal memory mat for amplifying a signal of the normal memory mat, and arranged corresponding to the redundant memory mat, A second sense amplifier dedicated to a redundant memory mat for amplifying a signal of the mat can be provided.
[0012]
Further, in order to reduce the chip occupation area of the memory mat, a third sense amplifier shared between the normal memory mat and the redundant memory mat, and a signal of the redundant memory mat and a signal of the normal memory are provided. Can be selectively provided to the third sense amplifier.
[0013]
A plurality of main word lines selected based on upper bits of a row address signal; and a plurality of sub-words arranged corresponding to each of the plurality of main word lines and selected based on lower bits of the row address signal And the predetermined relief unit may be the main word line unit.
[0014]
The redundant address comparing means fetches a plurality of comparison logics for comparing the row address signal and the redundant address information of the redundancy address storage unit and a wired OR signal of the plurality of comparison logics, respectively, and A redundancy hit determination circuit for determining whether a signal matches the redundancy address information.
[0015]
The redundant address comparison circuit includes: a redundant address storage unit capable of storing redundant address information; and a plurality of comparison logics for comparing the input address with the redundant address information respectively stored in the redundant address storage unit. And a redundancy hit determination logic for fetching the wired OR signals of the plurality of comparison logics and determining whether or not the input address signal matches the redundant address information.
[0016]
Then, a first redundant hit determination aggregation circuit for integrating output signals from the redundant hit determination circuit or a second redundant hit determination aggregation circuit for integrating output signals of the plurality of comparison logics can be included. .
[0017]
The mat controller may include a first mat controller arranged corresponding to the normal memory mat and a second mat controller arranged corresponding to the redundant memory mat. In such a case, the first mat controller at least defines a logic of a bit line equalize signal for instructing bit line equalization, a drive signal of the sub word line, and an enable signal for instructing operation of the sense amplifier. It can be configured to include a first array control circuit capable of forming the inactive state of the normal memory mat by fixing the memory array, and the second mat controller based on a comparison result of the redundant address comparison circuit, At least the logics of the bit line equalize signal for instructing the bit line equalization, the drive signal of the sub-word line, and the enable signal for instructing the operation of the sense amplifier are fixed, so that the redundancy memory mat is reset. Second array control circuit capable of forming active state Comprise can be configured.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 18 shows an overall layout example of a DRAM logic mixed LSI chip which is an example of the semiconductor memory device according to the present invention.
[0019]
Although the DRAM logic mixed LSI chip shown in FIG. 18 is not particularly limited, nine SRAM macro cells 251 are arranged in the center, and two I / O (input / output) cell arrays sandwich the SRAM macro cells. 254 are further arranged, and eight DRAM macro cells 200 are arranged so as to sandwich the SRAM macro cell 251 and the I / O cell array 254, and are formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. It is formed. The DRAM macro cell 200 includes a plurality of dynamic memory cells, and the SRAM macro cell 251 includes a plurality of static memory cells. The DRAM macro cell 200 and the SRAM 251 can be externally accessed via the I / O cell array 254.
[0020]
FIG. 19 shows a layout example of one of the eight DRAM macro cells 200.
[0021]
The DRAM macro cell 200 includes an indirect peripheral circuit and power supply circuit 25, a main amplifier (MA) for amplifying a read signal, a write amplifier (WA) 21 for amplifying a write signal, and a laser fuse for storing redundant address information. Forming area 193, normal memory mat 301, redundant memory mat 302 for relieving defects of normal memory mat 301, subword driver 17 for driving subword lines, power supply circuit 23, indirect peripheral circuit, and I / O latch Circuit 24 is included. In the laser fuse forming area 193, laser fuses 197 are regularly arranged so that a part thereof is shown in an enlarged manner.
[0022]
FIG. 20 shows a main part of the laser fuse 197 and a cross section thereof.
[0023]
The laser fuse 197 is formed on the uppermost aluminum (AL) wiring. A chromium (Cr) film 198 is laminated on the uppermost layer aluminum (AL) via a protection film. By irradiating the chromium film 198 with a laser beam, the fuse can be cut, and writing of redundant address information is performed depending on whether the fuse is cut or not. On the uppermost aluminum (AL) wiring, a concave portion is formed by a laminated film of nickel (Ni) / gold (Au).
[0024]
FIG. 5 shows a configuration example of a memory mat in the DRAM macro cell 200.
[0025]
In the present DRAM macro cell 200, the entire mat is divided into four parts via a main amplifier (MA), a write amplifier (WA) 21, and a mat controller 22. The upper mat controller 22 includes an array control circuit (AC), a main word driver (MWD), and an FX driver (FXD), as described later in detail. At the center, an indirect peripheral circuit 25 such as a column selection system is arranged, and at one end, a power supply circuit 23, an indirect peripheral circuit, and an I / O latch circuit 24 are arranged. The memory mat includes a memory cell array 15, a sense amplifier 16 and a sub-word driver 17 arranged so as to sandwich the memory cell array 15, as a part of the memory mat is shown in an enlarged manner. Reference numeral 18 denotes a crossing region with the sense amplifier region and the sub-word driver region. A horizontal row unit is defined as a memory mat with the sense amplifier 16 and the subword driver 17 shared between the memory cell array 15 and the adjacent memory cell array 15 as the minimum unit (subarray).
[0026]
The arrangement combinations of the memory mats include examples shown in FIGS. 6 and 7 in addition to those shown in FIG.
[0027]
FIG. 6 shows an example in which divided mat groups are arranged in a horizontal line, and FIG. 7 shows an upper divided mat group sandwiching a power supply circuit 23, an indirect peripheral circuit, and an I / O latch circuit 24. This is an example of disposing them in a mirror target.
[0028]
FIG. 1 shows a configuration example of a main part of the DRAM macrocell 200. The row system in the DRAM macro cell 200 includes an address buffer 101 for receiving an input row address signal, and a predecoder 102 for predecoding complementary address signals BXT0 to BXT0 and BXB0 to 9 output from the address buffer 101. A redundancy address comparison circuit 103 for performing a redundancy address comparison, an inverter 104 for inverting an output signal RXRHITB of the redundancy address comparison circuit 103 to form an exclusive deactivation signal RXRHITRT, and an output signal AX30 of the predecoder 102. Address selector 105 for selectively transmitting the output signals RHITR0 to RHITR7 of the redundant address comparison circuit 103 to the redundant memory mat 302, the array control, decoding and word drive. Because normal memory mat controller 106-0～106-3, including redundant memory mat controller 402 and the column selection circuit 107. The address buffer 101 has a function of latching an address. The redundant address comparison circuit 103 includes a fuse latch circuit 103-1 in which redundant address information is set, the redundant address information set in the fuse latch circuit 103-1 and the complementary address BXRT0 transmitted from the address buffer 101. 9, a redundant address comparison unit 103-2 for comparing BXRB0 to BXRB9. As a result of the comparison in the redundant address comparison unit 103-2, the local hit signals RHITR0 to RHITR7 and the main hit signal RXRHITB obtained by taking the OR logic thereof are output. Local hit signals RHITR0 to RHITR7 are transmitted to redundant memory mat controller 402 via address scan selector 105. Here, the fuse latch circuit 103-1 is an example of a redundant address storage unit in the present invention.
[0029]
The column selection circuit 107 includes a plurality of normal memory mat side column selection switches for selectively coupling the bit lines in the normal memory mats 301-0 to 301-3 to a common line, and a bit in the redundant memory mat 302. And a plurality of redundant memory side column selection switches for selectively coupling the line to the common line. The normal memory mat side column selection switch and the redundant memory side column selection switch are driven and controlled based on a column address signal. Further, a main hit signal RXRHITB from the redundant address comparison circuit 103 is transmitted to the column selection circuit 107. When the main hit signal RXRHHITB is at a high level (mis-hit), the normal memory mat side column selection switch is activated, so that the bit lines in the normal memory mats 301-0 to 301-3 are selectively common. Joined to a line. At this time, the redundant memory mat side column selection switch is deactivated. On the other hand, when the main hit signal RXRHITB is at a low level (hit), the redundant memory mat side column selection switch is activated instead of the normal memory mat side column selection switch, thereby causing the redundant memory mat The bit line at 302 is selectively coupled to a common line. At this time, the normal memory mat side column selection switch is inactive.
[0030]
When the main hit signal RXRHHITB is at a high level (mis-hit), the normal memory mat controllers 106-0 to 106-3 activate the corresponding normal memory mats 301-0 to 301-3. , The data in the normal memory mats 301-0 to 301-3 can be read and written. At this time, the redundant memory mat controller 402 suppresses current consumption in the redundant memory mat 302 by deactivating the corresponding redundant memory mat 302. On the other hand, when the main hit signal RXRHITB is at a low level (hit), the redundant memory mat is activated to read and write data in the redundant memory mat 302. At this time, the normal memory mats 301-0 to 301-3 are made inactive, so that current consumption in the normal memory mats 301-0 to 301-3 is suppressed.
[0031]
In the above configuration, the input row address signal is taken into the address buffer 101, latched during a RAS (row address strobe) cycle indicating the validity of the row address signal, and the complementary address signals BXT0 to BXT0, BXB0 to BXB9 and BXRTs 0 to 9 and BXRBs 0 to 9 are supplied to the predecoder 102 and the redundant address comparison circuit 103.
[0032]
The predecoder 102 predecodes an input address signal to activate SWL selection predecode signals AX00-03 / AX20-21, AX30-37 / AX60-63, mat select signals MSB0-3, and redundant memory mat activation. The signal RMACTB is output. One of the normal memory mats 301-0 to 301-3 is selected by the mat select signals MSB0 to MSB3. The redundant memory mat 302 is activated by the redundant memory mat activation signal RMACTB. SWL selection predecode signals AX00-03 / AX20-21 are transmitted to normal memory mat controllers 106-0-0-106-3. AX30-37 / AX60-63 are transmitted to normal memory mat controllers 106-0-0-106-3 for selection of main word line MW, and transmitted to redundant memory mat controller 402 via address scan selector 105. . Mat select signals MSB0 to 3 are transmitted to normal memory mat controllers 106-0 to 106-3. Redundant memory mat activation signal RMACTB is transmitted to redundant memory mat controller 402. The AXs 30 to 37 / AXs 60 to 63 are transmitted to the redundant memory mat controller 402 via the address scanning selector 105.
[0033]
In the redundant address comparison unit 103-2, the address comparison is performed between the latch signal of the relief address previously stored in the fuse latch circuit 103-1 and the complementary signal of the row address signal, and the local hit signal of each relief address comparison set. RHITR0 to RHITR7 are input to the redundant memory controller 402 for activation of the relief set of the redundant memory mat. Further, in order to deactivate the unselected memory mats, the main hit signal RXRHITB obtained by taking the OR logic of the local hits RHITR0 to RHITR7 is inverted by the inverter 104 at the subsequent stage, so that the normal memory mat controllers 106-0 to 106-0 106-3 and the redundant memory mat controller 402 are input with phases opposite to each other.
[0034]
FIG. 8 shows a configuration example of the normal memory mat controller 106-0. The other normal memory mat controllers 106-1 to 106-3 are configured similarly to the normal memory mat controller 106-0.
[0035]
FIG. 2 shows an example of a configuration of the normal memory mats 301-0 to 301-3 and the redundant memory mat 302, and a main part thereof.
[0036]
In the example illustrated in FIG. 2, although not particularly limited, the regular memory mats 301-0 to 301-3 and the redundant memory mat 302 are provided with dedicated sense amplifiers (SA) 608 and 635, respectively.
[0037]
The normal memory mats 301-0 to 301-3 are arranged at a plurality of bit lines BL, a plurality of sub-word lines SWL arranged so as to intersect the bit lines BL, and at intersections of the bit lines BL and the sub-word lines SWL. And a plurality of memory cells. Each of the plurality of memory cells includes a charge storage capacitor 630 as one of them is typically shown, and an n-channel MOS transistor 629 for coupling the charge storage capacitor 630 to the bit line BL. N-channel MOS transistor 629 is rendered conductive by driving sub-word line SWL to a high level, and couples charge storage capacitor 630 to corresponding bit line BL.
[0038]
The operation of the sense amplifiers 608 arranged in the normal memory mats 301-0 to 301-3 is controlled by sense amplifier control signals APCSB / ANCST from the corresponding normal memory mat controllers 106-0 to 106-3. The memory cell data amplified by the sense amplifier 608 is transmitted to the read I / O. The sense amplifier 608 is shared between the memory mats disposed so as to sandwich the sense amplifier 608. Therefore, corresponding memory mats are selectively coupled to the sense amplifier 608 by shared circuits 601 and 614. ing. The shared circuit 601 includes n-channel MOS transistors 602 and 603 arranged so that bit lines can be intermittently connected. Although not shown in the drawing, a corresponding one of the normal memory mat controllers 106-0 to 106-3 is provided. The operation is controlled by the shared control signal. Shared circuit 614 includes n-channel MOS transistors 615 and 616 arranged so that bit lines can be intermittently connected, and its operation is controlled by a shared control signal ASHRUT from corresponding normal memory mat controllers 106-0 to 106-3. You.
[0039]
An equalizer 604 is provided between the shared circuit 601 and the sense amplifier 608 for equalizing the bit line BL with a voltage (VDD / 2) of 1/2 of the high-potential power supply VDD. Although not particularly limited, the equalizer 604 is formed by combining three n-channel MOS transistors 605 to 607. The n-channel MOS transistors 606 and 607 are connected in series with each other, and a voltage (VDD / 2) of １ ／ of the high-potential-side power supply VDD is supplied to this series connection node. Bit line equalize signals ABLEQSAT from the corresponding normal memory mat controllers 106-0 to 106-3 are transmitted to the gate electrodes of n channel type MOS transistors 605 to 607. The type MOS transistors 605 to 607 are turned on to equalize the bit line BL. Similarly, near the shared circuit 614, an equalizer 620 for equalizing the bit line BL with a voltage (VDD / 2) of 1/2 of the high potential power supply VDD is provided. Although not particularly limited, this equalizer 620 is formed by combining three n-channel MOS transistors 617 to 619. The n-channel MOS transistors 618 and 619 are connected in series with each other, and a voltage (VDD / 2) of 高 of the high-potential-side power supply VDD is supplied to this series connection node. Bit line equalize signals ABLEQUT from the corresponding normal memory mat controllers 106-0 to 106-3 are transmitted to the gate electrodes of n channel type MOS transistors 617 to 619. The type MOS transistors 617 to 619 are turned on to equalize the bit line BL.
[0040]
In addition, a shared circuit 621 corresponding to a sense amplifier different from the sense amplifier 608 is provided. The shared circuit 621 includes n-channel MOS transistors 623 and 624 arranged so that bit lines can be connected and disconnected. The operation is controlled by a shared control signal ASHRDT from the corresponding normal memory mat controller 106-0 to 106-3. An equalizer 625 for equalizing the bit line BL with half the voltage of the high-potential-side power supply VDD (VDD / 2) is provided near the shared circuit 621. Although not particularly limited, the equalizer 625 is formed by combining three n-channel MOS transistors 626 to 628. The n-channel MOS transistors 627 and 628 are connected in series with each other, and a voltage (VDD / 2) of １ ／ of the high-potential-side power supply VDD is supplied to this series connection node. Bit line equalize signals ABLEQDT from corresponding normal memory mat controllers 106-0 to 106-3 are transmitted to the gate electrodes of n channel type MOS transistors 626 to 628. The type MOS transistors 617 to 619 are turned on to equalize the bit line BL.
[0041]
A write amplifier 609 is arranged near the sense amplifier 608, and write data transmitted via the write I / O is transmitted to the bit line BL after being selected by the write amplifier 609. Although not particularly limited, the write amplifier 609 is formed by combining four n-channel MOS transistors 610 to 613. The operation of the n-channel MOS transistors 610 and 612 is controlled by a column selection signal YS, and the operation of the n-channel MOS transistors 611 and 613 is controlled by a write amplifier control signal WS.
[0042]
Although the redundant memory mat 302 is smaller in size than the normal memory mats 301-0 to 301-3, basically, like the normal memory mats 301-0 to 301-3, a plurality of bit lines BLR and It comprises a plurality of sub-word lines SWLR arranged so as to intersect, and a plurality of memory cells arranged at intersections of the bit lines BLR and the sub-word lines SWLR. The plurality of memory cells include a charge storage capacitor 641 as one of which is representatively shown, and an n-channel MOS transistor 642 for coupling the charge storage capacitor 641 to the bit line BLR. N-channel MOS transistor 642 is rendered conductive by driving sub-word line SWL to a high level, and couples charge storage capacitor 641 to corresponding bit line BLR.
[0043]
The operation of the sense amplifier 635 arranged in the redundant memory mat 302 is controlled by a sense amplifier control signal APCSRB / ANCSRT from the redundant memory mat controller 402. The memory cell data amplified by the sense amplifier 635 is transmitted to the read I / O.
[0044]
In the vicinity of the sense amplifier 635, an equalizer 631 for equalizing the bit line BL with a voltage (VDD / 2) of 1/2 of the high potential side power supply VDD is provided. Although not particularly limited, the equalizer 631 is formed by combining three n-channel MOS transistors 632 to 634. The n-channel MOS transistors 633 and 634 are connected in series with each other, and a voltage (VDD / 2) of 高 of the high-potential-side power supply VDD is supplied to this series connection node. A bit line equalize signal ABLEQSART from the corresponding redundant memory mat controller 402 is transmitted to the gate electrodes of n-channel MOS transistors 632 to 634, and the n-channel MOS transistors 632 to 634 are transmitted by the bit line equalize signal ABLEQSART. Is turned on to equalize the bit line BL.
[0045]
A write amplifier 636 is arranged near the sense amplifier 635, and write data transmitted via the write I / O is transmitted to the bit line BL after being selected by the write amplifier 636. Although not particularly limited, the write amplifier 636 includes four n-channel MOS transistors 637 to 640 coupled. The operation of the n-channel MOS transistors 637 and 639 is controlled by a column selection signal YS, and the operation of the n-channel MOS transistors 638 and 640 is controlled by a write amplifier control signal WS.
[0046]
Here, in the redundant memory mat 302, unlike the normal memory mats 301-0 to 301-3, the sense amplifier 635 is not shared among a plurality of memory mats. 3 does not correspond to the shared circuits 601, 614, 621.
[0047]
FIG. 8 shows a configuration example of the normal memory mat controller 106-0. The other regular memory mat controllers 106-1 to 106-3 have the same configuration.
[0048]
The normal memory mat controller 106-0 is not particularly limited, but as shown in FIG. 8, an array control circuit AC for array control, an FX driver FXD for FX drive, and a main word line for driving main word line. The word driver MWD includes a sub-word driver SWD for driving a sub-word line.
[0049]
Based on the mat selection signals MSB0 to 3 from the predecoder 102 and the other control signals R1B and R2B and the redundant sense amplifier enable signal RSAEB, the array control circuit AC generates a bit line equalize signal ABLEQB, a shared control signal ASHRB, and a word line precharge signal. By generating various control signals such as charge signals WPHMWT, WPHFXT, sub-word line activation signal AXDGB, and sense amplifier control signal APCSB / ANCST, the regular memory mat 106- such as the FX driver FXD, main word driver MWD, sub-word driver SWD, etc. 0 controls the operation of each unit.
[0050]
The FX driver FXD includes eight FX drive circuits for forming drive signals FX0B to FX7B based on the output signals AX00 to AX03, AX20, and AX21 of the predecoder 102. The eight FX drive circuits have the same configuration as each other, and p-channel MOS transistors 81, 82, 85, n-channel MOS transistor 86, inverter 83 are combined. A word line precharge signal WPFXT is transmitted to the gate electrode of the p-channel MOS transistor 81. Then, n-channel MOS transistors 84, 87, 88 and p-channel MOS transistors 89 to 91 for controlling the operation of the eight FX drive circuits are provided. Sub-word line activation signal AXDGB is transmitted to the source electrodes of n-channel MOS transistors 87 and 88, and word line precharge signal WPHFXB is transmitted to the gate electrodes of n-channel MOS transistors 89 to 91.
[0051]
The main word driver MWD includes a plurality of main word drive circuits for forming drive signals for the main word lines MWL0B to MWL31B based on the output signals AX30 to AX37 and AX60 to AX63 of the predecoder 102. A plurality of main word drive circuits for forming the main word line drive signals MWL0B to MWL31B have the same configuration, and as shown representatively of one of them, the p-channel MOS transistor 121, 122 and 123, n-channel MOS transistors 124 and 126, and an inverter 127 are combined. Further, an n-channel MOS transistor 124 corresponding to signals AX30 to AX37 transmitted from predecoder 102 and an n-channel MOS transistor 125 corresponding to signals AX60 to AX63 are provided, and a source electrode of n-channel MOS transistor 125 is provided. The sub-word line activation signal AXDGB is transmitted to the main word line MWL, and the main word line MWL can be selectively driven in a state where the sub-word line activation signal AXDGB is at a low level. Of the sub-word line SWL to be driven. The ends of the main word lines MWL0B to MWL31B are connected to a sub-word driver SWD.
[0052]
The sub-word driver SWD includes a plurality of sub-word drive circuits for driving the sub-word lines SWL based on the control signals FX0B to FX7B from the FX driver FXD and the main word drive signals MWL0B to MWL31B from the main word driver MWD. Including. A sub-word drive circuit corresponding to one sub-word line is formed by combining p-channel MOS transistors 92 and 94 and n-channel MOS transistors 93, 95 and 96. The output signal FX1B of the FX driver FXD is transmitted to the gate electrodes of the MOS transistors 92, 93 and 96, and the inverted signal is transmitted to the source electrode of the MOS transistor 94. The signal of main word line MWL0B is transmitted to the gate electrodes of MOS transistors 94 and 95, and a drive signal of sub-word line SWL is obtained from the serial connection node of MOS transistors 94 and 95.
[0053]
FIG. 9 shows a configuration example of the redundant memory mat controller 402.
[0054]
The redundant memory mat controller 402 basically includes an array control circuit AC for array control, an FX driver FXD for FX drive, and a main word, like the circuits corresponding to the normal memory mats 301-0 to 301-3. It comprises a main word driver MWD for driving a line, and a sub-word driver for driving a sub-word line. However, in the redundant memory mat controller 402, the array control circuit AC transmits the exclusive deactivation signal RXRHITRT and the redundant memory mat activation signal RMACTB, and the main word driver MWD decodes RHITR0 to RHITR7 or AX30 to AX37. This is largely different in that a redundant area test mode switching signal TRATXT is taken in. Further, in the redundant memory mat 302 of this example, as shown in FIG. 2, since the sense amplifier 635 is not shared among a plurality of memory mats, a shared circuit is not required. No circuit control signal (a signal corresponding to ASHRB in FIG. 8) is generated.
[0055]
The main word driver MWD included in the redundant memory mat controller 402 drives the redundant main word lines RMWL0B to RMWL7B based on the output signals AX30 to AX37 of the predecoder 102 and the output signals RHITR0 to RHITR7 of the redundant address comparison circuit 103. To form a redundant main word drive circuit. The plurality of redundant main word drive circuits have the same configuration. As representatively showing the configuration of one of them, p-channel type MOS transistors 131, 132, 133, n-channel type MOS transistors 134, 136, 138 and inverter 137 are connected. Word line precharge signal WPHMWRT is transmitted to the gate electrode of p-channel MOS transistor 131, RHITR0 is transmitted to the gate electrode of n-channel MOS transistor 134, and AX30 is transmitted to the gate electrode of n-channel MOS transistor 138. Is transmitted. Further, redundant area test mode switching signal TRATXT is transmitted to the gate electrode of n-channel MOS transistor 141 via inverter 139 and further transmitted to the gate electrode of n-channel MOS transistor 142 via inverter 140 at the subsequent stage. , The n-channel MOS transistors 134 and 138 are selectively activated.
[0056]
Note that the FX driver FXD and the sub-word driver SWD are configured in the same manner as shown in FIG. 8, and thus detailed description thereof will be omitted.
[0057]
FIG. 10 shows a configuration example of the array control circuit AC in FIG.
[0058]
As shown in FIG. 10, the array control circuit AC corresponding to the normal memory mats 301-0 to 301-3 includes a sub-word activation control circuit 111, a sense amplifier and bit line equalize control circuit 112, a shared and bit line equalize control circuit. 113-1 and 113-2, and a word precharge control circuit 114.
[0059]
The sub-word activation control circuit 111 is formed by combining NOR gates NR1 and NR2, a delay circuit DLY for signal delay, an AND gate AN1, inverters IV1 and IV2, and an n-channel MOS transistor Q1, and includes a control signal DFT and a main hit signal RXRHITB. , A sub-word line activation signal AXDGB is generated by a logical operation of the mat selection signal MSB and the control signal R1B.
[0060]
The sense amplifier and bit line equalize control circuit 112 includes inverters IV3 to IV18, a NAND gate NA2, a NOR gate NR3, and a delay circuit DLY for signal delay, and is combined with a mat select signal MSB, a sense amplifier enable signal RSAEB, and a main hit signal. The sense amplifier control signals APCSB and ANCST are generated by the logical operation of the signal RXRHITB.
[0061]
The shared and bit line equalize control circuit 113-1 is formed by combining inverters IV19 to IV26, a NAND gate NA3, a NOR gate NR5, and a level shift circuit LVSFT, and is a logic of a mat select signal MSB, predecode signals RAX62 and RAX63, and a main hit signal RXRHITB. An arithmetic operation generates a shared control signal ASHRB and a bit line equalize control signal AVLEQB.
[0062]
The shared and bit line equalize control circuit 113-2 is formed by combining inverters IV27 to IV34, a NAND gate NA5, a NOR gate NR6, and a level shift circuit LVLSFT for level conversion, and includes a mat select signal MSB, predecode signals RAXT60, RAXT61, A logical control of the hit signal RXRHITB generates a shared control signal ASHRB and a bit line equalize control signal AVLEQB.
[0063]
The word precharge control circuit 114 is formed by combining inverters IV35 to IV41, an AND gate AN2, and a NOR gate NR7 level shift circuit LVLSFT, and generates word line precharge signals WPHMWT and WPFXFT by logical operation of DFT, MSB, and R2B.
[0064]
FIG. 11 shows a configuration example of the array control circuit AC in FIG.
[0065]
As shown in FIG. 11, the array control circuit AC corresponding to the redundant memory mat 302 includes a sub-word activation control circuit 211, a sense amplifier and bit line equalize control circuit 212, and a word precharge control circuit 214. The array control circuit AC corresponding to the redundant memory mat 302 is not provided with ones corresponding to the shared and bit line equalize control circuits 113-1 and 113-2 shown in FIG.
[0066]
The sub-word activation control circuit 211 is formed by combining inverters IV42 to 45, NAND gates NA7 to NA9, a delay circuit DLY, and an n-channel MOS transistor Q2. Generate.
[0067]
The sense amplifier and bit line equalize control circuit 212 is formed by combining inverters IV46 to IV61, a NAND gate NA9, a NOR gate NR8, and a delay circuit DLY, and outputs a redundant memory mat activation signal RMACTB, a sense amplifier enable signal RSAEB, and a main hit signal RXRHITB. The logic operation generates sense amplifier control signals APCSRB, ANCSRT and bit line equalize signal ABLEQRB.
[0068]
The word precharge control circuit 214 is formed by combining inverters IV62 to IV68, an AND gate AN3, a NOR gate NR9, and a level shift circuit LVLSFT, and generates word line precharge signals WPHMWRT and WPHFXRT by logical operation of DFT, RMACTB, and R2B. I do.
[0069]
FIG. 12 shows a detailed configuration example of the redundant address comparison circuit 103 shown in FIG.
[0070]
As shown in FIG. 12, the redundant address comparison circuit 103 includes a fuse latch circuit 103-1 capable of holding redundant address information, a row address signal input via the address buffer 101, and the fuse latch circuit 103-1. And a redundant hit determination circuit 103-3 for performing a redundant hit determination based on the result of the comparison by the redundant address comparison unit 103-2. A redundant address comparison precharge circuit 103-4 for precharging the redundant address comparison path, and a redundancy hit determination aggregation circuit 103-5 for integrating the output signals of the redundancy hit determination circuit 103-3 are included.
[0071]
FIG. 13 shows a detailed configuration example of the fuse latch circuit 103-1 in relation to the address buffer 101.
[0072]
The address buffer 101 includes a plurality of address buffer circuits arranged corresponding to a 10-bit row address signal RADDa (a = 0 to 9). FIG. 13 representatively shows one circuit configuration of the plurality of address buffer circuits.
[0073]
The address buffer circuit shown in FIG. 13 includes an address latch unit 1340 for latching an input row address signal RADDa, an output unit 1360 for transmitting an output signal of the address latch unit 1340 to a subsequent circuit, An operation timing control unit 1350 for controlling the operation timing of the address latch circuit 1340 and the output unit 1360 is included.
[0074]
The address latch unit 1340 is formed by combining tri-state buffers 1316 and 1317 and an inverter 1318. The operation of the tri-state buffers 1316 and 1317 is controlled by the operation timing control unit 1350.
[0075]
The output unit 1360 includes inverters 1319, 1320, 1321, 1322, 1324, and 1326, and NOR gates 1323 and 1325. Output signal RBXTa is obtained from inverter 1320. Output signal RBXBa is obtained from inverter 1322. The output signals RBXTa and RBXBa are transmitted to the predecoder 102. Further, an output signal RBXRTa is obtained from the inverter 1324, and an output signal RBXRBa is obtained from the inverter 1326. The output signals RBXRTa and RBXRBa are transmitted to the redundant address comparator 103-2 together with the output signal RFSmnBa (m = 0 to 7, n = T / B, a = 0 to 9) of the fuse latch circuit 103-1 described later. You. The suffix “T” in the signal name indicates normal rotation, and “B” indicates reverse.
[0076]
The operation timing control unit 1350 includes an inverter 1311 that receives an internal RAS signal (row active signal) PIRAST, a NAND gate 1312 that obtains a NAND logic between an output signal of the inverter 1311 and a row reset signal R3B, and an output from the NAND gate 1312 based on the output. Inverters 1313 and 1314 for controlling the operation of the tri-state buffers 1316 and 1317, and an inverter 1315 for controlling the operation of the output unit 1360 based on the output signal of the NAND gate 1312.
[0077]
Although not particularly limited, the fuse latch circuit 103-1 includes eight fuse latch units, one of which is representatively shown in FIG. One fuse latch unit includes a fuse 1305, n-channel MOS transistors 1301 to 1304, and inverters 1306 and 1307. The fuse 1305 and the n-channel MOS transistors 1301 to 1303 are connected in series. Fuse 1305 is coupled to high potential power supply VDD. This fuse 1305 is a part of the laser fuse 197 shown in FIGS. The set signal SET is transmitted to the gate electrode of the n-channel MOS transistor 1301, and the redundant address information of the fuse latch circuit 103-1 can be read while the set signal SET is at a high level. The n-channel MOS transistors 1302 and 1303 are turned on when the high potential side power supply VDD is supplied to their gate electrodes. The source electrodes of the n-channel MOS transistors 1303 and 1304 are coupled to the lower potential power supply VSS. Inverters 1306 and 1307 are connected in series, and output signal RFSmnBa is obtained from inverter 1307. When the output signal of the inverter 1306 is fed back to the input terminal side of the inverter 1306 via the n-channel MOS transistor 1304, a latch circuit for holding the logic of the output signal RFSmnBa is formed.
[0078]
Writing of redundant address information is performed depending on whether the fuse 1305 is cut or not. When the fuse 1305 is not blown, the output signal RFSmnBa from the inverter 1307 is at a high level. On the other hand, when the fuse 1305 is cut, the output signal RFSmnBa from the inverter 1307 is at a low level.
[0079]
FIG. 14 shows a detailed configuration example of the redundant address comparison unit 103-2.
[0080]
The redundant address comparison unit 103-2 includes eight comparison circuits COMP0 to COMP7 formed corresponding to the fuse latch units in the fuse latch circuit 103-1 and output signals RBXRTa and RBXRBa (a) of the address buffer 101. = 0 to 9).
[0081]
Although not shown in the drawing, the eight comparison circuits COMP0 to COMP7 have the same configuration. The eight comparison circuits COMP0 to COMP7 each include an output signal RBXRTa (a = 0 to 9) and an RBXRBa (a = 0) of the address buffer 101 so that one of the comparison circuits COMP0 is representatively shown. 9) comprising a plurality of comparison logics 500 corresponding to. Although not particularly limited, the comparison logic 500 includes four n-channel MOS transistors 501 to 504. Wired OR of the plurality of comparison logics 500 is performed for each of the comparison circuits COMP0 to COMP7, and the result is transmitted to the redundancy hit determination circuit 103-3. In order to reduce the number of wires between the fuse latch circuit 103-1 and the redundant address comparison unit, the plurality of comparison logics 500 include an inverter 505 between the gate electrodes of the n-channel MOS transistors 502 and 504. Some are joined by. N-channel MOS transistors 501 and 502 are connected in series, and n-channel MOS transistors 503 and 504 are connected in series. The signal RBXRTa (a = 0 to 9) is transmitted to the gate electrode of the n-channel MOS transistor 501 via the corresponding inverter 90. RBXRBa (a = 0 to 9) is transmitted to the gate electrode of the n-channel MOS transistor 503 via the corresponding inverter 90. The output signal RFSmTBa (m = 0 to 7, a = 0 to 9) of the fuse latch circuit 103-1 is transmitted to the gate electrode of the n-channel MOS transistor 502. The output signal RFSmBBa (m = 0 to 7, a = 0 to 9) of the fuse latch circuit 103-1 is transmitted to the gate electrode of the n-channel MOS transistor 504. SW is a switch for enabling a change in the circuit scale involved in the circuit operation in the redundant address comparison unit.
[0082]
In comparison circuits COMP0 to COMP7, signals RBXRTa (a = 0 to 9) and RBXRBa (a = 0 to 9) transmitted from address buffer 101 and signal RFSmnBa (m = 0) transmitted from fuse latch circuit 103-1. , N = T / B, a = 0 to 9), and the comparison results RFU00 to RFU07, RFU10 to RFU17 are transmitted to the subsequent redundant hit determination circuit 103-3.
[0083]
As shown in FIG. 12, the redundant hit determination circuit 103-3 includes eight redundant hit determination units JUD0 to JUD7 arranged corresponding to the comparison circuits COMP0 to COMP7 in the redundant address comparison unit 103. The eight redundant hit determination units JUD0 to JUD7 have the same configuration. For example, the redundant hit determination unit JUD0, which is one of the eight redundant hit determination units JUD0 to JUD7, includes p-channel MOS transistors 1201, 1203 to 1205, inverters 1206, 1210, 1211, a NAND gate 1209, and an n-channel MOS It comprises transistors 1207 and 1208. P-channel MOS transistors 1201 and 1205 are provided for precharging the redundant address comparison path to the high potential side power supply VDD level, and take in a precharge control signal RXRPT from redundant address comparison precharge control circuit 103-4. The operation is controlled by the output signal of 1206. The p-channel MOS transistors 1203 and 1204 are provided to latch the output state of the NAND gate 1209. An output signal RHIT0 is obtained from the NAND gate 1209 and transmitted to the redundant hit determination aggregation circuit 103-5. Also, an output signal RHITR0 is obtained via inverters 1210 and 1211 arranged at the subsequent stage of NAND gate 1209, and this signal RHITR0 is transmitted to redundant memory mat controller 402 via selector 105 as shown in FIG. . When the redundant area skip mode signal TRSKT is at a high level, the redundant hit determination is skipped.
[0084]
The redundant address comparison precharge control circuit 103-4 includes an inverter 1213 for receiving an internal RAS signal (row active signal) ILAST, a NAND gate 1214 for obtaining a NAND logic of an output signal of the inverter 1213 and the row reset signal R3B, and a NAND gate 1214. It comprises an inverter 1215 for inverting the output signal of 1214 to obtain a precharge control signal RXRPT.
[0085]
FIG. 15 shows a configuration example of the redundant hit determination aggregation circuit 103-5.
[0086]
The redundant hit determination aggregation circuit 103-5 includes three-input NAND gates 151, 152, two-input NAND gates 153, 155, three-input NOR gate 154, and inverters 156, 157. The three-input NAND gate 151 obtains NAND logic for the local hit signals RHIT0 to RHIT3 from the redundant hit determination circuit 103-3. The three-input NAND gate 152 obtains NAND logic for the local hit signals RHIT3 to RHIT5 from the redundant hit determination circuit 103-3. The two-input NAND gate 153 obtains the NAND logic of the local hit signals RHIT6 and RHIT7 from the redundant hit determination circuit 103-3. The output signals of the NAND gates 151, 152, and 153 are collected by a NOR gate 154 disposed at a subsequent stage and transmitted to a NAND gate 155 at a subsequent stage. In the NAND gate 155, a NAND logic of an output signal of the inverter 157 that takes in the redundant area forced selection mode signal TRATTX and an output signal of the NOR gate 154 is obtained, and the output signal is output via the inverter 156 in the subsequent stage. The output signal of inverter 156 is transmitted as main hit signal RXRHITB to normal memory mat controllers 106-0 to 106-3 and column selection circuit 107 shown in FIG. Is transmitted to
[0087]
Next, the operation of the above configuration will be described.
[0088]
FIG. 16 shows a row-related operation timing when the DRAM macro cell 200 hits a miss, and FIG. 17 shows a row-related operation timing when the DRAM macro cell 200 hits. The DRAM macro cell 200 operates synchronously with the clock signal CLK_N, for example, taking in the row address signal during a period in which the row address strobe signal RAS_N is asserted to a low level in synchronization with the falling edge of the waveform of the clock signal CLK_N. The column address is fetched into the column address strobe signal during a period in which the column address strobe signal is asserted to a low level in synchronization with the falling edge of the waveform of the clock signal CLK_N, but the column-related signals are omitted. .
[0089]
It is assumed that the defect relief is performed for each main word line MWL. That is, based on the comparison result between the input address signal and the redundant address information, the defective portion in the normal memory mat is relieved by being replaced with the redundant memory cell array in units of the main word line MWL. This unit of relief is called a "relief set". When the input address signal and the redundant address information match (redundancy hit) in a specific rescue set, the main memory driver MWD (RMWLnB / n = 0 to 7) corresponding to the rescue set in the redundant memory mat 302. And FX driver FXD (FXnB / n = 0 to 7) are selected, and sub-word line SWL in redundant memory mat 302 is activated.
[0090]
On the other hand, the sub-word lines SWL in the normal memory mats 301-0 to 301-3 are deactivated by setting the main word driver MWD and the FX driver FXD to a non-selected state.
[0091]
Such control is exclusively performed by the array control circuit AC in the normal memory mat controllers 106-0 to 106-3 and the redundant memory mat controller 402.
[0092]
That is, when the main hit signal RXRHHITB is at the high level (mis-hit), the array control circuit AC in the normal memory mat controllers 106-0 to 106-3 sets the bit line equalize signal ABLEQB to the high level as shown in FIG. , The bit line equalization release is instructed, and the shared control signal ASHRT is set to the high level (ASHRB is set to the low level), thereby coupling the memory mat and the corresponding sense amplifier, and the word line precharge signal WPHMWT, By setting WPFXXT to low level, the precharge of the corresponding word line is released, and by setting the sub word line activation signal AXDGB to low level, the sub word line can be driven, and the sense amplifier control signal APCSB / ANCS The activating. When the main hit signal RXRHITB is at a high level (mis-hit), the exclusive deactivation signal RXRHITRT is at a low level, so that the array control circuit AC in the redundant memory mat controller 402 sets the bit line equalize signal ABLEQRB to a low level. Level (standby state), the word line precharge signals WPHMWRT, WPFXRT are set to high level to instruct word line precharge, the FX driver control signal AXDGRB is fixed to high level (inactive state), and sense is performed. By activating the amplifier control signal APCSRB / ANCSRT, current consumption in the redundant memory mat 302 is suppressed.
[0093]
On the other hand, when the main hit signal RXRHHITB is at a low level (hit), the array control circuit AC in the normal memory mat controllers 106-0 to 106-3 outputs the bit line equalize signal ABLEQB as shown in FIG. The corresponding word is fixed at a low level (standby state), the shared control signal ASHRT is fixed at a low level (ASHRHB is at a high level) (inactive state), and the word line precharge signals WPHMWT and WPFXTXT are set at a high level. By precharging the lines, fixing the sub-word line activation signal AXDGB to a high level (inactive state), and inactivating the sense amplifier control signals APCSB / ANCST, the normal memory mats 301-0 to 301- Current consumption at 3 The suppress. When the main hit signal RXRHITB is at a low level (hit), the exclusive deactivation signal RXRHITRT is at a high level. Therefore, the array control circuit AC in the redundant memory mat controller 402 sets the bit line equalize signal ABLEQRB to a high level. To cancel the word line precharge by setting the word line precharge signals WPHMWRT and WPFXRT to low level, and set the FX driver control signal AXDGRB to low level to set the FX driver Is operated to activate the sense amplifier control signal APCSRB / ANCSRT, whereby data can be read from the redundant memory mat 302 and data can be written to the redundant memory mat 302.
[0094]
As described above, when the main hit signal RXRHITB is at a high level (mis-hit), the normal memory mats 301-0 to 301-3 are controlled by the array control circuit AC in the normal memory mat controllers 106-0 to 106-3. Are activated, data can be written to the normal memory mats 301-0 to 301-3 and data can be read from the normal memory mats 301-0 to 301-3. Since the deactivation signal RXRHITRT is set to low level and each part of the redundant memory mat 302 is deactivated, current consumption in the redundant memory mat 302 is suppressed.
[0095]
When the main hit signal RXRHHITB is at a low level (hit), each part of the normal memory mats 301-0 to 301-3 is controlled by the array control circuit AC in the normal memory mat controllers 106-0 to 106-3. The current consumption is suppressed by being deactivated. In this case, the exclusive deactivation signal RXRHITRT is set to the high level, and each part of the redundant memory mat 302 is activated, so that the redundant memory mat 302 Data reading and data writing to the redundant memory mat are enabled.
[0096]
According to the above example, the following effects can be obtained.
[0097]
(1) When any one of the normal memory mats 301-0 to 301-3 is selected by the memory mat selection signals MSB0 to MSB3 obtained by pre-decoding the row address signal by the pre-decoder 102, the redundant memory By the mat activation signal RMACTB, the redundant memory mat 302 is activated in synchronization with the mat selection by the mat selection signals MSB0 to MSB3. In the redundant address comparison circuit, the input row address signal and the redundant address information are compared in parallel with the above mat selection, and in the case of a mishit in the address comparison, the column selection circuit 107 When a bit line in the selected memory mat is selected and a hit occurs in the address comparison, the bit line in the redundant memory mat 302 is selected by the column selection circuit 107, so that high-speed operation is possible. Is done.
[0098]
(2) The redundant address comparison unit 103-2 has a plurality of comparison circuits COMP0 to COMP7 arranged corresponding to the repair set, and the defect is repaired based on the comparison result of the comparison circuits COMP0 to COMP7. For this reason, as shown in FIG. 3, for example, as shown in FIG. 3, the redundant memory mat 302 uses a main word driver (MWD) unit corresponding to a plurality of sub-word lines as a repair unit per one set of the repair address comparison circuit, and The repair set can correspond to all sub-word lines in all the normal memory mats 301, and can be replaced in main word units. Here, as shown in FIG. 4, when the redundant memory mat to be used has the same address configuration (full mat) as the normal memory mat, the same memory configuration is used for a plurality of mats due to a collision of a relief destination (data conflict). Since address rescue is physically impossible, the area overhead for the redundant memory mat increases, and the improvement of rescue efficiency is hindered by the collision of the rescue destination. Comparing circuits COMP0 to COMP7 are arranged corresponding to the unit, and each of the comparing circuits can compare the input address signal with the preset redundant address information. Of the normal memory mat 301 can avoid data conflict in defect repair. Rukoto can.
[0099]
(3) In the normal memory mat controllers 106-0 to 106-3 and the redundant memory mat controller 402, the memory mat in which the bit line is not selected by the column selection circuit 107 is inactivated. In the memory mat in which the bit line is not selected by the column selection circuit 107, the charge / discharge current due to the useless activation operation can be suppressed, and the current consumption in the DRAM macro cell 200 can be reduced.
[0100]
Next, another configuration example will be described.
[0101]
FIG. 24 shows an example of the configuration of the normal memory mat 301-0 and the redundant memory mat 302, and the main parts thereof. It should be noted in the configuration shown in FIG. 24 that the sense amplifier (SA) 635 is shared between the redundant memory mat 302 and the normal memory mat 301-0 disposed adjacent to the redundant memory mat 302. Therefore, shared circuits 700 and 720 are provided. Shared circuit 700 includes n-channel MOS transistors 711 and 712. The operations of the n-channel MOS transistors 711 and 712 are controlled by a shared control signal ASHRUT. Shared circuit 720 includes n-channel MOS transistors 721 and 722. The operations of the n-channel MOS transistors 721 and 722 are controlled by a shared control signal ASHRSRT.
[0102]
Since the sense amplifier (SA) 635 is shared between the redundant memory mat 302 and the normal memory mat 301-0 disposed adjacent to the redundant memory mat 302, the number of sense amplifiers can be reduced. The area occupied by the chip can be reduced.
[0103]
FIG. 25 shows an example of the configuration of array control circuit AC in normal memory mat controllers 106-0 to 106-3 when the configuration shown in FIG. 24 is employed, and FIG. A configuration example of the array control circuit AC in the redundant memory mat controller 402 when the configuration is adopted is shown. The array control circuit AC shown in FIG. 25 includes a sub-word activation control circuit 111, a sense amplifier and bit line equalization control circuit 112, shared and bit line equalization control circuits 113-1 and 113-2, and a word precharge control circuit 114. , And each circuit has the same configuration as that shown in FIG. In contrast, array control circuit AC in redundant memory mat controller 402 shown in FIG. 26 includes sense amplifier (SA) 635 between redundant memory mat 302 and normal memory mat 301-0 arranged adjacent thereto. Since shared and shared circuits 700 and 720 are provided, sense amplifiers and bit line equalize control circuits 212-1 and 212-2 and shared and bit line equalize control circuits 213 are provided. Is greatly different from the case shown in FIG. Note that the sub-word activation control circuit 211, the sense amplifier and bit line equalize control circuit 212-1 and the word precharge control circuit 214 have the same configuration as that shown in FIG.
[0104]
The sense amplifier and bit line equalize control circuit 212-1 has the same configuration as the sense amplifier and bit line equalize control circuit 212 shown in FIG. On the other hand, the sense amplifier and bit line equalize control circuit 212-2 is provided for controlling the operation of the shared part of the sense amplifier (SA) 635 between the redundant memory mat 302 and the normal memory mat 301-0. It includes inverters IV87 to IV102, NAND gates NA12, NOR gates NR12 to NR13, and a delay circuit DLY, and has a logic of a redundant memory mat activation signal RMACTB, a sense amplifier enable signal RSAEB, a main hit signal RXRHITB, and a mat selection signal MSB. By the operation, the sense amplifier control signals APCSSB and ANCSST and the bit line equalize signal ABLEQSB are generated.
[0105]
The shared and bit line equalize control circuit 213 includes inverters IV103 to IV108, a NAND gate NA13, a NOR gate NR14, a delay circuit DLY, and a level shift circuit LVLSFT, and performs logic of the exclusive deactivation signal RXRHITRT and the redundant memory mat activation signal RMACTB. An arithmetic operation generates a shared control signal ASHRB and a bit line equalize signal ABLEQB.
[0106]
The redundant memory mat 302 can share a sense amplifier with any of the regular memory mats 301-0 to 301-3. For example, in the configuration example shown in FIG. 27, the sense amplifier 635 is shared between the redundant memory mat 302 and the normal memory mat 301-1.
[0107]
FIG. 28 shows another configuration example of the redundant hit determination circuit 103-5. The redundant hit determination circuit 103-5 shown in FIG. 28 obtains the main hit signal RXRHITB by directly integrating the comparison results RFU00 to RFU07 and RFU10 to RFU17 in the redundant address comparison unit 103-2 by complex logic. ing. Although not particularly limited, the composite logic includes NAND gates 71, 72, 73 for obtaining an OR logic of the comparison result in the redundant address comparison unit 103-2, a NAND gate 74, and an inverter 75.
[0108]
Although the invention made by the present inventors has been specifically described above, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention.
[0109]
For example, in the inactive state of the normal memory mats 301-0 to 301-3 and the redundant memory mat 302, by fixing the logic of the word line precharge signals WPHMWT / WPHMWRT, WPFXT / WPHFXRT, the current in the inactive memory mat is fixed. Consumption can be further reduced.
[0110]
Further, the present invention can be applied to general-purpose DRAM chips.
[0111]
FIG. 21 shows a layout example of a general-purpose DRAM chip.
[0112]
The memory mat of the general-purpose DRAM chip 210 shown in FIG. 21 is divided into two in the bit line direction and two in the word line direction. The divided memory mat includes a regular memory mat 69 and a redundant memory mat 20. A main row decoder 11, a main word driver 12, a peripheral circuit, and a bonding pad 14 for decoding a row address signal are formed in the center of the chip. The redundant memory mat 20 is formed so as to sandwich the peripheral circuit and the bonding pad 14. In the normal memory mat 69, as partially enlarged, a memory cell array 15, a sense amplifier 16 and a sub-word driver 17 arranged so as to sandwich the memory cell array 15 are arranged. Reference numeral 18 denotes a crossing region with the sense amplifier region and the sub-word driver region. The redundant memory mat 20 includes a redundant memory cell array 15R, a sense amplifier 16 and a sub-word driver 17 arranged so as to sandwich the redundant memory cell array 15R, as shown in a partially enlarged manner. A dedicated sense amplifier is used between the mat 69 and the redundant memory mat. On the other hand, as shown in FIG. 22, the sense amplifier 16 can be shared between the redundant memory cell array 15R and the normal memory cell array 15 arranged adjacent thereto. For sharing the sense amplifier, the shared technology described above is used. Further, as shown in FIG. 23, the redundant memory mat 20 can be formed at an arbitrary position. In this case, the sense amplifier is shared between the redundant memory cell array and the normal memory cell array adjacent thereto. can do.
[0113]
Generally, the formation area of the redundant memory mat may be smaller than the formation area of the normal memory mat, but is not limited thereto. For example, the formation area of the redundant memory mat and the formation area of the normal memory mat may be equal.
[0114]
In the above description, the case where the invention made by the present inventor is applied to a DRAM, which is the background of the application, has been mainly described. However, the present invention is not limited to this, and is applied to various semiconductor memory devices. be able to.
[0115]
The present invention can be applied on the condition that it includes at least a plurality of regular memory mats and a redundant memory mat capable of repairing the regular memory mats.
[0116]
【The invention's effect】
The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.
[0117]
That is, the activated redundant memory mat is activated in synchronization with the mat selection by the mat selection signal, and in parallel with the mat selection by the mat selection signal, the row address signal is compared with the redundant address information of the redundant address storage unit. According to the address comparison result, either the bit line in the normal memory mat or the bit line in the redundant memory mat is selected, so that the operation can be speeded up. The mat controller deactivates the memory mat in which the bit line is not selected by the column selection circuit in accordance with the comparison result of the redundant address comparison unit, thereby suppressing current consumption there. Is achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a main part in a DRAM macro cell as an example of a semiconductor memory device according to the present invention.
FIG. 2 is a circuit diagram illustrating a configuration example of a memory mat and the redundant memory mat in the DRAM macro cell and a main part thereof.
FIG. 3 is an explanatory diagram of defect relief in the DRAM macro cell.
FIG. 4 is an explanatory diagram of defect relief in a DRAM macro cell to be compared with the DRAM macro cell.
FIG. 5 is an explanatory diagram of a mat definition in the DRAM macro cell.
FIG. 6 is an explanatory diagram of an example of a mat arrangement combination in the DRAM macro cell.
FIG. 7 is an explanatory diagram of an example of a mat arrangement combination in the DRAM macro cell.
FIG. 8 is a circuit diagram illustrating a configuration example of a normal memory mat controller in the DRAM macro cell.
FIG. 9 is a circuit diagram showing a configuration example of a redundant memory mat controller in the DRAM macro cell.
FIG. 10 is a detailed configuration example circuit diagram of a main part in FIG. 8;
11 is a detailed configuration example circuit diagram of a main part in FIG. 8;
FIG. 12 is a circuit diagram showing a configuration example of a redundant address comparison circuit in the DRAM macro cell.
FIG. 13 is a detailed configuration example circuit diagram of a fuse latch circuit included in the redundant address comparison circuit and an address buffer corresponding thereto.
FIG. 14 is a circuit diagram illustrating a detailed configuration example of a redundant address comparing unit included in the redundant address comparing circuit;
FIG. 15 is a circuit diagram illustrating a configuration example of a redundant hit determination aggregation circuit included in the redundant address comparison circuit.
FIG. 16 is a timing chart of row-related operations at the time of a mishit in the DRAM macro cell.
FIG. 17 is a timing chart of row-related operations when the DRAM macro cell hits.
FIG. 18 is an explanatory diagram of an overall layout example of a DRAM logic mixed LSI chip including the DRAM macro cell.
FIG. 19 is an explanatory diagram of a layout of the DRAM macro cell.
FIG. 20 is a diagram illustrating a configuration example of a laser fuse used for defect remedy in the DRAM macro cell.
FIG. 21 is a layout explanatory diagram of a general-purpose DRAM chip as another example of the semiconductor memory device according to the present invention.
FIG. 22 is an explanatory diagram of a layout of the general-purpose DRAM chip.
FIG. 23 is an explanatory diagram of a layout of the general-purpose DRAM chip.
FIG. 24 is a circuit diagram of another configuration example of a normal memory mat and a redundant memory mat in the DRAM macro cell and a main part thereof.
FIG. 25 is a circuit diagram showing a configuration example of an array control circuit in a normal memory mat controller when the configuration shown in FIG. 24 is adopted;
26 is a circuit diagram showing a configuration example of an array control circuit in a redundant memory mat controller when the configuration shown in FIG. 24 is adopted;
FIG. 27 is a circuit diagram of another configuration example of a normal memory mat and a redundant memory mat in the DRAM macro cell and a main part thereof.
FIG. 28 is a circuit diagram showing another configuration example of the redundant hit determination circuit in the DRAM macro cell.
[Explanation of symbols]
101 Address buffer
102 predecoder
103 Redundant address comparison circuit
103-1 Fuse latch circuit
103-2 Redundant Address Comparison Unit
103-3 Redundant Hit Determination Circuit
103-4 Redundant Address Comparison Precharge Circuit
103-5 Redundant Hit Judgment Aggregation Circuit
106-0 to 106-3 Regular memory mat controller
107 Column selection circuit
200 DRAM macrocell
301-0 to 301-3 Regular memory mat
302 Redundant memory mat
402 Redundant memory mat controller
500 comparison logic
AC array control circuit
FXD FX driver
MWL main word line
MWD main word driver
SWD sub-word driver
SWL sub-word line
SA sense amplifier

Claims (9)

A plurality of normal memory mats selectable by a mat selection signal formed based on a row address signal;
A redundant memory mat activated in synchronization with the mat selection by the mat selection signal and capable of replacing the normal memory mat with a predetermined repair unit;
A redundancy address storage unit capable of storing redundancy address information to be relieved by the redundancy memory mat;
A redundancy address comparison unit that can compare the row address signal and redundancy address information of the redundancy address storage unit in parallel with the mat selection by the mat selection signal;
A column selection circuit capable of selecting either a bit line in the normal memory mat or a bit line in the redundant memory mat according to a comparison result of the redundant address comparing means;
A semiconductor memory device, comprising: a mat controller for inactivating a memory mat in which a bit line is not selected by the column selection circuit according to a comparison result of the redundant address comparison means. A first sense amplifier dedicated to the normal memory mat for amplifying a signal of the normal memory mat, the first sense amplifier being arranged corresponding to the normal memory mat;
2. The semiconductor memory device according to claim 1, further comprising a second sense amplifier arranged corresponding to said redundant memory mat and dedicated to said redundant memory mat for amplifying a signal of said redundant memory mat. A third sense amplifier provided between the normal memory mat and the redundant memory mat arranged adjacent thereto and shared between the normal memory mat and the redundant memory mat;
3. The semiconductor memory device according to claim 1, further comprising: a shared circuit capable of selectively transmitting a signal of said redundant memory mat and a signal of said normal memory to said third sense amplifier. 4. The semiconductor memory device according to claim 1, wherein a formation area of the redundant memory mat is smaller than a formation area of the normal memory mat. A plurality of main word lines selected based on upper bits of a row address signal; and a plurality of sub-words arranged corresponding to each of the plurality of main word lines and selected based on lower bits of the row address signal 5. The semiconductor memory device according to claim 1, wherein the predetermined repair unit is the main word line unit. A plurality of comparison logics for comparing the row address signal with redundant address information in the redundant address storage unit;
6. A redundancy hit determination circuit for taking in the wired OR signals of the plurality of comparison logics and determining whether the row address signal matches the redundancy address information. 2. The semiconductor memory device according to claim 1. A first redundant hit determination aggregation circuit for aggregating output signals from the redundant hit determination circuit;
7. The semiconductor memory device according to claim 6, wherein said mat controller deactivates a memory mat whose bit line is not selected by said column selection circuit based on an output signal of said first redundant hit determination aggregation circuit. A second redundant hit determination aggregation circuit for aggregating the output signals of the plurality of comparison logics, wherein the mat controller determines whether a bit line in the column selection circuit is based on an output signal of the second redundancy hit determination aggregation circuit. 7. The semiconductor memory device according to claim 6, wherein the memory mat which is not selected is inactivated. The mat controller includes a first mat controller arranged corresponding to the normal memory mat, and a second mat controller arranged corresponding to the redundant memory mat,
The first mat controller, based on the comparison result of the redundant address comparison circuit, at least instructs a bit line equalize signal for instructing bit line equalization, a drive signal for the sub word line, and an operation of the sense amplifier. A first array control circuit capable of forming the inactive state of the normal memory mat by fixing the logic of an enable signal for performing
The second mat controller fixes at least the logic of a bit line equalize signal for instructing bit line equalization, the drive signal of the sub word line, and the enable signal for instructing operation of the sense amplifier. 9. The semiconductor memory device according to claim 5, further comprising a second array control circuit capable of forming an inactive state of said redundant memory mat.

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