JP2004336661A - Method and instrument for picture decoding - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform decoding by smaller operand when encoded each pixel is decoded by using template based on a reference pixel. <P>SOLUTION: Source position of template in a first register which memorizes data of decoded pixels is fixed, and data of a group of the decoded pixels contained in the template are read to a second register (S103). The data of the group of the pixels which are read to the second register are linked in single dimension (S104). By using the linked data of the group of the pixels, pixels which are encoded by using the data of the group of the pixels at the time of encoding are decoded. Decoded data of the pixels are overwritten on data of the pixels before decoding in the first register. After that, storage location of each data memorized with the first register is shifted in the predetermined direction by 1 bit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is directed to image decoding for decoding image encoded data obtained by encoding pixel data in an image using data of a pixel group included in a template arranged at a position corresponding to the position of the pixel. The present invention relates to an apparatus and an image decoding method performed by the image decoding apparatus.
[0002]
[Prior art]
A conventional decoding method of image information encoded by predicting a pixel value of a processing target pixel from a reference pixel data group determined by a template shape will be described with reference to FIGS.
[0003]
FIG. 4A is a diagram showing an example of the shape of a template used when decoding image information, and FIG. 4B is a diagram showing the use of a template for decoding image information encoded by the above encoding method. It is a figure for explaining a method. FIG. 5 is a diagram showing how to obtain a one-dimensionally linked reference pixel data group from the decoded pixel data group read into the first register group.
[0004]
In FIG. 4A, when decoding the image information at the position indicated by A (hereinafter referred to as “processing target pixel A”), a group of decoded pixel data located in the vicinity (the shaded portion in FIG. Region). Since these reference pixel data groups are usually stored on the memory, when these reference pixel data groups are used, it is necessary to read these reference pixel data groups from the memory into a predetermined register and store them.
[0005]
Since the template shown in FIG. 4B extends over three rows, three registers 1, 2, and 3 are prepared as a first register group as shown in FIG. 5, and are stored in the memory at the time of decoding. The decoded pixel data group is read out and stored in these register groups. Register 1 stores the decoded pixel data group in the (m-2) th row, register 2 stores the decoded pixel data group in the (m-1) th row, and register 3 stores the same row as the pixel A to be processed. m (hereinafter, processing target row) decoded pixel data groups are read and stored.
[0006]
Since reading of data from the memory to the register is usually performed in byte units, unnecessary decoded pixel data groups other than the reference pixel data group may be simultaneously read. Therefore, as shown in FIG. 5, registers 4, 5, and 6 are prepared as the second register group having the same number as the first register group, and the reference pixel data group read from the first register group is masked to form the second register group. Fetches only the reference pixel data group into the register group. That is, a mask is applied to the decoded pixel data group read from the register 1 to obtain a reference pixel data group in the first row of the template in the register 4. Further, a mask is applied to the decoded pixel data group read from the register 2 to obtain a reference pixel data group in the second row of the template in the register 5. Similarly, a mask is applied to the decoded pixel data group read from the register 3 to obtain a reference pixel data group in the third row of the template in the register 6.
[0007]
All necessary reference pixel data groups are divided and stored in the three registers 4, 5, and 6. However, decoding of the processing target pixel A becomes complicated as it is. Therefore, as shown in the lower part of FIG. 5, the reference pixel data groups are connected one-dimensionally to combine the reference pixel data groups into one register 7. The processing target pixel A can be decoded by referring to the reference pixel data group thus connected. After the decoding of the processing target pixel A is completed, the template is moved rightward by one pixel in preparation for decoding the pixel on the right of A which is a new processing target pixel.
[0008]
A state in which the reference pixel data group one-dimensionally linked from the reference pixel data group extracted to the second register group (registers 4, 5, 6) is obtained in the register 7 by the method described above, that is, the conventional method. Are shown in FIG.
[0009]
FIG. 6 is a diagram for explaining a process of connecting the reference pixel data groups extracted to the second register group one-dimensionally and storing the data in the register 7.
[0010]
In the example shown in FIG. 6A, the register 4 is shifted by 2 bits to the left, the register 5 is shifted by 4 bits to the right, the register 6 is shifted by 12 bits to the right, and the shifted reference pixel data groups are connected. By performing (OR operation), a reference pixel data group one-dimensionally connected to the register 7 is obtained.
[0011]
On the other hand, in the example shown in FIG. 6B, the register 4 is shifted 9 bits to the left, the register 5 is shifted 3 bits to the left, and the register 6 is shifted 5 bits to the right. By linking, a reference pixel data group one-dimensionally linked to the register 7 is obtained.
[0012]
As described above, JBIG (ITU-T T82) encoding is known as encoding and decoding using a template based on reference pixels (for example, see Non-Patent Document 1).
[0013]
If the relative position of the processing target pixel A in the second register group changes as described above, the reference pixel data one-dimensionally connected to the register 7 unless the shift direction of each register and the number of bits to be shifted are changed. You can't get a group. Actually, eight types of shift modes are conceivable depending on the relative position of the processing target pixel A in the second register group.
[0014]
[Non-patent document 1]
Recommendations on Digital Still Image Compression Coding (ITU-T T82) Published January 25, 1994
[0015]
[Problems to be solved by the invention]
As described above, in the conventional method, the shift mode applied to the reference pixel data group extracted to the second register group must be changed depending on the relative position of the processing target pixel A in the second register group. The number of operations required to obtain a group of dimensionally connected reference pixel data increases.
[0016]
The present invention has been made in view of the above problems, and has as its object to perform a smaller number of operations when decoding each encoded pixel using a template based on reference pixels.
[0017]
[Means for Solving the Problems]
In order to achieve the object of the present invention, for example, an image decoding method of the present invention has the following configuration.
[0018]
That is, a first register group for storing decoded pixel data and a second register group different from the first register are provided, and pixel data in an image is stored in a position corresponding to the position of the pixel. An image decoding method performed by an image decoding device that decodes image encoded data obtained by encoding using pixel group data included in an arranged template,
A reading step of fixing the position of the template in the first register group and reading out data of a decoded pixel group included in the template to a second register group;
A linking step of linking the pixel group data read to the second register group one-dimensionally;
A pixel coded by using the data of the pixel group at the time of encoding using the data of the pixel group connected in the connecting step is decoded, and the decoded data of the pixel before decoding in the first register group is decoded. A shifting step of shifting the storage position of each data stored in the first register group by one bit in a predetermined direction after the data of the pixel is overwritten;
It is characterized by having.
[0019]
In order to achieve the object of the present invention, for example, an image decoding device of the present invention has the following configuration.
[0020]
That is, an image decoding apparatus that decodes image data obtained by encoding pixel data in an image using data of a pixel group included in a template arranged at a position corresponding to the position of the pixel. So,
A first group of registers for storing decoded pixel data;
Reading means for fixing a position of the template in the first register group and reading data of a decoded pixel group included in the template into a second register group;
Connecting means for one-dimensionally connecting pixel group data read to the second register group;
A pixel coded by using the data of the pixel group at the time of encoding using the data of the pixel group connected by the connection unit is decoded, and the decoded data of the pixel before decoding in the first register group is decoded. Shift means for shifting the storage position of each data stored in the first register group by one bit in a predetermined direction after being overwritten with the data of the pixel;
It is characterized by having.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail according to preferred embodiments with reference to the accompanying drawings.
[0022]
[First Embodiment]
In this embodiment, a computer using a RISC (Reduced Instruction Set Computer) processor is applied as an image decoding device that decodes an image encoded by a known encoding process using the template by an image decoding process described later. The case will be described.
[0023]
FIG. 7 is a block diagram illustrating a basic configuration of the image decoding device according to the present embodiment. A reduced instruction set computer (RISC) processor 701 controls the entire apparatus using programs and data stored in a RAM 702 and a ROM 705 and executes an image decoding process described later. I do. Further, a first register group 703 and a second register group 704 described later are provided inside.
[0024]
A RAM 702 has a work area necessary for the CPU 701 to perform various types of processing, and also has an area for temporarily storing programs and data loaded from the external storage device 708 and the storage medium drive 709.
[0025]
A first register group 703 temporarily stores decoded data. Details of the first register group 703 will be described later.
[0026]
Reference numeral 704 denotes a second register group which reads out data of a pixel group necessary for decoding a pixel of interest in the encoded image data from the first register group 703 by a method described later and temporarily stores the data. Details of the second register group 704 will be described later.
[0027]
A ROM 705 stores programs and data for controlling the entire apparatus and setting the apparatus.
[0028]
Reference numeral 706 denotes a display unit which is configured by a CRT, a liquid crystal screen, or the like, and can display various information such as images and character information. A GUI or the like for instructing can be displayed.
[0029]
An operation unit 707 includes a keyboard, a mouse, and the like, and can input various instructions to the CPU 701.
[0030]
Reference numeral 708 denotes an external storage device, which is generally constituted by a large-capacity information storage device such as a hard disk drive, in which an OS and programs and data for causing the CPU 701 to execute image decoding processing to be described later are stored. These programs and data are loaded into the RAM 702 according to instructions from the CPU 701 as needed. The external storage device 708 also stores encoded image data to be processed, and is loaded into the RAM 702 according to an instruction from the CPU 701 as needed.
[0031]
Reference numeral 709 denotes a storage medium drive that can read out a program or data stored in a storage medium such as a CD-ROM or a DVD-ROM and output the program or data to the external storage device 708. Note that the programs and data stored in the external storage device 708 may be stored in this storage medium and loaded into the RAM 702 as needed.
[0032]
A bus 710 connects the above-described units.
[0033]
Next, an image decoding process according to the present embodiment performed by the image decoding apparatus having the above configuration will be described. FIG. 1 is a flowchart of the image decoding process. The program according to the flowchart of FIG. 13 is loaded from the external storage device 708 or the storage medium drive 709 to the RAM 702, and the CPU 701 executes the program, so that the image decoding device according to the present embodiment performs an image decoding process described later. Can be.
[0034]
FIG. 2 is a diagram showing the stored contents of the first register group 703 and the second register group 704 when the decoding process is performed according to the flowchart shown in FIG. Hereinafter, the image decoding process according to the present embodiment will be described with reference to FIGS.
[0035]
First, as preparation for decoding, registers 1, 2, and 3 as a first register group 703, registers 4, 5, and 6 as a second register group 704, and reference pixels one-dimensionally connected by processing described later. A register 7 for storing group data is prepared in the CPU 101.
[0036]
When decoding the encoded image data, the second row, the third row, and so on are sequentially decoded from the first row of the image. Therefore, when the m-th row is decoded, n is satisfied for all n that satisfies n <m. The row has already been decoded, and the decoded pixel data is stored in a predetermined area of the RAM 702 or an external storage device 708 (hereinafter, these “memory for storing decoded pixel data” are collectively referred to as “decoded (Referred to as “completed pixel data memory”).
[0037]
Therefore, if the row to be decoded (the row to be processed) is the m-th row, the decoded pixel data of the (m−2) -th row is written from the decoded pixel data memory to the register 1 and the register 2 The decoded pixel data of the (m-1) th row is written from the decoded pixel data memory. The register 3 is used to store the decoded pixel data of the m-th row which is the processing target row.
[0038]
In this embodiment, one byte of decoded pixel data can be stored in the register 3. When one byte of decoded pixel data is written, these are output to the decoded pixel data memory. Thus, each register (1, 2, 3) of the first register group 703 can store decoded pixel data in byte units. In this embodiment, the registers 1 and 2 have 3 bytes and the register 3 has 1 byte. However, the present invention is not limited to this.
[0039]
When the preparation is completed, the CPU 701 determines whether to read the decoded pixel data into the first register group 703 (step S101). In the case of reading, the process proceeds to step S102, and first, one-byte decoded pixel data is read into the first register group 703 (step S102). Specifically, the 1-byte decoded pixel data group of the (m-2) -th row is read into the register 1 and the 1-byte decoded pixel data group of the (m-1) -th row is read into the register 2. .
[0040]
FIG. 2A is a diagram showing the storage contents of the first register group 703 before reading a 1-byte decoded pixel data group into each of the registers 1 and 2 in step S102, and FIG. FIG. 17 is a diagram showing the storage contents of the first register group 703 after reading a 1-byte decoded pixel data group into each of the registers 1 and 2 in step S102.
[0041]
In FIG. 2A, nothing is read in the last 1 byte of the registers 1 and 2, but as shown in FIG. The decoded pixel data of the next one byte in the (m-2) th row and the (m-1) th row is read. In FIGS. 2A and 2B, hatched portions indicate portions included in the template, and the position of the template is assumed to be fixed in the first register group 703 (in other words, The position of the hatched portion in one register group 703 is assumed to be fixed.)
[0042]
Next, the data of the reference pixel group necessary for decoding the pixel at the position indicated by A in FIGS. 2A and 2B, that is, the pixel data of the shaded portion is transferred from the first register group 703 to the second register. The data is read out to the group 704 (step S102).
[0043]
Specifically, a mask is applied to the decoded pixel data group read from the register 1 (the image data group stored in the register 1 is read as 0 except for the reference pixel data group), and one line of the template is stored in the register 4. An eye reference pixel data group (data of the image in the (m−2) th row) is obtained. Further, a mask is applied to the decoded pixel data group read from the register 2 to obtain the reference pixel data group (the image data of the (m−1) th row) in the second row of the template in the register 5. Similarly, a mask is applied to the decoded pixel data group read from the register 3 to obtain a reference pixel data group (image data of the mth row) in the third row of the template in the register 6.
[0044]
FIG. 2C is a diagram showing the storage contents of the second register group 704 in which the reference pixel data group extracted in step S102 is stored. As shown in the drawing, in the first register group 703, only the data of the reference pixel group is extracted to the second register group 704, and 0 is stored in the other groups.
[0045]
Next, in preparation for decoding of a pixel to the right of the position indicated by A, which is a new decoding target, the storage position of each data stored in the first register group 703 is shifted by one bit in the left direction ( (Step S103). FIG. 2D is a diagram showing the storage contents of the first register group 703 after the shift processing in step S103. As shown in the figure, the right end of the registers 1 and 2 has a portion in which the data of the decoded pixel is not stored for one bit, and the right end of the register 3 is A in FIGS. 2 (a) and 2 (b). The data of the pixel at the position indicated by is stored. Naturally, the data stored at the right end of the register 3 (the data stored at the position indicated by A in FIG. 2D) has not been decoded yet, so the value has not been determined.
[0046]
Next, processing for one-dimensionally linking the data of the reference pixel group taken out to the second register group 704 is performed (step S104). Specifically, first, the data stored in each register (4, 5, 6) is shifted by a predetermined direction and by a predetermined number of bits. 2C, the register 4 shifts right by 2 bits, the register 5 shifts right by 8 bits, and the register 6 shifts right by 16 bits.
[0047]
FIG. 2E shows the storage contents of the second register group 704 as a result of the shift as described above. By performing a logical OR operation between the same storage locations in the registers 4, 5, and 6, the storage contents of the registers 4, 5, and 6 are linked and stored in the register 7. FIG. 2F is a diagram showing the contents stored in the register 7. In the figure, among the hatched portions, the first 4 bits are the data of the reference pixel group stored in the register 4, the next 7 bits are the data of the reference pixel group stored in the register 5, and the last 3 bits. The bits are the data of the reference pixel group stored in the register 6, and as a result, the register 7 is one-dimensionally linked data of the reference pixel group stored in each of the registers 4, 5, and 6. Is stored.
[0048]
Conventionally, as described above, when decoding the next pixel, the position of the template has changed in the second register group 704 (in other words, the position of the pixel to be decoded in the second register group 704 is Therefore, the shift direction and the number of bits to be shifted in each register are different each time, and cannot be determined in advance. Therefore, it is necessary to find this each time and the calculation is complicated.
[0049]
However, in the decoding processing according to the present embodiment, since the position of the template in the second register group 704 does not change (in other words, the position of the decoding target pixel in the second register group 704 does not change), the next pixel When decoding is performed, the direction of shifting in each register and the number of bits to be shifted are always the same and can be determined in advance, so that the calculation can be performed more easily, and one-dimensionally at a higher speed. Data of the connected reference pixel group can be obtained.
[0050]
Using the data of the one-dimensionally connected reference pixel group obtained in this manner, the pixel at the position indicated by A is decoded by a known method (step S105), and the shifted The data of the decoded pixel is overwritten at the position indicated by A (the position indicated by A in FIG. 2D in this embodiment) in the one register group 703 (step S106). As a result, the decoded pixel data is stored at the position A in FIG. 2D.
[0051]
Then, it is determined whether or not the decoded data that has not yet been written to the decoded pixel data memory is to be written to the decoded pixel data memory (step S107). For example, when the writing unit is a one-byte unit, it is determined in step S107 whether the decoding process for one byte has been performed. If it is determined that the data is to be written, the process proceeds to step S108, and the decoded data not yet written to the decoded pixel data memory is written to the decoded pixel data memory (step S108).
[0052]
Then, it is determined whether or not all the pixels for one row have been decoded (step S109). If not, the process returns to step S101, and the subsequent processes are repeated.
[0053]
As described above, the image decoding apparatus according to the present embodiment is configured such that when the data of the reference pixel group stored in each of the registers of the second register group 704 are connected one-dimensionally, the shift direction of each register, Since the number of bits can be fixed in advance, there is no need to obtain these in the concatenation process as in the conventional case, and the decoding process can be made simpler. it can.
[0054]
Note that, instead of using the register 7, any of the registers 4, 5, and 6 may be used instead.
[0055]
Further, in the present embodiment, in order to prepare for decoding of the pixel at the position on the right of the pixel at position A, the first register group 703 was first shifted in step S103. After decoding and overwriting the pixel data decoded in step S106, the shift process in step S103 may be performed.
[0056]
[Second embodiment]
In the present embodiment, as the CPU 701, a processor having SIMD (Single Instruction Multiple Data streams) arithmetic capability is applied. Note that the basic configuration of the image decoding apparatus according to the present embodiment is the same as that of FIG. 1, and is the same except that the CPU 701 is a SIMD processor.
[0057]
Specifically, in the decoding process according to the present embodiment, the number of registers to be used is adaptively changed according to the shape of the template and the instruction mounted on the CPU 701. For example, using the template shown in FIG. 4, the CPU 701 has a 64-bit register, and when a shift operation can be applied in 32-bit units, as shown in FIGS. Registers 1 and 2 are prepared as a group 703, and registers 3 and 4 are prepared as a second register group 704. FIG. 3 is a diagram showing the stored contents of the first register group 703 and the second register group 704 according to the present embodiment.
[0058]
Here, "apply a 32-bit shift operation" means that a 64-bit register is composed of two 32-bit registers, and that a shift operation can be applied separately. That is, when the contents of the 64-bit register are (x63, x62,..., X33, x32, x31, x30,..., X1, x0), if a 32-bit shift operation (1-bit left shift) is applied, The contents of the register are (x62, x61, ..., x32, 0, x30, x29, ..., x0, 0).
[0059]
As shown in FIG. 3A, the register 1 is used to store the decoded pixel data in the (m-2) th and (m-1) th rows, and the stored pixel data group is This is a pixel data group read from the pixel data memory. The register 2 is used to store the decoded pixel data group of the row m to be processed, and the stored pixel data group has been decoded but has not been written to the memory yet.
[0060]
Next, the flow of the decoding process according to the present embodiment will be described. However, since the flow is basically the same as that of the first embodiment, only different portions will be described.
[0061]
In step S103, a mask is applied to the decoded pixel data group read from the register 1 to obtain a reference pixel data group in the first and second rows of the template in the register 3. Similarly, a mask is applied to the decoded pixel data group read from the register 2 to obtain the reference pixel data group in the third row of the template in the register 4. Since the decoded pixel data groups of the (m−2) th and (m−1) th rows are stored in the register 1, the data of the reference pixel group for two rows can be read into the register 3 at a time. it can. For this reason, the decoded pixel data groups of the (m−2) th row and the (m−1) th row can be stored in the register 3 with the number of processing times smaller than that of the first embodiment.
[0062]
As shown in FIG. 3B, in the register 1, only the data of the reference pixel group in the (m−2) th row and the (m−1) th row is extracted to the register 3, and other than 0, Is stored.
[0063]
In step S103, in preparation for decoding of a pixel at a position on the right of the position indicated by A, which is a new decoding target, the storage position of each data stored in the first register group 703 is set to 1 in the left direction. Shift by one bit (one pixel). In the present embodiment, since the shift processing can be performed in units of 32 bits, the shift processing can be performed with a smaller number of operations than in the first embodiment.
[0064]
FIG. 3C is a diagram showing the storage contents of the first register group 703 after the shift processing in step S103.
[0065]
As described above, by using the CPU 701 having the SIMD operation capability, the number of operations can be further reduced as compared with the case where the CPU 701 of the first embodiment, that is, the RISC processor is used, and the speed of the entire decoding process can be further increased. Can be.
[0066]
[Third Embodiment]
In the present embodiment, a processor having a special instruction is applied as the CPU 701. Note that the basic configuration of the image decoding apparatus according to the present embodiment is the same as that in FIG. 1, and is the same except that the CPU 701 is a processor having a special instruction.
[0067]
The flow of the decoding process according to the present embodiment will be described. However, since it is basically the same as the first embodiment, only different portions will be described.
[0068]
For example, it is assumed that there is a special instruction that takes out a data group at a predetermined position of a register into another register and shifts the data group of the original register by a specified number. In this case, in step S103, a process of extracting the reference pixel data group from the decoded pixel data group stored in the register 1 of FIG. 2B as in the register 4 of FIG. Since the processing of shifting the decoded pixel data group stored as in the register 1 of d) can be performed by one instruction, the number of operations related to the processing can be reduced as compared with the first embodiment, and the decoding processing can be performed. The whole can be made faster.
[0069]
It is also assumed that there is an instruction for shifting the data stored in a register by a specified number and then performing a logical sum with another register. In this case, in step S104, the reference pixel data group one-dimensionally connected to the register 7 in FIG. 2F from the reference pixel data group stored in the second register group 704 in FIG. Can be reduced in the number of operations when obtaining.
[0070]
When a processor having a special instruction is used as described above, the number of operations related to a process of obtaining one-dimensionally connected reference pixel data groups can be reduced as compared with the first embodiment, and the entire decoding process can be performed. Higher speed can be achieved.
[0071]
In the above embodiment, the template shape shown in FIG. 4 is used, but the above embodiment is not limited to the template having the shape and size shown in FIG.
[0072]
[Other embodiments]
An object of the present invention is to supply a recording medium (or a storage medium) in which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or an apparatus and a computer (or CPU or MPU) of the system or the apparatus. Can be achieved by reading and executing the program code stored in the recording medium. In this case, the program code itself read from the recording medium implements the functions of the above-described embodiment, and the recording medium on which the program code is recorded constitutes the present invention.
[0073]
When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. It goes without saying that a part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.
[0074]
Further, after the program code read from the recording medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function is executed based on the instruction of the program code. It goes without saying that the CPU included in the expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.
[0075]
When the present invention is applied to the recording medium, the recording medium stores program codes corresponding to the flowcharts described above.
[0076]
【The invention's effect】
As described above, according to the present invention, when each encoded pixel is decoded using the template based on the reference pixel, it can be performed with a smaller number of operations.
[Brief description of the drawings]
FIG. 1 is a flowchart of an image decoding process according to a first embodiment of the present invention.
FIG. 2 is a diagram showing storage contents of a first register group 703 and a second register group 704 when decoding processing is performed according to the flowchart shown in FIG.
FIG. 3 is a diagram showing stored contents of a first register group 703 and a second register group 704 according to the second embodiment of the present invention.
FIG. 4A is a diagram illustrating an example of the shape of a template used when decoding image information, and FIG. 4B is a diagram illustrating the use of a template for decoding image information encoded by the encoding method. It is a figure for explaining a method.
FIG. 5 is a diagram illustrating a state in which a one-dimensionally linked reference pixel data group is obtained from a decoded pixel data group read into a first register group.
FIG. 6 is a diagram for explaining a process in which reference pixel data groups taken out by a second register group are connected one-dimensionally and stored in a register 7;
FIG. 7 is a block diagram illustrating a basic configuration of an image decoding device according to the first embodiment of the present invention.

Claims (5)

A first register group that stores decoded pixel data; and a second register group that is different from the first register. Pixel data in an image is arranged at a position corresponding to the position of the pixel. An image decoding method performed by an image decoding device that decodes image encoded data obtained by encoding using data of a pixel group included in the template,
A reading step of fixing the position of the template in the first register group and reading out data of a decoded pixel group included in the template to a second register group;
A linking step of linking the pixel group data read to the second register group one-dimensionally;
A pixel coded by using the data of the pixel group at the time of encoding using the data of the pixel group connected in the connecting step is decoded, and the decoded data of the pixel before decoding in the first register group is decoded. Shifting the storage position of each data stored in the first register group by one bit in a predetermined direction after overwriting the data of the pixel. In the reading step, among the decoded pixel data for each row stored in the first register group, decoded pixel data of a row necessary for decoding a pixel of interest to be decoded is stored in the second register group. Read line by line
2. The image decoding method according to claim 1, wherein, in the connecting step, the pixel data of each row read into the second register group is connected for each row. An image decoding device for decoding image encoded data obtained by encoding pixel data in an image using data of a pixel group included in a template arranged at a position corresponding to the position of the pixel. ,
A first group of registers for storing decoded pixel data;
Reading means for fixing a position of the template in the first register group and reading data of a decoded pixel group included in the template into a second register group;
Connecting means for one-dimensionally connecting pixel group data read to the second register group;
A pixel coded by using the data of the pixel group at the time of encoding using the data of the pixel group connected by the connection unit is decoded, and the decoded data of the pixel before decoding in the first register group is decoded. An image decoding apparatus comprising: a shift unit that shifts a storage position of each data stored in the first register group by one bit in a predetermined direction after being overwritten with data of the pixel. A program for causing a computer to execute the image decoding method according to claim 1. A computer-readable storage medium storing the program according to claim 4.

Images