JP2004335773A - Sub-mount substrate for semiconductor laser chip, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce costs for manufacturing a ceramic sub-mount substrate 3 obtained by respectively forming electrode films 4 and 5 to a semiconductor laser chip 1 on its front surface and an electrode film 6 for die bonding to a heat sink 2 on its rear surface. <P>SOLUTION: The substrate has a double-layer laminated structure consisting of non-electrolyzed NiP plated layers 4a, 5a, and 6a obtained by directly forming the electrode films 4 and 5 on the front surface of the sub-mount substrate 3 and the electrode film 6 on the rear surface as a base on the sub-mount substrate, and electroplating layers 4b, 5b and 6b plated with gold overlapped thereon. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a submount substrate used during die bonding of a semiconductor laser chip to a heat sink, and a method of manufacturing the same.
[0002]
[Prior art]
Generally, when a semiconductor laser chip is die-bonded to a heat sink, the semiconductor laser chip is die-bonded to a submount substrate, and then the submount substrate is die-bonded to the heat sink, or After the submount substrate is die-bonded to the heat sink, the semiconductor laser chip is die-bonded to the submount substrate.
[0003]
In this case, on the upper surface of the submount substrate, an electrode film made of gold for die-bonding the semiconductor laser chip and an electrode film made of gold for energizing the semiconductor laser chip are formed on the lower surface of the submount substrate. Form an electrode film of gold for die bonding the submount substrate to the heat sink.
[0004]
According to Patent Document 1 as a prior art, the submount substrate is made of a ceramic such as aluminum nitride ceramic (AlN) having excellent heat resistance and thermal conductivity, and titanium (as a base) is provided on both upper and lower surfaces thereof. A thin film of Ti) and platinum (Pt) is formed by sputtering or vacuum evaporation, and a thin film of gold (Au) is formed on the thin film by sputtering or vacuum evaporation. A die bonding electrode film and a current-carrying electrode having a three-layer structure of titanium, platinum and gold are formed, and an electrode film for die bonding having a three-layer structure of titanium, platinum and gold is formed on the lower surface of the submount substrate. It is described.
[0005]
[Patent Document 1]
JP-A-5-48213
[Problems to be solved by the invention]
However, as in this prior art, an electrode film having a three-layer structure of titanium, platinum and gold is formed on the upper and lower surfaces of the submount substrate by sputtering or vacuum deposition.
▲ 1 ▼. Sputtering or vacuum deposition of titanium, platinum, and gold must be performed separately on both the upper surface and the lower surface of the submount substrate. In other words, sputtering or vacuum deposition is performed six times in total. It has to be done over time, the process is complicated,
▲ 2 ▼. In order to make the surface of each electrode film gold, expensive platinum must be used as its base,
(3). At the time of sputtering or vacuum deposition of the platinum and gold, these expensive platinum and gold will considerably adhere to unnecessary portions such as the inner surface of the container where the sputtering or vacuum deposition is performed, so that platinum and gold can be used. Waste increases,
Therefore, there is a problem that the manufacturing cost is significantly increased.
[0007]
An object of the present invention is to provide a submount substrate that solves this problem and a method of manufacturing the same.
[0008]
[Means for Solving the Problems]
In order to achieve this technical object, the submount substrate of the present invention has the following features.
`` In a ceramic submount substrate formed by forming an electrode film for a semiconductor laser chip on the front surface and an electrode film for die bonding to a heat sink on the back surface,
Two layers of an electroless NiP plating layer formed directly on the submount substrate as an underlayer of the electrode film on the front surface and the electrode film on the rear surface of the submount substrate, and an electroplating layer of gold formed thereon. Structured. "
It is characterized by:
[0009]
Further, the submount substrate of the present invention has the following features.
In the above-mentioned claim 1, an electroplating layer of tin is formed on a portion of the electrode film on the surface of the submount substrate on which the semiconductor laser chip is die-bonded so as to overlap the electroplating layer of gold. did."
It is characterized by:
[0010]
Next, the manufacturing method of the present invention, as described in claim 3,
"Electroless NiP plating on the front and back surfaces of the submount substrate by subjecting the submount substrate to an electroless NiP plating process after the process of subjecting the surface and the back surface to catalytic activation. A step of forming a layer, and a step of applying gold electroplating to the submount substrate to form a gold electroplated layer on each of the electroless NiP plated layers. "
It is characterized by:
[0011]
Further, according to the production method of the present invention,
"Electroless NiP plating on the front and back surfaces of the submount substrate by subjecting the submount substrate to an electroless NiP plating process after the process of subjecting the surface and the back surface to catalytic activation. Forming a layer, and patterning the electroless NiP plating layer on the surface of the submount substrate so as to divide the semiconductor laser chip into a portion to be die-bonded and another portion, and then the A step of forming a gold electroplating layer on each of the electroless NiP plating layers by performing gold electroplating on the submount substrate. "
It is characterized by:
[0012]
Moreover, the manufacturing method of the present invention, as described in claim 5,
"In the method according to claim 3 or 4, before the step of performing a catalyst activation treatment on the submount substrate, the step of performing an etching treatment on the submount substrate to roughen the front and rear surfaces thereof. I have it. "
It is characterized by:
[0013]
In addition to this, the manufacturing method of the present invention as described in claim 6,
"In any one of claims 3 to 5, after the step of performing the electroplating with gold, a semiconductor laser chip is die-bonded to the gold electroplated layer on the surface of the submount substrate. A step of forming a tin electroplating layer on the gold electroplating layer by subjecting the portion to a tin electroplating process. "
It is characterized by:
[0014]
[Action and Effect of the Invention]
As described above, the electrode film on the front surface of the ceramic submount substrate and the electrode film on the back surface are formed directly on the submount substrate by an electroless NiP plating layer and an electroplating by gold formed on the electroless NiP plating layer. With the two-layer structure, the electrode film on the front surface and the electrode film on the back surface can be simultaneously formed by one electroless NiP plating process and one gold electroplating process. In addition, unlike the prior art, in addition to being able to form a surface made of gold without using expensive platinum, the use of gold is less wasteful due to electroplating of gold, so that manufacturing costs are significantly reduced. It has the effect of being able to reduce.
[0015]
Further, an electroplating layer of tin is formed on a portion of the electrode film on the surface of the submount substrate on which the semiconductor laser chip is die-bonded, by superposing the electroplating layer of gold on the portion, thereby forming the semiconductor laser chip. In the case of die bonding with a hot-melt type die bonding material such as solder or the like, since they are alloyed with each other due to the presence of tin, there is an advantage that the ease, reliability and strength of the die bonding can be improved.
[0016]
In particular, as described in claim 4, after a step of patterning the electroless NiP plating layer on the surface of the submount substrate so that the electroless NiP plating layer is divided into a part where the semiconductor laser chip is die-bonded and another part, By performing electroplating of gold on the submount substrate, a gold electroplating layer can be formed only on each of the electroless NiP plating layers. Of these, the formation of a gold electroplating layer in portions other than the above-described electroless NiP plating layers can be reliably avoided, so that the amount of gold used can be further reduced.
[0017]
In addition, prior to the step of performing a catalyst activation process on the submount substrate, the submount substrate is subjected to an etching process for roughening the front and back surfaces thereof, whereby each of the electroless NiP plating layers is formed. The adhesion strength to the submount substrate can be improved.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0019]
FIGS. 1 and 2 show a state in which a semiconductor laser chip 1 is die-bonded to a heat sink 2 using a submount substrate 3.
[0020]
That is, the semiconductor laser chip 1 is die-bonded to the submount substrate 3 with a heat-melting die bonding material (not shown) such as solder, and this submount substrate 3 is attached to the heat sink 2. The submount substrate 3 is die-bonded to the heat sink 2 using a heat-melting type die bonding material (not shown) such as solder. ), And the semiconductor laser chip 1 is die-bonded to the submount substrate 3 with a heat-melting die bonding material (not shown) such as solder.
[0021]
In this case, the submount substrate 3 is made of a ceramic such as aluminum nitride ceramic (AlN), and the submount substrate 3 has a surface as shown in FIGS. 1, 2, 3 and 4. A pair of electrode films 4 and 5 separated from each other by a trimming groove 7 are formed on the (upper surface), and an electrode film 6 for die bonding to the heat sink 2 is formed on the back surface (lower surface). One of the electrode films 4 and 5 is configured such that the semiconductor laser chip 1 is die-bonded to one of the electrode films 4, and the other electrode film 5 is configured to energize the semiconductor laser chip 1.
[0022]
In FIGS. 1 and 2, reference numeral 8 denotes a metal wire formed by wire bonding for electrically connecting the semiconductor laser chip 1 and the current-carrying electrode film 5. Metal wires 9 and 10 for energizing the semiconductor laser chip 1 are connected to the two electrode films 4 and 5 on the upper surface of the submount substrate 3 by wire bonding.
[0023]
Then, the electrode films 4 and 5 on the front surface (upper surface) of the submount substrate 3 and the electrode film 6 on the back surface (lower surface) are directly attached to the submount substrate 3 as shown in FIGS. It has a two-layer structure of an electroless NiP plating layer 4a, 5a, 6a formed as a base and a gold electroplating layer 4b, 5b, 6b formed thereon.
[0024]
On the other hand, a tin electroplating layer 11 is formed on a part of the one electrode film 4 on the surface (upper surface) of the submount substrate 3 so as to overlap with the gold electroplating layer 4b. The semiconductor laser chip 1 is configured to be die-bonded to the layer 11 with a heat-melting die bonding material (not shown) such as solder.
[0025]
Next, FIGS. 5 to 13 show a method of manufacturing the submount substrate 3 having the above-described configuration.
[0026]
This manufacturing method, as described below,
▲ 1 ▼. As shown in FIG. 5, a material substrate A formed by integrating a large number of the submount substrates 3 in the vertical and horizontal directions with a vertical cutting line A1 and a horizontal cutting line A2 interposed therebetween is used as an aluminum nitride substrate. A step of preparing a ceramic (AlN) or alumina ceramic.
[0027]
A margin portion is provided integrally around the material substrate A.
[0028]
▲ 2 ▼. Next, the material substrate A is immersed in an aqueous solution for degreasing for an appropriate period of time, then pulled up, washed with water, and dried to perform a degreasing treatment on the front and rear surfaces thereof.
[0029]
(3). Next, the material substrate A is immersed in an alkaline aqueous solution such as an aqueous solution of caustic soda for an appropriate period of time, or after applying ultrasonic waves in this immersed state, by withdrawing and washing and drying, the front and rear surfaces thereof are A step of performing an etching process for roughening.
[0030]
▲ 4 ▼. Next, the material substrate A is, for example, immersed in a Pb-Sn catalyst solution for an appropriate period of time, and then withdrawn and washed with water. A step of performing a treatment for activating the catalyst.
[0031]
▲ 5 ▼. Next, the material substrate A was immersed in an electroless NiP plating bath solution for an appropriate period of time, then lifted, washed with water, and dried to perform an electroless NiP plating process, as shown in FIG. An electroless NiP plating layer A3 having an appropriate thickness (this becomes the electroless NiP plating layers 4a and 5a as a base among the two electrode films 4 and 5 on the surface of the submount substrate 3) is formed on the back surface thereof. A step of simultaneously forming an electroless NiP plating layer A4 having an appropriate thickness (this becomes an electroless NiP plating layer 6a as a base of the die bonding electrode film 6 on the back surface of the submount substrate 3).
[0032]
▲ 6 ▼. Next, as shown in FIGS. 8 and 9, trimming grooves 7 are engraved at the positions of the submount substrates 3 in the electroless NiP plating layer A3 on the surface of the material substrate A, so that the electroless The NiP plating layer A3 is divided into an electroless NiP plating layer 4a as a base on the die bonding electrode film 4 on the upper surface of each of the submount substrates 3 and an electroless NiP plating layer 5a as a base on the energizing electrode film 5. A step of performing patterning for dividing.
[0033]
In this patterning step, a resist film for covering each of the electroless NiP plating layer A3 on the front surface of the material substrate A and the electroless NiP plating layer A4 on the back surface is formed. The pattern in the trimming groove 7 is exposed and baked with respect to the resist film on the surface of the film, and the portion corresponding to the trimming groove 7 in the resist film is removed by a developing process. Is immersed in an etching solution, the trimming groove 7 is formed by etching, and the resist film on the front surface and the resist film on the rear surface are peeled and removed by a so-called photolithography method.
[0034]
▲ 7 ▼. Next, the material substrate A is immersed in a gold plating solution, and in this state, the electroless NiP plating layers 4a and 5a on the front surface and the electroless NiP plating layer A4 on the back surface (this is the back surface of the submount substrate 3). Is formed by applying an electric current between the plating solution and the electroless NiP plating layer 6a as a base of the die bonding electrode film 6 in FIG. At the same time, the gold electroplating layers 4b and 5b are formed on the electroless NiP plating layers 4a and 5a on the front surface, and the gold electroplating layer 6b is formed on the electroless NiP plating layer 6a (A4) on the back surface. Forming the electrode films 4 and 5 on the front surface and the electrode film 6 on the rear surface.
[0035]
<8>. As shown in FIGS. 11 and 12, by subjecting the entire material substrate A to a tin electroplating process, a portion of one of the electrode films 4 on the surface of the material substrate A where the semiconductor laser chip 1 is die-bonded is provided. Forming a tin electroplating layer 11 on the gold electroplating layer 4a.
[0036]
The step of forming the tin electroplating layer 11 includes forming a resist film covering the entire front surface and the entire rear surface of the material substrate A, and forming a resist film on the front surface of the two resist films. On the other hand, the pattern of the tin electroplating layer 11 is exposed and baked, and then a portion corresponding to the tin electroplating layer 11 of the resist film is removed by a development process. Is immersed in a plating solution, and in this state, an electroplating process of applying a current between the electrode film 4 on the surface and the plating solution is performed.
[0037]
▲ 9 ▼. Then, as shown in FIG. 13, the material substrate A is cut by using the high-speed rotating tying cutters A5 and A6 at the vertical cutting line A1 and the horizontal cutting line A2 of the material substrate A. And a step of dividing each of the plurality of submount substrates 3.
Through these steps, the submount substrate 3 having the configuration shown in FIGS. 3 and 4 can be manufactured.
[0038]
Note that the gold electroplating process in (7) may be performed before the patterning process in (6). However, the gold electroplating process in (7) is performed in (6). If it is performed after the patterning step, it is possible to avoid that the gold electroplating layer is formed in a portion other than the electroless NiP plating layers 4a, 5a and 6a during the gold electroplating process. You can save money on gold.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a state in which a semiconductor laser chip is die-bonded to a heat sink using a submount substrate.
FIG. 2 is an enlarged sectional view taken along line II-II of FIG.
FIG. 3 is a perspective view showing FIG.
FIG. 4 is an enlarged sectional view taken along line IV-IV of FIG. 3;
FIG. 5 is a perspective view showing a material substrate used for manufacturing the submount substrate.
FIG. 6 is an enlarged sectional view taken along line VI-VI of FIG. 5;
FIG. 7 is an enlarged sectional view showing a state in which an electroless NiP plating layer is formed on the front and back surfaces of the material substrate.
FIG. 8 is a perspective view showing a state where the surface of the material substrate is patterned.
FIG. 9 is an enlarged cross-sectional view taken along IX-IX in FIG. 8;
FIG. 10 is an enlarged sectional view showing a state in which a gold electroplating layer is formed on the front and back surfaces of the material substrate.
FIG. 11 is a perspective view showing a state in which a tin electroplating layer is formed on the front and back surfaces of the material substrate.
FIG. 12 is an enlarged sectional view taken along the line XII-XII of FIG. 11;
FIG. 13 is a perspective view showing a state in which the material substrate is divided into a number of submount substrates.
[Explanation of symbols]
Reference Signs List 1 semiconductor laser chip 2 heat sink 3 submount substrate 4, 5 electrode film 4a, 5a on submount substrate surface Electroless NiP plating layer 4b, 5b gold electroplating layer 6 electrode film 6a on back surface of submount substrate, electroless NiP Plating layer 6b Gold electroplating layer 7 Trimming groove 11 Tin electroplating layer A Material substrate A1, A2 Vertical and horizontal cutting lines A3, A4 Electroless NiP plating layers A5, A6 Dicing cutter

Claims (6)

An electrode film for the semiconductor laser chip on the front surface, and a die-bonding electrode film for the heat sink formed on the back surface of the ceramic submount substrate.
A two-layer stack of an electroless NiP plating layer formed directly on the submount substrate as an underlayer with the electrode film on the front surface and the electrode film on the back surface of the submount substrate, and an electroplating layer of gold formed thereon. A submount substrate for a semiconductor laser chip having a structure. 2. The electroplating layer made of tin is formed on the electrode film on the surface of the submount substrate in a portion where the semiconductor laser chip is die-bonded to the electroplating layer made of gold. A submount substrate for a semiconductor laser chip. A step of subjecting the ceramic submount substrate to a process of activating the front and back surfaces of the submount substrate with a catalyst, and then applying an electroless NiP plating process to the submount substrate to form an electroless NiP plating layer And a step of forming a gold electroplating layer on each of the electroless NiP plating layers by subjecting the submount substrate to gold electroplating. A method for manufacturing a submount substrate for a laser chip. A step of subjecting the ceramic submount substrate to a process of activating the front and back surfaces of the submount substrate with a catalyst, and then applying an electroless NiP plating process to the submount substrate to form an electroless NiP plating layer And a step of patterning the electroless NiP plating layer on the surface of the submount substrate so as to divide the semiconductor laser chip into a portion for die bonding and a portion other than the portion. Manufacturing a submount substrate for a semiconductor laser chip, comprising a step of forming a gold electroplating layer on each of the electroless NiP plating layers by applying gold electroplating to the mounting substrate. Method. 5. The method according to claim 3, further comprising, prior to the step of performing a catalyst activation process on the submount substrate, performing an etching process on the submount substrate to roughen the front and rear surfaces thereof. A method of manufacturing a submount substrate for a semiconductor laser chip. 6. A portion of the gold electroplated layer on the surface of the submount substrate, to which a semiconductor laser chip is die-bonded, after the step of performing the electroplating with gold according to any one of claims 3 to 5, And forming a tin electroplating layer on the gold electroplating layer by performing a tin electroplating process.

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