JP2004335771A - Diffusion wafer and method for manufacturing the same - Google Patents
Diffusion wafer and method for manufacturing the same Download PDFInfo
- Publication number
- JP2004335771A JP2004335771A JP2003130217A JP2003130217A JP2004335771A JP 2004335771 A JP2004335771 A JP 2004335771A JP 2003130217 A JP2003130217 A JP 2003130217A JP 2003130217 A JP2003130217 A JP 2003130217A JP 2004335771 A JP2004335771 A JP 2004335771A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- diffusion
- layer
- dislocation density
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
【0001】
【発明の属する技術分野】
本発明は、トランジスタやダイオード、MOSFET等のディスクリートデバイス(個別素子)の製造に用いられ、デバイス形成面の転位密度を高レベルとして高周波特性を良好にし得る拡散ウェーハ及びその製造方法に関する。
【0002】
【従来の技術】
従来、この種の拡散ウェーハとしては、シリコンウェーハの一方の面に高濃度の不純物が拡散された拡散層を有し、他方の面に表面が鏡面で不純物が拡散されていない非拡散層を有する2層構造からなり、デバイス形成面となる非拡散層の転位密度が5000〜20000個/cm2と高レベルで、非拡散層の表面から所定の表層付近(所定の深さ)まで転位密度が漸減し、かつ、所定の表層付近から拡散層との界面までの転位密度が漸増する転位密度分布を有していると共に、表面から所定の表層付近までの転位密度の勾配と所定の表層付近から拡散層との界面までの転位密度の勾配が等しいものが開示されている(例えば、特許文献1参照)。
【0003】
【特許文献1】
特許第2888294号公報
【0004】
この拡散ウェーハは、両面にラッピング加工を均等に施し、ボートに装填したシリコンウェーハに、例えば、常圧下、1200℃の温度でPOCl3(オキソ塩化リン)を用いてデポジションを行い、更に、より高温で、例えば、1280℃でドライブイン拡散し、シリコンウェーハの両面に高濃度の拡散層を中間に不純物が拡散されていない非拡散層を介在させて形成した後、一方の面の拡散層及び非拡散層の1/2厚未満を研削除去し、露出した非拡散層の表面を鏡面に仕上げることにより製造されるものである。
【0005】
【発明が解決しようとする課題】
しかし、従来の拡散ウェーハ及びその製造方法では、非拡散層の表面から所定の表層付近までの転位密度の勾配と所定の表層付近から拡散層との界面までの転位密度の勾配が等しいため、表面の転位密度の高レベル化を行うには、素材としての拡散前のシリコンウェーハの厚みを大きくしなければならず、原材料の増大を招来している。
又、非拡散層の表面における転位密度の高レベル化に併せて、非拡散層の厚さを所定の規格内にすることが困難となる不具合もある。
【0006】
そこで、本発明は、原材料の低減が可能であると共に、非拡散層の表面における転位密度の高レベル化と非拡散層の厚さの規格内化を図り得る拡散ウェーハ及びその製造方法を提供することを課題とする。
【0007】
【課題を解決するための手段】
前記課題を解決するため、本発明の拡散ウェーハは、シリコンウェーハの一方の面に高濃度の不純物が拡散された拡散層を有し、他方の面に不純物が拡散されていない非拡散層を有する2層構造からなり、上記非拡散層の表面から所定の表層付近まで転位密度が漸減し、かつ、所定の表層付近から拡散層との界面まで転位密度が漸増する転位密度分布を有している拡散ウェーハにおいて、前記非拡散層の表面から所定の表層付近までの転位密度の勾配を所定の表層付近から拡散層との界面までの転位密度の勾配より大きくしたことを特徴とする。
【0008】
一方、拡散ウェーハの製造方法は、ラッピング加工が施されたシリコンウェーハの両面に高濃度の不純物を拡散させ、一方の拡散層を研削除去し、露出した非拡散層の表面を鏡面仕上げする拡散ウェーハの製造方法において、前記研削除去される側の面のラッピング加工によるダメージを他の面のラッピング加工によるダメージより小さくしておくことを特徴とする。
【0009】
【作用】
本発明の拡散ウェーハにおいては、非拡散層の表面における転位密度が、非拡散層の厚さを同等にした従来のものに比べて格段に高くなる。
【0010】
所定の表層付近から拡散層との界面までの転位密度の勾配より大きくした非拡散層の表面から所定の表層付近までの転位密度の勾配は、非拡散層に求められる表面の転位密度と厚さの規格に対応させて変化させるようにすることが望ましい。
【0011】
一方、拡散ウェーハの製造方法においては、ラッピング加工によるダメージ(マイクロクラックを有する破砕層深さ)を小さくしておいた側が大きくしておいた側よりも、拡散層形成時における不純物の拡散に伴うひずみ応力やウェーハ外周部と中心部との温度差に伴う熱応力等の吸収緩和能力が小さくなり、又、拡散層形成後の非拡散層における転位密度分布の極小値が、非拡散層の厚さの中心よりもダメージを大きくしておいた側にずれる。
【0012】
ラッピング加工によるダメージを小さくしておく側のダメージの程度は、非拡散層の厚さの規格に対応させて変化させるようにすることが望ましい。
【0013】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して説明する。
図1、図2は本発明に係る拡散ウェーハの実施の形態の一例を示す断面図、図1の拡散ウェーハにおける非拡散層の転位密度分布図である。
【0014】
この拡散ウェーハは、シリコンウェーハの一方(図1においては下方)の面に高濃度の不純物(代表的なものとして、n型はP(リン)、P型はB(ボロン)が挙げられる)が拡散された拡散層1を有し、他方(図1においては上方)の面に表面Sが鏡面で不純物が拡散されていない非拡散層2を有する2層構造からなる。
そして、デバイス形成面となる非拡散層2の表面の転位密度は、デバイス工程でのゲッタリング能力及び最終的に素子となった時の高周波特性を良好にすべく、5000〜20000個/cm2と高レベルであり、かつ、非拡散層2は、その表面Sから所定の表層付近(例えば、表面から10〜30μmの深さ)NSまで転位密度が漸減し、かつ、所定の表層付近NSから拡散層1との界面Bまで転位密度が漸増する転位密度分布を有しており、非拡散層2の表面Sから所定の表層付近NSまでの転位密度の勾配は、所定の表層付近NSから拡散層1との界面Bまでの転位密度の勾配より大きくされている。
なお、非拡散層2の表面Sから所定の表層付近NSまでの転位密度の勾配は、非拡散層2に求められる表面Sの転位密度と厚さの規格に対応させて変化させられるものである。
【0015】
上述した拡散ウェーハを製造するには、先ず、図3(a)に示すように、素材となる所要厚さのシリコンウェーハWの両面に比較的粗い砥粒を用いてラッピング加工を施し、両面をダメージの大きい面DLとした。
次に、図3(b)に示すように、シリコンウェーハWの一方(図3(b)においては下方)の面を、接着テープ(図示せず)を介し保護パッド3により覆った後、他方(図3(b)においては上方)の面に比較的細かい砥粒を用いてラッピング加工を施し、他方の面をダメージの小さい面DSとした。
次いで、保護パット3を取り外し、図3(c)に示すように、両面のダメージを変えたシリコンウェーハWの両面にデポジション及びドライブイン拡散処理を順次施して高濃度の不純物を拡散させ、不純物が拡散されていない非拡散層2を中間に介在させて拡散層1を形成した後、図3(d)に示すように、ダメージの小さい面DS側の拡散層1及び非拡散層2を研削除去し、露出した非拡散層2の表面を鏡面仕上げし、鏡面MSとして拡散ウェーハを得た。
【0016】
ここで、非拡散層の転位密度分布を測定するため、先ず、CZ法による口径125mmのn型シリコンウェーハの両面に、#800の砥粒によるラッピング加工を取代、片面15μmずつ、計30μm施した後、一方の面に厚さ1.5mm、口径125mmのフッ素樹脂製の保護パッドを、接着テープを介し貼り付けて一方の面を保護し、しかる後に、他方の面に、#1200の砥粒によるラッピング加工を取代10μm施して両面のダメージを変えたn型シリコンウェーハを得た。
次に、両面のダメージを変えたn型シリコンウェーハを電気炉に装入し、炉内温度を1200℃に保持すると共に、炉内に酸素、窒素及びPOCl3ガスを導入して180分間熱処理し、n型シリコンウェーハの両面にデポ拡散層を形成させた後、このn型シリコンウェーハをアルゴンガス雰囲気において1290℃の温度で300時間熱処理し、不純物をさらに深くまで拡散させた拡散層を形成し、しかる後に、ダメージの小さい面側の拡散層を研削除去し、非拡散層を露出させた。
次いで、取代20μm程度、研削面を研磨し、研削でのダメージを完全に除去して、拡散ウェーハとした。その後、これらの拡散ウェーハに対して、深さ方向に20μm毎に表面を研磨してそれぞれサンプルを作成し、拡散ウェーハ表面から拡散層界面までの転位密度の変化の傾向をアングルラップによってサンプルを作成し転位密度を評価した。結果を図4に示す。
【0017】
図4から分かるように、非拡散層の転位密度分布は、ダメージの小さい面DS側の界面B1から非拡散層の厚さの中心Cを越える位置まで転位密度が漸減し、ある極小値を経た後、ダメージの大きい面DL側の界面B2に向って転位密度が漸増し、かつ、極小値を境にしてダメージの小さい面DS側の転位密度の勾配が、ダメージの大きい面DL側の転位密度の勾配より大きくなっている。
なお、上述した傾向は、拡散前のシリコンウェーハの電気抵抗、酸素濃度、タイプ、表面のダメージの大小、拡散条件、拡散層の厚さ等によって異なるため、予めそれぞれの傾向を把握しておくことが望ましい。
【0018】
【発明の効果】
以上説明したように、本発明の拡散ウェーハ及びその製造方法によれば、非拡散層の表面における転位密度が、非拡散層の厚さを同等にした従来のものに比べて格段に高くなるので、原材料の低減ができる。
又、非拡散層の表面から所定の表層付近までの転位密度の勾配を変えることにより、非拡散層に求められる表面の転位密度と厚さの規格の両方を満たすことができる。
【図面の簡単な説明】
【図1】本発明に係る拡散ウェーハの実施の形態の一例を示す断面図である。
【図2】図1の拡散ウェーハにおける拡散層の転位密度分布図である。
【図3(a)〜(d)】図3は本発明に係わる拡散ウェーハの製造方法の実施の形態の一例を示すもので、(a)は第1工程の説明図、(b)は第2工程の説明図、(C)は第3工程の説明図、(d)は最終工程の説明図である。
【図4】図1の拡散ウェーハの具体例における非拡散層の転位密度分布図である。
【符号の説明】
1 拡散層
2 非拡散層
S 表面
NS 所定の表層付近
B 界面
W シリコンウェーハ
DL ダメージの大きい面
DS ダメージの小さい面
MS 鏡面[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a diffusion wafer used in the manufacture of discrete devices (individual elements) such as transistors, diodes, and MOSFETs, and capable of improving the high-frequency characteristics by setting the dislocation density of a device formation surface to a high level, and a method of manufacturing the same.
[0002]
[Prior art]
Conventionally, as a diffusion wafer of this type, a silicon wafer has a diffusion layer in which high-concentration impurities are diffused on one surface, and a non-diffusion layer in which the surface is mirror-finished and the impurities are not diffused on the other surface. The non-diffusion layer, which has a two-layer structure, has a high dislocation density of 5,000 to 20,000 / cm 2, and has a dislocation density from the surface of the non-diffusion layer to the vicinity of a predetermined surface layer (a predetermined depth). It has a dislocation density distribution that gradually decreases and the dislocation density from the vicinity of the predetermined surface layer to the interface with the diffusion layer gradually increases, and the dislocation density gradient from the surface to the vicinity of the predetermined surface layer and the vicinity of the predetermined surface layer Japanese Patent Application Laid-Open Publication No. HEI 11-163556 discloses a technique in which the gradient of the dislocation density up to the interface with the diffusion layer is equal.
[0003]
[Patent Document 1]
Japanese Patent No. 2888294 [0004]
This diffusion wafer is subjected to lapping evenly on both sides, and the silicon wafer loaded in the boat is deposited using, for example, POCl 3 (phosphorous oxychloride) at a temperature of 1200 ° C. under normal pressure. At a high temperature, for example, drive-in diffusion at 1280 ° C., and after forming a high concentration diffusion layer on both sides of the silicon wafer with a non-diffusion layer in which impurities are not diffused therebetween, the diffusion layer on one side and It is manufactured by grinding and removing less than half the thickness of the non-diffusion layer and finishing the surface of the exposed non-diffusion layer to a mirror surface.
[0005]
[Problems to be solved by the invention]
However, in the conventional diffusion wafer and its manufacturing method, the dislocation density gradient from the surface of the non-diffusion layer to the vicinity of a predetermined surface layer is equal to the dislocation density gradient from the vicinity of the predetermined surface layer to the interface with the diffusion layer. In order to raise the dislocation density to a higher level, the thickness of the silicon wafer before diffusion as a material must be increased, which leads to an increase in raw materials.
There is also a problem that it is difficult to keep the thickness of the non-diffusion layer within a predetermined standard in accordance with the increase in the level of dislocation density on the surface of the non-diffusion layer.
[0006]
Therefore, the present invention provides a diffusion wafer and a method for manufacturing the same, which can reduce the amount of raw materials, increase the dislocation density on the surface of the non-diffusion layer, and standardize the thickness of the non-diffusion layer. That is the task.
[0007]
[Means for Solving the Problems]
In order to solve the above problem, the diffusion wafer of the present invention has a diffusion layer in which high-concentration impurities are diffused on one surface of a silicon wafer, and a non-diffusion layer in which impurities are not diffused on the other surface. It has a two-layer structure, and has a dislocation density distribution in which the dislocation density gradually decreases from the surface of the non-diffusion layer to the vicinity of a predetermined surface layer, and the dislocation density gradually increases from the vicinity of the predetermined surface layer to the interface with the diffusion layer. In the diffusion wafer, the gradient of the dislocation density from the surface of the non-diffusion layer to the vicinity of a predetermined surface layer is larger than the gradient of the dislocation density from the vicinity of the predetermined surface layer to the interface with the diffusion layer.
[0008]
On the other hand, a method for manufacturing a diffusion wafer is to diffuse a high-concentration impurity on both sides of a silicon wafer subjected to a lapping process, grind and remove one diffusion layer, and mirror-finish the surface of an exposed non-diffusion layer. In the method, the damage caused by the lapping of the surface to be ground and removed is made smaller than the damage caused by the lapping of the other surface.
[0009]
[Action]
In the diffusion wafer of the present invention, the dislocation density on the surface of the non-diffusion layer is much higher than that of a conventional wafer in which the thickness of the non-diffusion layer is equal.
[0010]
The gradient of the dislocation density from the surface of the non-diffusion layer to the vicinity of the predetermined surface layer, which is larger than the gradient of the dislocation density from the vicinity of the predetermined surface layer to the interface with the diffusion layer, is the dislocation density and thickness of the surface required for the non-diffusion layer. It is desirable to change it in accordance with the standard.
[0011]
On the other hand, in the manufacturing method of the diffusion wafer, the side where the damage due to the lapping process (the depth of the crushed layer having the microcrack) is reduced is larger than the side where the damage is increased due to the diffusion of impurities during the formation of the diffusion layer. The ability to absorb and relax strain stress and thermal stress due to the temperature difference between the wafer outer peripheral part and the central part becomes smaller, and the minimum value of the dislocation density distribution in the non-diffusion layer after the formation of the diffusion layer is reduced by the thickness of the non-diffusion layer. It shifts to the side where the damage was larger than the center of the sword.
[0012]
It is desirable to change the degree of damage on the side where the damage due to the lapping process is kept small in accordance with the standard of the thickness of the non-diffusion layer.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 and 2 are cross-sectional views showing an example of the embodiment of the diffusion wafer according to the present invention, and a dislocation density distribution diagram of a non-diffusion layer in the diffusion wafer of FIG.
[0014]
This diffusion wafer has a high concentration of impurities (typically, P (phosphorus) for n-type and B (boron) for P-type) on one (lower in FIG. 1) surface of the silicon wafer. It has a two-layer structure having a diffused layer 1 diffused and a
The dislocation density on the surface of the
Incidentally, the gradient of dislocation density from the surface S of the
[0015]
In order to manufacture the above-mentioned diffusion wafer, first, as shown in FIG. 3 (a), a lapping process is performed on both surfaces of a silicon wafer W having a required thickness as a material using relatively coarse abrasive grains. It was a large surface D L of the damage.
Next, as shown in FIG. 3B, one surface (the lower side in FIG. 3B) of the silicon wafer W is covered with a protective pad 3 via an adhesive tape (not shown), and then the other side. (in FIG. 3 (b) above) subjected to lapping with relatively fine abrasive grains on the surface of, and the other surface with small surface D S of damage.
Next, the protective pad 3 is removed, and as shown in FIG. 3C, deposition and drive-in diffusion processes are sequentially performed on both surfaces of the silicon wafer W whose both surfaces have been changed to diffuse high-concentration impurities. after There has been formed a diffusion layer 1 by interposing the
[0016]
Here, in order to measure the dislocation density distribution of the non-diffusion layer, first, lapping with # 800 abrasive grains was performed on both sides of a 125 mm-diameter n-type silicon wafer by the CZ method, and 15 μm on each side, 30 μm in total. Then, a protective pad made of a fluororesin having a thickness of 1.5 mm and a diameter of 125 mm is pasted on one surface through an adhesive tape to protect one surface, and then the other surface is coated with # 1200 abrasive grains. An n-type silicon wafer was obtained by changing the lapping process by 10 μm to change the damage on both sides.
Next, an n-type silicon wafer having both surfaces changed is charged into an electric furnace, the temperature in the furnace is kept at 1200 ° C., and oxygen, nitrogen and POCl 3 gas are introduced into the furnace and heat-treated for 180 minutes. After forming a diffusion layer on both sides of the n-type silicon wafer, the n-type silicon wafer is heat-treated at a temperature of 1290 ° C. for 300 hours in an argon gas atmosphere to form a diffusion layer in which impurities are further diffused. Thereafter, the diffusion layer on the side with less damage was removed by grinding to expose the non-diffusion layer.
Next, the ground surface was polished with a margin of about 20 μm, and the damage caused by the grinding was completely removed to obtain a diffusion wafer. Then, the surface of each of these diffusion wafers is polished every 20 μm in the depth direction to prepare a sample, and a sample is prepared by angle wrap to show the tendency of the change in the dislocation density from the diffusion wafer surface to the diffusion layer interface. The dislocation density was evaluated. The results are shown in FIG.
[0017]
As can be seen from FIG. 4, the dislocation density distribution of the non-diffusion layer, the dislocation density gradually decreases from the interface B 1 of the small surface D S side of the damage to a position beyond the center C of the thickness of the non-diffusion layer, there minima after a, toward the interface B 2 larger surface D L side damage by increasing dislocation density, and the gradient of the dislocation density in the boundary of the minimum value smaller surface D S side of the damage, a large surface damage It is greater than the slope of the dislocation density of D L side.
It should be noted that the above-mentioned tendencies vary depending on the electrical resistance, oxygen concentration, type, surface damage, diffusion conditions, diffusion layer thickness, etc. of the silicon wafer before diffusion. Is desirable.
[0018]
【The invention's effect】
As described above, according to the diffusion wafer and the method of manufacturing the same of the present invention, the dislocation density on the surface of the non-diffusion layer is significantly higher than that of the conventional one in which the thickness of the non-diffusion layer is equal. In addition, raw materials can be reduced.
Further, by changing the gradient of the dislocation density from the surface of the non-diffusion layer to the vicinity of a predetermined surface layer, both the specification of the dislocation density and the thickness of the surface required for the non-diffusion layer can be satisfied.
[Brief description of the drawings]
FIG. 1 is a sectional view showing an example of an embodiment of a diffusion wafer according to the present invention.
FIG. 2 is a diagram showing a dislocation density distribution of a diffusion layer in the diffusion wafer of FIG.
3 (a) to 3 (d) show an example of an embodiment of a method for manufacturing a diffusion wafer according to the present invention. FIG. 3 (a) is an explanatory view of a first step, and FIG. (C) is an explanatory view of a third step, and (d) is an explanatory view of a final step.
FIG. 4 is a diagram showing a dislocation density distribution of a non-diffusion layer in a specific example of the diffusion wafer of FIG. 1;
[Explanation of symbols]
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003130217A JP4420268B2 (en) | 2003-05-08 | 2003-05-08 | Diffusion wafer and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003130217A JP4420268B2 (en) | 2003-05-08 | 2003-05-08 | Diffusion wafer and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004335771A true JP2004335771A (en) | 2004-11-25 |
JP4420268B2 JP4420268B2 (en) | 2010-02-24 |
Family
ID=33505809
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003130217A Expired - Lifetime JP4420268B2 (en) | 2003-05-08 | 2003-05-08 | Diffusion wafer and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4420268B2 (en) |
-
2003
- 2003-05-08 JP JP2003130217A patent/JP4420268B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP4420268B2 (en) | 2010-02-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7442992B2 (en) | Bonded SOI substrate, and method for manufacturing the same | |
CN101681805B (en) | SOI wafer manufacturing method | |
JPH04154147A (en) | Semiconductor device and manufacture thereof | |
CN104115255B (en) | The manufacture method of laminating SOI wafer | |
US20080224270A1 (en) | Silicon single crystal substrate and manufacture thereof | |
US7615467B2 (en) | Method for manufacturing SOI wafer | |
KR101340002B1 (en) | SOI Wafer Manufacturing Method | |
US5951755A (en) | Manufacturing method of semiconductor substrate and inspection method therefor | |
JP3454033B2 (en) | Silicon wafer and manufacturing method thereof | |
KR0148500B1 (en) | Semiconductor device and method of manufacturing the same | |
US20090011598A1 (en) | Method of manufacturing semiconductor device including silicon carbide substrate | |
US5024867A (en) | Dopant film and methods of diffusing impurity into and manufacturing a semiconductor wafer | |
GB2451602A (en) | Silicon on diamond microelectronic devices | |
JP4218681B2 (en) | Silicon single crystal substrate manufacturing method, resistance characteristic measuring method, and resistance characteristic guarantee method | |
US20080242067A1 (en) | Semiconductor substrate and method of manufacture thereof | |
JP4420268B2 (en) | Diffusion wafer and manufacturing method thereof | |
US5094976A (en) | Dopant film and methods of diffusing impurity into and manufacturing a semiconductor wafer | |
JP2010153488A (en) | Manufacturing method of soi wafer, and soi wafer | |
KR101888250B1 (en) | Method for forming wafer | |
US5352625A (en) | Method of manufacturing semiconductor substrate | |
JP4791694B2 (en) | Manufacturing method of semiconductor epitaxial wafer | |
JP4465760B2 (en) | Method for manufacturing vertical semiconductor device | |
EP3742473A1 (en) | Method for manufacturing bonded wafer, and bonded wafer | |
JP2975910B2 (en) | Method of manufacturing discrete substrate | |
JPH07221053A (en) | Method for polishing semiconductor substrate and manufacture of non-punch-through type semiconductor device using method for polishing semiconductor substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20041026 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060307 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20070711 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091119 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091125 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091125 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121211 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4420268 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121211 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131211 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131211 Year of fee payment: 4 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |