JP2004334780A - Interface control device, image formation apparatus, interface control method, computer program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface control device capable of dynamically switching an interface mode. <P>SOLUTION: The interface control device 1 is structured with a PCI control part 7 for controlling a PCI bus 3, a general-purpose memory control part 8 for controlling a general-purpose memory such as a ROM 5a and a RAM 5b, a PCI arbiter 9 for mediating which device is made to use the PCI bus 3 and a selector 10 for selecting which is used to control a terminal of the PCI bus 3, PCI control part 7 or the general-purpose memory control part 8. The control part is selected by the selector 10 according to the interface mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a control device for a plurality of interfaces including a PCI bus interface and a general-purpose memory interface, an image forming apparatus provided with the interface control device, a control method for the interface, a computer program for realizing the control method, and a computer. The present invention relates to a recording medium storing a program.
[0002]
[Prior art]
With the development of information technology in recent years, various external devices have been proposed. When designing a device that can respond to such various external devices, an increase in the number of terminals on the device side is inevitable because it corresponds to the interface of each external device. For example, a PCI bus interface and a general-purpose memory interface have a bus structure, so that the number of signal lines is large and the number of terminals is naturally increased. However, there is a problem that an increase in the number of terminals leads to an increase in chip size and ultimately an increase in cost.
[0003]
Therefore, the terminals are shared, but if they are simply shared, the time in the PCI bus mode and the time in the general-purpose bus mode are completely divided. That is, it is not possible to dynamically switch between access to the PCI bus and access to the general-purpose memory.
[0004]
[Problems to be solved by the invention]
The present invention has been made in view of such a situation of the related art, and an object thereof is to provide an interface control device capable of dynamically switching an interface mode, an image forming apparatus including the interface control device, and the interface. And a computer program for realizing the control method, and a recording medium storing the computer program.
[0005]
[Means for Solving the Problems]
To achieve the above object, a first means is an interface control device comprising a plurality of interfaces including first and second interfaces, and arbitration means for arbitrating a master connected to a PCI bus. And the arbitration means switches the connection state of the terminal according to the mode used by the interface.
[0006]
A second means is the first means, wherein the first interface is a PCI bus interface, and the second interface is a general-purpose memory interface.
[0007]
A third means is the first or second means, wherein the arbitration means switches the connection state of the terminals according to a mode used by a PCI bus interface and a mode used by a general-purpose memory interface, Arbitration is performed.
[0008]
A fourth means is the third means, wherein the arbitration means is configured to output a request signal from a PCI device connected to a PCI bus when the terminal is used in a mode used by the general-purpose memory interface. In this case, the permission signal is asserted after the access to the general-purpose memory is completely completed.
[0009]
Fifth means is the third means, wherein the arbitrating means asserts a request signal from a general-purpose memory device connected to a PCI bus when the terminal is used in a mode used by the PCI bus interface. In this case, the permission signal is asserted after the PCI bus becomes idle, and the access to the general-purpose memory device is started.
[0010]
A sixth means is the third means, wherein the arbitration means asserts a request signal from a general-purpose memory device connected to a PCI bus when the terminal is used in a mode used by the PCI bus interface. In this case, the assertion is made regardless of whether the PCI bus is in an idle state or not, and access to the general-purpose memory device is started when the PCI bus is in the idle state or when the PCI bus is in the idle state.
[0011]
A seventh means is the fifth or sixth means, wherein the general-purpose memory interface includes a general-purpose memory control circuit for detecting an idle state of the PCI bus.
[0012]
Eighth means is the third means, wherein the arbitration means is a frame signal which is a signal transmitted first when data is transferred when the terminal is used in a mode used by a general-purpose memory interface. The output is inhibited, and control is performed so as not to access the PCI device in the mode used by the general-purpose memory interface.
[0013]
The ninth means is characterized in that the image forming apparatus comprises the interface control device according to the first to eighth means and an image forming means for forming an image on a recording medium.
[0014]
Tenth means is an interface control method for arbitrating a plurality of interfaces including a first and a second interface and a master connected to a PCI bus, wherein the first interface is a PCI bus interface, and the second interface is a second bus. Are respectively composed of general-purpose memory interfaces, the terminals of both the first and second interfaces, and the connection states of the terminals according to the mode used by the PCI bus interface and the mode used by the general-purpose memory interface And performs arbitration of the master.
[0015]
An eleventh means is the tenth means, wherein the request signal is asserted from a PCI device connected to a PCI bus when the terminal is used in a mode used by the general-purpose memory interface. The permission signal is asserted after the memory access is completely completed.
[0016]
In a twelfth aspect, in the tenth aspect, the request signal is asserted from a general-purpose memory device connected to a PCI bus when the terminal is used in a mode used by the PCI bus interface. A permission signal is asserted after the PCI bus enters an idle state, and access to the general-purpose memory device is started.
[0017]
A thirteenth means is the tenth means, wherein when the terminal is used in a mode used by the PCI bus interface, when a request signal is asserted from a general-purpose memory device connected to the PCI bus, Assert regardless of whether the bus is idle or not, and start accessing the general-purpose memory device when the bus is idle or when the bus is idle.
[0018]
Fourteenth means is the tenth means, wherein when the terminal is used in a mode used by a general-purpose memory interface, output of a frame signal which is a signal to be transmitted first when transferring data is prohibited, It is characterized in that control is performed so as not to access the PCI device in the mode used by the general-purpose memory interface.
[0019]
The fifteenth means is characterized by a computer program loaded on a computer and executing the interface control method according to the tenth to fourteenth means.
[0020]
The sixteenth means is characterized by a recording medium in which the computer program according to the fifteenth means is read out by a computer and recorded so as to be executable.
[0021]
In the following embodiments, the arbitration means is connected to the PCI arbiter 9, the terminal is connected to the PIC bus 3, and the PCI bus interface is connected to a circuit connected to the PCI bus from the CPU interface 5 via the PCI control unit 7 and the selector 10. The general-purpose memory interface is a circuit connected to the PCI bus from the CPU interface 5 via the general-purpose memory control unit 8 and the selector 10, the PCI devices are PIC devices A and B (4a, 4b), and the general-purpose memory devices are the ROM 5a and the RAM 5b. Respectively.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an interface control device according to an embodiment of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 is a functional block diagram showing one example of a connection example of the interface control device and its peripheral devices according to the present embodiment. In FIG. 1, an interface control device 1 includes a CPU interface (cpuif) 6, a PCI control unit 7, a PCI arbiter 9, a general-purpose memory control unit 8, and a selector 10. Is connected to the PCI bus 3 via the. The CPU 2 executes a program. This program has, for example, a PCI bus interface on the PCI bus 3 stored in the ROM 5a, a PIC device A (4a) for realizing a predetermined function, and a PCI bus interface. A PCI device B (4b) that realizes a function different from that of 4a), a ROM 5a that stores programs and data, and a RAM 5b that stores calculation formulas and data used when executing the programs are connected.
[0024]
The CPU interface 6 decodes the interface with the CPU bus 25 and the address accessed from the CPU 2, and determines whether to access the PCI devices A and B (4a, 4b) or the ROM 5a or the RAM 5b. The PCI control unit 7 controls the PCI bus 3. The general-purpose memory control unit 8 controls general-purpose memories such as the ROM 5a and the RAM 5b. The PCI arbiter 9 arbitrates which device uses the PCI bus 3. The selector 10 selects whether the terminal of the PCI bus 3 is controlled by the PCI control unit 7 or the general-purpose memory control unit 8. The PCI arbiter 9 is connected to a signal line 21 for the PCI device A (4a) and a signal line 22 for the PCI device B (4b), whereby the interface control device 1 functions as a central master. The PCI arbiter 9 is also connected to a signal line 23 for the PCI control unit 7 and a signal line 24 for the general-purpose memory control unit 8. The selector 10 receives a select signal 11 from the general-purpose memory control unit 8. With this configuration, the terminal for the PCI interface can be used as a PCI bus or as a general-purpose memory. Since the terminal for the PCI interface (PCI bus 3) is used as a PCI bus or as a general-purpose memory as described above, the number of device terminals can be significantly reduced, and the cost can be reduced. The mounting area can be reduced.
[0025]
FIG. 2 shows details of signals input to and output from the PCI arbiter 9. Devices such as the PCI devices A and B (4a, 4b) that access the PCI bus 3 and modules such as the PCI control unit 7 and the general-purpose memory control unit 8 are all requested (REQ) by the PCI arbiter 9 in a point-to-point manner. ) Signal and permission (GNT) signal are input and output. That is, the signals REQ_A and GNT_A are applied to the signal line 21 connecting the PCI arbiter 9 and the PCI device A (4a), and the signal line 22 connecting the PCI arbiter 9 and the PCI device B (4b) is connected to the signal line 22. , REQ_B and GNT_B are applied, and these signal lines 21 and 22 are connected outside the interface control device 1. REQ_C and GNT_C signals are applied to a signal line 23 connecting the PCI arbiter 9 and the PCI control unit 7, and the signal line 23 is connected in the interface control device 1. Further, since the general-purpose memory control unit 8 also uses the PCI bus 3, the REQ_D and GNT_D signals are exchanged with the PCI arbiter 9 via the signal line 24 inside the interface control device 1, and arbitrated by the PCI arbiter 9. For the first time, a signal is output on the PCI bus 3. When arbitration is performed, the general-purpose memory control unit 8 outputs a signal “BUSY” to the selector 10 via the signal line 11, and the selector 10 receives the signal from the PCI control unit 7 or the signal from the general-purpose memory control unit 8. Select a signal. In this case, the interface control device 1 is a central master of the PCI bus 3, and performs arbitration between using the terminal in the PCI bus mode and using the terminal in the general-purpose memory mode. There is no need to perform exclusive control when accessing the memory space.
[0026]
FIG. 3 is a timing chart showing the timing at which the requests of the two PCI devices A and B (4a, 4b) are processed. In FIG. 3, in cycle 2, the PCI device A (4a) outputs a request signal REQ_A. Since there is no other request, the PCI arbiter 9 outputs the permission signal GNT_A in cycle 3. At the same time, assuming that the device B in the PCI device 4b outputs the request signal REQ_B, in the cycle 4, the device A sends the frame (FRAME) signal and an initiator ready (hereinafter referred to as IRDY) signal (not shown) to the H level bus. After confirming the idle state, the FRAME signal is output, and the address is output to AD. In cycle 5, the PCI arbiter 9 outputs GNT_B to REQ_B to notify the device B that the right to use the bus is B. Note that a frame (FRAME) signal, an initiator ready (IRDY) signal, and AD described later are PCI bus standard signals, and indicate a transfer amount that the master wants to transfer in FRAME and IRDY. For example, when FRAME is “H” and IRDY Is "H", indicating that the bus is idle. The master sets FRAME to "L" (active side) at the start of transfer, and at the same time, outputs address information to AD. In addition to AD, there is also a signal called CMD, which outputs commands (read, write) at the same timing. These signals are signal names according to a well-known standard and will not be described in detail here.
[0027]
On the other hand, in the cycle 6, since the IRDY signal (not shown) is asserted and the bus is not in an idle state, the PCI device B4b does not output the FRAME signal. Since the bus is idle in cycle 7, the PCI device B4b outputs the FRAME signal and outputs the address to AD. In other words, a general PCI device starts access after checking whether the bus is idle in FRAME and IRDY even if GNT is asserted to itself. Therefore, the PCI arbiter 9 can perform arbitration only based on the status of REQ and GNT from each device without observing the state of the bus.
[0028]
Next, a case where the PCI bus 3 is used as the PCI bus mode after using the PCI bus 3 as the general-purpose memory mode will be described with reference to FIGS. FIG. 4 is a timing chart of the process, and FIG. 5 is a diagram showing details of signals around the PCI arbiter when implementing the timing chart of FIG.
[0029]
In the general-purpose memory mode, the FRAME signal is not used to prevent the connected PCI devices A and B (4a, 4b) from reacting. This makes it possible to prevent the PCI devices A and B (4a, 4b) connected to the PCI bus 3 from responding in the general-purpose device mode. Therefore, when the GNT_B signal is asserted to the PCI device B (4b), the access is started by misunderstanding that the PCI bus 3 is in the idle state. That is, if the GNT_B signal is asserted in cycle 5, the FRAME signal is output in cycle 6 and access to the device B may be started. Therefore, the output timing of the GNT_B signal is delayed. FIG. 5 shows a method of realizing this. As is clear from FIG. 5, the BUSY signal output from the general-purpose memory control unit 8 is also input to the PCI arbiter 9, and the output condition of each of the signals GNT_A, GNT_B, and GNT_C indicates that when BUSY is not inactive. To be added. As described above, when a request signal is asserted from another PCI device while the terminal is used in the general-purpose memory mode, a bus collision occurs by asserting the permission signal after the general-purpose memory access is completely completed. Can be avoided.
[0030]
4 and 7, the case where the PCI bus 3 is used as the general-purpose memory mode after the PCI bus 3 is used as the PCI bus mode will be described with reference to FIGS. FIG. 6 is a timing chart of the processing, and FIG. 7 is a diagram showing details of signals around the PCI arbiter when the timing chart of FIG. 6 is implemented.
[0031]
Also in this case, when accessing the general-purpose memory ROMs 5a and 5b, it is necessary to determine whether the PCI bus 3 is actually used. For example, in FIG. 6, the GNT_D signal for general-purpose memory access is asserted in cycle 5, but when the general-purpose memory access is started in the next cycle 6, the PCI bus 3 may conflict. Therefore, even if the GNT_D signal is asserted, the use of the PCI bus 3 as a general-purpose memory access is delayed until cycle 7. FIG. 7 shows a method of realizing this. As shown in FIG. 7, when the FRAME signal and the IRDY signal for judging the idle state of the PCI bus are input to the general-purpose memory control unit 8 and the GNT_D signal is detected, both the FRAME signal and the IRDY signal become H level. If not, do not start access. As described above, when the request signal from the general-purpose memory device is asserted when the terminal is used in the PCI bus mode, the permission signal is asserted and the access is started after the PCI bus 3 is in the idle state. Bus collision can be avoided.
[0032]
Next, another example of using the PCI bus 3 as the general-purpose memory mode after using the PCI bus 3 as the PCI bus mode will be described with reference to FIGS. FIG. 8 is a processing timing chart, and FIG. 9 is a diagram showing details of signals around the PCI arbiter when the timing chart of FIG. 8 is implemented.
[0033]
The difference between FIG. 8 and FIG. 6 is that the GNT_D signal is asserted in cycle 5 in FIG. 6, but the GNT_D signal is asserted in cycle 6 in FIG. FIG. 9 shows an example of implementing this method. In this example, the FRAME signal and the IRDY signal for determining that the PCI bus 3 is in the idle state are input to the PCI arbiter 9, and the output condition of the GNT_D signal indicates that both the FRAME signal and the IRDY signal are H. Add. As a result, the general-purpose memory control unit 8 only needs to start access by seeing only the assertion of the GNT_D signal. Therefore, when the request signal from the general-purpose memory device is asserted while the terminal is used in the PCI bus mode, the enable signal is asserted even if the PCI bus 3 is not in the idle state, and the general-purpose memory control unit 8 sets the PCI signal. Access can be started by detecting the idle state of the bus 3.
[0034]
Such an interface control device 1 is used for an image forming apparatus such as a copier, a facsimile, a printer, or a multifunction peripheral (MFP-Multi Function Peripheral) that combines the above. By connecting peripheral devices such as a capacity storage device, a recording medium driving device, an image reading device, and a post-processing device, a small-sized image forming system can be constructed. As the image forming apparatus, for example, an electrophotographic type, an inkjet type, a type using photoengraving, a type using type printing, and the like are used. Description is omitted.
[0035]
Note that the functions of the interface control device 1 can be realized by a computer. At this time, a procedure corresponding to the functions can be programmed and downloaded to a computer to be executed. At this time, the control program may be stored in the ROM of the computer, or the program may be downloaded from an external server or a recording medium.
[0036]
【The invention's effect】
As described above, according to the present invention, the terminal of each interface is shared, and the connection state of each interface to the PCI bus can be switched according to the mode of the interface. On the other hand, dynamic mode switching becomes possible.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of connection of an interface control device and peripheral devices according to an embodiment of the present invention.
FIG. 2 is a diagram showing details of signals around a PCI arbiter in FIG. 1;
FIG. 3 is a timing chart showing timings at which requests of two PCI devices are processed.
FIG. 4 is a processing timing chart in a case where a PCI bus is used as a PCI bus mode after a PCI bus is used as a general-purpose memory mode.
FIG. 5 is a diagram showing details of signals around a PCI arbiter when the timing chart of FIG. 4 is implemented.
FIG. 6 is a processing timing chart in a case where a PCI bus is used as a general-purpose memory mode after a PCI bus is used as a PCI bus mode.
7 is a diagram illustrating details of signals around a PCI arbiter when the timing chart of FIG. 6 is implemented.
FIG. 8 is a processing timing chart in another embodiment in a case where a PCI bus is used as a general-purpose memory mode after a PCI bus is used as a PCI bus mode.
9 is a diagram showing details of signals around the PCI arbiter when the timing chart of FIG. 8 is implemented.
[Explanation of symbols]
1 Interface control device 2 CPU
3 PCI bus 4a, 4b PCI device 5a ROM
5b RAM
6 CPU interface (cpuif)
7 PCI control unit 8 General-purpose memory control unit 9 PCI arbiter 10 Selector

Claims (16)

An interface control device comprising: a plurality of interfaces including first and second interfaces; and arbitration means for arbitrating a master connected to a PCI bus.
An interface control device, wherein terminals of the plurality of interfaces are shared, and the arbitration unit switches the connection state of the terminals according to a mode used by the interface. 2. The interface control device according to claim 1, wherein the first interface comprises a PCI bus interface, and the second interface comprises a general-purpose memory interface. 3. The arbitration unit according to claim 1, wherein the arbitration unit switches the connection state of the terminals according to a mode used by a PCI bus interface and a mode used by a general-purpose memory interface, and arbitrates the master. Interface control device. The arbitration means completely terminates access to the general-purpose memory when a request signal is asserted from a PCI device connected to a PCI bus when the terminal is used in a mode used by the general-purpose memory interface. 4. The interface control device according to claim 3, wherein the permission signal is asserted after the termination. The arbitration means is configured such that when the terminal is used in a mode used by the PCI bus interface and the request signal is asserted from a general-purpose memory device connected to the PCI bus, the PCI bus enters an idle state. 4. The interface control device according to claim 3, wherein a permission signal is asserted after that, and access to the general-purpose memory device is started. The arbitration unit is configured to determine whether the PCI bus interface is in an idle state when a request signal is asserted from a general-purpose memory device connected to the PCI bus when the terminal is used in a mode used by the PCI bus interface. 4. The interface control device according to claim 3, wherein the interface controller is asserted regardless of whether the access is made, and the access to the general-purpose memory device is started when there is an idle state or when the idle state is reached. 7. The interface control device according to claim 5, wherein the general-purpose memory interface includes a general-purpose memory control circuit that detects an idle state of the PCI bus. The arbitration means inhibits output of a frame signal which is a signal to be transmitted first when transferring data when the terminal is used in a mode used by the general-purpose memory interface, and sets a mode used by the general-purpose memory interface. 4. The interface control device according to claim 3, wherein the control is performed so as not to access the PCI device. An interface control device according to any one of claims 1 to 8,
Image forming means for forming an image on a recording medium;
An image forming apparatus comprising: An interface control method for arbitrating a plurality of interfaces including a first and a second interface and a master connected to a PCI bus,
The first interface comprises a PCI bus interface, and the second interface comprises a general-purpose memory interface;
Terminals of a plurality of interfaces including both the first and second interfaces are shared,
Switching a connection state of the terminal according to a mode used by the PCI bus interface and a mode used by the general-purpose memory interface;
An interface control method comprising arbitrating the master. When a request signal is asserted from a PCI device connected to a PCI bus when the terminal is used in a mode used by the general-purpose memory interface, an enable signal is output after the general-purpose memory access is completely completed. 11. The interface control method according to claim 10, wherein is asserted. When the request signal is asserted from a general-purpose memory device connected to the PCI bus when the terminal is used in a mode used by the PCI bus interface, the permission signal is output after the PCI bus is in an idle state. 11. The interface control method according to claim 10, wherein the interface control unit asserts and starts accessing the general-purpose memory device. When the request signal is asserted from a general-purpose memory device connected to the PCI bus when the terminal is used in a mode used by the PCI bus interface, regardless of whether the PCI bus is in an idle state or not. 11. The interface control method according to claim 10, wherein the general-purpose memory device is accessed when asserted and in an idle state or when the idle state occurs. When the terminal is used in the mode used by the general-purpose memory interface, the output of the frame signal which is the first signal to be transmitted when transferring data is prohibited, and the output to the PCI device is performed in the mode used by the general-purpose memory interface. 11. The interface control method according to claim 10, wherein control is performed so that access is not performed. A computer program which is loaded on a computer and executes the interface control method according to any one of claims 10 to 14. A recording medium on which the computer program according to claim 15 is read by a computer and recorded in an executable manner.

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