JP2004328361A - Harmonic overtone generation method and harmonic overtone generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a harmonic overtone generation method and a harmonic overtone generater which enable the capacity of a buffer memory to be reduced. <P>SOLUTION: The harmonic overtone generation method consist of a processing step S11 for applying downsampling to an inputted signal, a step S12 for storing the inputted signal after the downsampling into a buffer memory, a step S13 for reading signal data from the buffer memory, a processing step S14 for applying upsampling to the read signal data and the processing step 15 for applying time axis compression operation to the upsampled signal and output of the processing step S15 becomes a harmonic overtone of the inputted signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an overtone generation method and an overtone generation device that generate overtones related to bass components.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, for various purposes, various acoustic signal devices including a harmonic generation device that generates a frequency component that is an integral multiple of an original sound, that is, a harmonic are proposed.
[0003]
For example, there has been known an acoustic signal processing device that generates harmonics of a low-frequency component that cannot be generated by a small speaker, and that uses a virtual pitch effect to improve bass feeling.
[0004]
Various frequency converters for converting the frequency of the original sound are known in relation to the harmonic generation device. The generation of harmonics may be considered as limiting the frequency conversion rate in frequency conversion to an integral multiple of 2 or more.
[0005]
The frequency conversion is performed by a time axis compression operation. For example, as shown in FIG. 23, by reproducing a signal having a time length t1 (FIG. 23A) with a shorter time length t2, the frequency can be increased to (t1 / t2) times (FIG. 23). 23 (b)).
[0006]
FIG. 24 shows, as a conventional example, a block diagram of a frequency conversion device described in Patent Document 1. As shown in FIG.
[0007]
This frequency conversion device performs a time axis compression operation by controlling the reading and writing speeds of the RAM serving as a buffer memory, that is, by reading out signals from the RAM at a speed faster than writing to the RAM, This increases the frequency of the input signal. However, such an operation necessarily involves a change in the reproduction time. Usually, a change in the reproduction time is corrected by appropriately resetting the read address.
[0008]
In FIG. 24, a read address counter 2415 and a write address counter 2416 give an address for reading data from the RAM and an address for writing to the RAM, respectively, and control the update speed of the addresses.
[0009]
The zero-cross detection circuit 2413 detects a zero-cross point for the signal stored in the RAM. The result is reflected in the read address resetting operation described above.
[0010]
That is, as shown in FIG. 25 (a), the shift between the zero-cross point detected by the zero-cross detection circuit and the provisionally determined reset addresses A1 and B1 is calculated, and the reset addresses of the reset addresses A1 to A2 and B1 to B2 are calculated. Make corrections. Thereby, as shown in FIG. 25B, the signal connection at the time of resetting the address is smoothly performed.
[0011]
[Patent Document 1]
JP-A-60-35795
[0012]
[Problems to be solved by the invention]
As described in the background art, the conventional harmonic generation apparatus requires a buffer memory having a capacity enough to store signal data exceeding a zero-cross section for a target signal. However, since the low-frequency component to be processed by the present technology has a long wavelength, the zero-cross section also becomes long, and therefore, there is a problem that the capacity of the buffer memory becomes enormous and the cost increases.
[0013]
The present invention has been made in view of the above problems, and has as its object to provide a harmonic generation method and a harmonic generation apparatus in which the capacity of a buffer memory for temporarily storing a signal in a zero-cross section is reduced.
[0014]
[Means for Solving the Problems]
A first invention is a harmonic generation method for generating an overtone of an input signal,
After performing downsampling on the input signal, store it in the buffer memory,
Up-sampling is performed on the signal read from the buffer memory,
The oversampled signal is used to generate harmonics by performing a time axis compression operation or a thinning operation.
[0015]
Thus, the signal is stored in the buffer memory in a state of being down-sampled, so that the required capacity of the buffer memory can be reduced.
[0016]
A second invention is a harmonic generation method for generating an overtone whose frequency is k times (k is a natural number) with respect to an input signal,
After down-sampling the input signal, it is stored in a buffer memory at a write address update speed p (p is a natural number),
Overtones are generated by up-sampling a signal read from the buffer memory at a read address update rate of p × k at a rate of 1 sample out of k samples.
[0017]
Thus, the signal is stored in the buffer memory in a state of being down-sampled, so that the required capacity of the buffer memory can be reduced. In addition, by performing upsampling at a rate of one sample out of k samples, an unnecessary sample upsampling operation can be omitted, so that the amount of calculation can be reduced.
[0018]
A third invention is a harmonic generation device that generates an overtone of an input signal,
Downsampling means for performing a thinning process on the input signal,
Zero-crossing detection means for detecting a zero-crossing point for any given signal in the process of processing the signal sequence,
A buffer memory for storing an output signal of the downsampling means;
Address management means for setting a read address from the buffer memory based on information of the zero-cross point detected by the zero-cross detection means and an order of a generated harmonic;
Upsampling means for selecting a coefficient of a filter used in upsampling from information of a read address from the address management means and upsampling a signal with respect to an output signal from the buffer memory. It is.
[0019]
Thus, the signal is stored in the buffer memory in a state of being down-sampled, so that the required capacity of the buffer memory can be reduced.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
First, the principle of a harmonic generation method in which the frequency conversion method described in the related art is improved for the purpose of generating harmonics, and a harmonic generation device to which the principle is applied will be described.
[0021]
First, the basic principle of frequency conversion of an integral multiple will be described with reference to FIG. An example of generating a harmonic of a sine wave as shown in FIG. The zero crossing point is defined as the point at which the signal changes from positive to negative or from negative to positive. For example, zero cross points from negative to positive are P1, P2, and P3. When generating the second harmonic, a section from a zero cross point from negative to positive to a next zero cross point from negative to positive (hereinafter, referred to as a zero cross section), a zero cross section P1-P2, a zero cross In the section P2-P3, the waveform is compressed to 1/2 in the time axis direction, and reproduced twice. As shown in FIG. 2B, the signal after this processing is a signal whose frequency is doubled.
[0022]
Similarly, the Nth overtone is generated by compressing it to 1 / N in the time axis direction and repeatedly playing back N times in the section of the zero cross point.
[0023]
FIG. 3 shows a block diagram of a basic harmonic generation device based on the above principle. The conventional harmonic generation device includes an input terminal 301 for receiving an input signal, a buffer memory 304 for temporarily storing a signal from the input terminal, a signal stored in the buffer memory 304, or an input or an output thereof, in which a zero cross point is set. A zero-cross detecting means 303 to be detected, an address managing means 305 for controlling a read address of a signal from the buffer memory 304 based on information from the zero-cross detecting means 303, and a signal read from the buffer memory 304, which is a target harmonic. Is constituted by an output terminal 308 for outputting this overtone to the outside.
[0024]
Here, the operation of the buffer memory 304 will be described with reference to FIG. Here, it is assumed that the order of the generated harmonic is 2 and one block is processed in units of 8 samples in the block processing.
[0025]
As shown in FIGS. 4A to 4B, the input signals are sequentially written in the buffer memory 304 in units of 8 samples, such as B1w, B2w, B3w,.
[0026]
On the other hand, as shown in FIG. 4 (b) to FIG. 4 (c), B1r, B2r, B3r,. In this way, the signal data read one sample at a time is output again as a signal of the original sampling frequency as shown in FIG. As a result, a signal whose frequency is doubled with respect to the input signal is obtained.
[0027]
The address management unit 305 controls a read address in the buffer memory 304. When the read address reaches the zero cross point address for the first time, the read address is returned to the previous zero cross point, and the address is updated again from there. In the second case, the read address is updated as it is without returning to the previous zero cross point. That is, it is repeated twice between adjacent zero-cross points.
[0028]
As can be seen from this operation, the update speed of the read address is twice the update speed of the write address. Therefore, it is necessary to provide a predetermined interval between the two addresses so that the read address does not overtake the write address.
[0029]
(Embodiment 1)
Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.
[0030]
First, a harmonic generation method according to Embodiment 1 of the present invention will be described with reference to FIG. Here, the detection of the zero-cross point which is not directly related to the essence of the present invention and the accompanying address management operation are omitted.
[0031]
As shown in FIG. 1, the overtone generation method according to the present embodiment includes a processing step S11 of downsampling an input signal, a step S12 of storing the input signal after downsampling in a buffer memory, It comprises a step S13 for reading out signal data, a processing step S14 for up-sampling the read-out signal data, and a processing step S15 for performing a time axis compression operation on the up-sampled signal.
[0032]
Further, a harmonic generation method showing an example of time axis compression will be described with reference to FIG. Here, it is assumed that a harmonic having a frequency of k times is generated.
[0033]
A processing step S51 of performing downsampling on an input signal of length M, a step S52 of storing the input signal after downsampling in a buffer memory, a step S53 of reading out signal data from the buffer memory, And a processing step S54 for performing upsampling to generate a signal of length M × k, and a processing step S55 for performing a thinning operation such as extracting a signal at a rate of one sample among k samples.
[0034]
Next, a more detailed operation will be described with reference to FIGS. Here, as a numerical example, it is assumed that the downsampling rate in step S51 is 1/4 and the order of the overtone to be generated is 2. In addition, block processing is performed in which eight samples (M = 8) are processed collectively (at the time of an input signal) in one block.
[0035]
The input signal having a length of 8 samples is down-sampled to 1/4 in step S51 to become 2 samples (FIG. 6A), and stored in the buffer memory in step S52 as (B1w, B2w, B3w,...). (FIG. 6B).
[0036]
In step S53, four samples of signal data are read from the buffer memory as (B1w, B2w, B3w,...) (FIG. 6C). That is, the read address from the buffer memory is behind the write address to the buffer memory, and the address update speed per unit time is twice the write address.
[0037]
In step S54, quadrupled up-sampling is performed on the four-sample signal data (FIG. 6D). This includes filtering to remove imaging distortion.
[0038]
In step S55, one sample of two samples is extracted from the up-sampled signal data (FIG. 6E). That is, the output sample and the discarded sample alternate. As a result, the signal is returned to the original time length, and the actual time axis compression operation is performed to obtain a signal having the same length as the original signal and a frequency doubled (FIG. 6 (f)).
[0039]
According to the above harmonic generation method, since the downsampled data can be stored in the buffer memory in a state where the number of signal data is reduced, the capacity of the buffer memory can be reduced.
[0040]
A harmonic generation device applied as an apparatus based on the harmonic generation method described above will be described.
[0041]
FIG. 7 is a block diagram of the overtone generation device according to the first embodiment of the present invention. The harmonic generation device according to the first embodiment includes an input terminal 701, a downsampling unit 702, a zero-cross detection unit 703, a buffer memory 704, an address management unit 705, an upsampling unit 706, a thinning unit 707, and an output terminal 708. .
[0042]
The input terminal 701 is a terminal for receiving an input signal to the harmonic generation device.
[0043]
The down-sampling unit 702 filters the input signal from the input terminal 701 to limit the frequency band in order to prevent alias distortion, and thins out the signal at predetermined intervals. In other words, the sampling frequency of the signal is reduced. As a filter for performing the filtering performed here, an FIR filter or an IIR filter may be used.
[0044]
The buffer memory 704 temporarily stores the output signal of the downsampling unit 702 in the memory, and outputs the signal stored in the memory to the upsampling unit 706 according to an instruction of the address management unit 705.
[0045]
The zero cross detection means 703 detects the zero cross point of the output signal from the up-sampling means 706.
[0046]
The address management unit 705 obtains a read address of a signal from the buffer memory 704 based on information from the zero-cross detection unit 703, and controls an output read from the buffer memory 704.
[0047]
The upsampling unit 706 filters the signal from the buffer memory 704 to limit the frequency band in order to prevent the occurrence of distortion due to imaging, returns the signal to the original sampling frequency, and further increases the signal length by k times ( k is the order of the overtone to be generated). As a filter for performing the filtering performed here, an FIR filter or an IIR filter may be used. The same filter as that used in the downsampling unit 702 may be used.
[0048]
The decimation unit 707 extracts a signal from the output from the up-sampling unit 706 once every k samples, performs time axis compression to increase the frequency by k times, and restores the length of the signal to the original value. It is.
[0049]
The output terminal 708 outputs an output signal from the thinning means 707 to the outside.
[0050]
Next, a more detailed operation will be described with reference to FIG. Here, as a numerical example, it is assumed that the downsampling rate in the downsampling unit 702 is 1/4 and the order of the overtone to be generated is 2. In addition, block processing is performed in which eight samples (at the time of input by the down-sampling unit 702) are processed in one block. Further, the zero-crossing detecting unit 703 performs a zero-crossing determination on the output of the up-sampling unit 706.
[0051]
The signal from the input terminal 701 is down-sampled to 1/4 by the down-sampling means 702 (FIG. 6A) and stored in the buffer memory 704 (FIG. 6B). If the input signal is 8 samples long, only 1/4 of them, 2 samples, is transferred to the buffer memory 704.
[0052]
The zero-crossing detecting means 703 detects a zero-crossing point from the output of the up-sampling means 706 and transmits it to the address managing means 705.
[0053]
The address management unit 705 calculates a read address from the buffer memory 704 based on the received information of the zero cross point. The read address from the buffer memory 704 is later than the write address to the buffer memory 704. The address update speed per unit time is twice as fast as the write address. That is, every time two samples are written into the buffer memory 704 (B1w, B2w, B3w,...), Four samples of signal data are read from the buffer memory 704 (B1r, B2r, B3r,...). (FIG. 6C).
[0054]
When the read address reaches the zero cross point, the read address returns to the previous read address at the zero cross point, and the address is updated again from there. That is, the zero cross section is repeated twice.
[0055]
The upsampling unit 706 performs quadruple upsampling on the output (FIG. 6C) from the buffer memory 704 (FIG. 6D). This includes filtering to remove imaging distortion.
[0056]
Here, the signal data read from the buffer memory 704 and filtered by the upsampling unit 706 will be briefly commented. In order for the upsampling unit 706 to perform filtering, past signal data based on the filter order is required. There are the following three methods for this.
[0057]
Method 1
The read address to the buffer memory 704 indicates the start (or end) address of the signal data, and then the continuous signal data is transferred from the buffer memory 704 by the amount (α) necessary for the filtering in the upsampling unit 706. read out.
[0058]
Method 2
Only new signal data is read from the buffer memory 704, and the other past signal data uses the signal data recorded by the upsampling unit 706. That is, the up-sampling unit 706 also includes a unit that retains past signal data.
[0059]
Method 3
It is an eclectic system of systems 1 and 2. The past filter output signal data accompanying the filtering is held in the up-sampling unit 706, and all the input signal data to the filter is supplied from the buffer memory 704.
[0060]
The decimation unit 707 extracts one sample out of two samples from the output of the upsampling unit 706 (FIG. 6D) (FIG. 6E). That is, the output sample and the discarded sample alternate. As a result, the signal is returned to the original time length, and a time axis compression operation is actually performed to obtain a signal having the same length as the original signal and a frequency doubled (FIG. 6 (f)).
[0061]
Here, the output of the up-sampling unit 706 is used as the signal for detecting the zero-cross point in the zero-crossing detecting unit 703. However, as shown in FIG. , A signal from which a zero-cross point should be detected. In this case, the time of the zero crossing point at the output of the upsampling unit 706 may be adjusted in consideration of the delay in the processing of the downsampling unit 702, the buffer memory 704, and the upsampling unit 706 in advance.
[0062]
Further, although the time resolution is inferior, it is also possible to detect the zero-cross point by the output of the thinning means 707. A block diagram in that case is shown in FIG.
[0063]
Further, as shown in FIGS. 8C, 8D, and 8E, the input, output, or recorded signal data of the buffer memory 704 may be used as a signal for detecting a zero-cross point. . Also in this case, it is necessary to consider the delay in the processing of the buffer memory 704 and the upsampling unit 706 in advance, and adjust the time to the zero-cross point time at the output of the upsampling unit 706.
[0064]
In each of the configurations shown in FIGS. 8C, 8D, and 8E, since the down-sampled signal data is used, the zero-cross point is detected with a large time resolution.
[0065]
In order to avoid this, for example, a method is considered in which the time resolution in detecting the zero-cross point is made fine using linear interpolation. This will be described with reference to FIG.
[0066]
In the case where a zero cross point is not included as in x (40), x (44), and x (52), it may be left as it is.
[0067]
When a zero crossing point is detected as in x (48), a straight line is connected to the previous down-sampled sample x (44), and the samples x (45), x inserted on the straight line are connected. When the zero cross point is detected including (46) and x (47), the time resolution of the detection can be improved.
[0068]
Various other modifications are conceivable for the method of detecting a zero cross, but any method may be used since the present invention does not depend on the method of detecting a zero cross.
[0069]
According to the present embodiment, the signal data stored in buffer memory 704 is reduced by １ ／ of the original signal data, that is, by the downsampling rate of downsampling means 702. Therefore, the capacity of the buffer memory 704 is only required to be 1/4, which indicates that the buffer memory 704 has a great effect in reducing the capacity of the buffer memory.
[0070]
The above operation will be described with a specific example. Here, a signal including the zero cross points y (41) and y (104) shown in FIG. 10 will be considered as an example. The downsampling rate is 1/4, and the second harmonic is produced. As a filter for removing imaging distortion at the time of upsampling, the following 16-tap FIR filter F (z−¹) Shall be used.
[0071]
F (z-¹) = F (0) + f (1) z^-1+ F (2) z-²+ ・ ・ + F (15) z-^Fifteen
In this example, it is assumed that the overtone y (n) is obtained at each time t. The values of x (4m + 1), x (4m + 2), and x (4m + 3) (m is a natural number) do not exist in the buffer memory, and may be calculated assuming that the value is 0. The multiplication of the value 0 can be omitted.
[0072]
Hereinafter, up to the point where the zero cross section is repeated twice is listed.
[0073]
t = 0, t = 1:
The down-sampled signal is written as x (80).
[0074]
Read x (28), x (32), x (36), x (40)
Generate signals y (40), y (41), y (42), y (43).
[0075]
Finally, y (40) and y (42) are output.
[0076]
t = 2, t = 3:
Read x (32), x (36), x (40), x (44)
Generate signals y (44), y (45), y (46), y (47).
[0077]
Finally, y (44) and y (46) are output.
[0078]
t = 4, t = 6:
Write as a signal x (84) after downsampling.
[0079]
Read x (36), x (40), x (44), x (48)
Generate y (48), y (49), y (50), y (51) signals.
[0080]
Finally, y (48) and y (50) are output.
[0081]
…
t = 30, t = 31:
Read x (88), x (92), x (96), x (100)
Generate y (100), y (101), y (102), y (103) signals.
[0082]
Finally, y (100) and y (102) are output.
[0083]
t = 32, t = 33:
Write down-sampled signal as x (112)
Read x (28), x (32), x (36), x (40)
Generate signals y (40), y (41), y (42), y (43).
[0084]
Finally, y (41) and y (43) are output.
[0085]
t = 34, t = 35:
Read x (32), x (36), x (40), x (44)
Generate signals y (44), y (45), y (46), y (47).
[0086]
Finally, y (45) and y (47) are output.
[0087]
…
t = 62, t = 63:
Read x (88), x (92), x (96), x (100)
Generate signals y (100), y (101), y (102), y (103).
[0088]
Finally, y (101) and y (103) are output.
[0089]
t = 64, t = 65:
Write down-sampled signal as x (144)
Read x (92), x (96), x (100), x (104)
Generate signals y (104), y (105), y (106), y (107).
[0090]
Finally, y (105) and y (107) are output.
[0091]
…
Overtones can be generated by such a series of operations.
[0092]
The harmonic generation device of the present invention can be applied as hardware or software in a computer.
[0093]
(Embodiment 2)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0094]
First, a harmonic generation method according to Embodiment 2 of the present invention will be described with reference to FIG. Here, it is assumed that a harmonic having a frequency of k times is generated, and the detection of a zero-cross point which is not directly related to the essence of the present invention and the accompanying address management operation are omitted.
[0095]
As shown in FIG. 11, the overtone generation method according to the present embodiment includes a processing step S111 of downsampling an input signal, and a step S112 of storing the input signal after downsampling in a buffer memory at a writing speed p. A step S113 of reading signal data from the buffer memory at a reading speed p × k, and a processing step S114 of upsampling the read signal data at a rate of one sample out of k samples to generate harmonics. .
[0096]
Next, a more detailed operation will be described with reference to FIGS. Here, as a numerical example, it is assumed that the downsampling rate in step S1 is 1/4 and the order of the generated harmonic is 2. In addition, block processing is performed in which eight samples (M = 8) are processed collectively (at the time of an input signal) in one block.
[0097]
The input signal having a length of 8 samples is down-sampled to 1/4 in step S111 to be 2 samples (FIG. 12A), and stored in the buffer memory in step S112 as (B1w, B2w, B3w,...). (FIG. 12B).
[0098]
In step S113, four samples of signal data are read from the buffer memory as (B1w, B2w, B3w,...) (FIG. 12C). That is, the read address from the buffer memory is behind the write address to the buffer memory, and the address update speed per unit time is twice the write address.
[0099]
In step S114, quadrupled up-sampling is performed on the four-sample signal data (FIG. 12D). This includes filtering to remove imaging distortion. Here, it is assumed that only one of the two samples is up-sampled. In other words, the upsampling operation is performed only for 8 samples, where 16 samples are obtained if all are upsampled. These 8 samples become the second harmonic of the same length 8 as the input signal.
[0100]
According to the above harmonic generation method, as in the first embodiment, the effect of reducing the capacity of the buffer memory is obtained, and in the first embodiment, the data discarded by the thinning means is not calculated in advance, so that the amount of calculation is It also has the effect of reducing.
[0101]
A harmonic generation device applied as an apparatus based on the harmonic generation method described above will be described. FIG. 13 is a block diagram of a harmonic generation device according to Embodiment 2 of the present invention.
[0102]
The harmonic generation device according to the second embodiment includes an input terminal 1301, a downsampling unit 1302, a zero-cross detection unit 1303, a buffer memory 1304, an address management unit 1305, an upsampling unit 1306, and an output terminal 1308.
[0103]
The input terminal 1301 is a terminal that receives an input signal to the harmonic generation device.
[0104]
The downsampling means 1302 performs filtering for limiting the frequency band to the input signal from the input terminal 1301 in order to prevent the occurrence of alias distortion, and thins out the signal at predetermined sampling intervals. In other words, the sampling frequency of the signal is reduced. As a filter for performing the filtering performed here, an FIR filter or an IIR filter may be used.
[0105]
The buffer memory 1304 temporarily stores the output signal of the downsampling unit 1302 in the memory, and outputs the signal stored in the memory to the upsampling unit 1306 in accordance with an instruction from the address management unit 1305.
[0106]
The zero-crossing detecting unit 1303 detects the zero-crossing of the signal stored in the buffer memory 1304, the input signal to the buffer memory 1304, the output signal from the buffer memory 1304, or the output signal from the up-sampling unit 1306. This is to detect points. Since this is the same as that described in Embodiment 1, only the case where the output signal from the upsampling unit 1306 is targeted will be described.
[0107]
The address management unit 1305 obtains a read address of a signal from the buffer memory 1304 based on information from the zero-cross detection unit 1303, and controls an output read from the buffer memory 1304.
[0108]
The up-sampling unit 1306 filters the signal from the buffer memory 1304 to limit the frequency band in order to prevent distortion due to imaging, restores the original sampling frequency, and further increases the frequency by k times. is there. Here, an FIR filter is used.
[0109]
The output terminal 1308 outputs an output signal from the upsampling unit 16 to the outside.
[0110]
Next, a more detailed operation will be described with reference to FIG. Here, as a numerical example, as in the first embodiment, it is assumed that the downsampling rate in the downsampling unit 1302 is 4, and the order of the generated harmonic is 2. In addition, block processing is performed in which one block collectively processes eight samples (at the time of input by the downsampling unit 1302).
[0111]
The zero-cross detecting means 1303 performs a zero-crossing determination on the output of the up-sampling means 1306.
[0112]
The signal from the input terminal 1301 is down-sampled to 1/4 by the down-sampling means 1302 (FIG. 12A) and stored in the buffer memory 1304 (FIG. 12B). If the input signal is 8 samples long, only 1/4 of the 2 samples are transferred to the buffer memory 1304.
[0113]
The zero-cross detecting means 1303 detects a zero-crossing point from the output of the up-sampling means 1306 and transmits it to the address managing means 1305.
[0114]
The address management unit 1305 calculates a read address from the buffer memory 1304 based on the received information of the zero cross point. The read address from the buffer memory 1304 is behind the write address to the buffer memory 1304. The address update speed per unit time is twice as fast as the write address. That is, every time two samples are written to the buffer memory 1304 (B1w, B2w, B3w,...), Four samples of signal data are read from the buffer memory 1304 (B1r, B2r, B3r,...). (FIG. 12C).
[0115]
The operation up to this point is the same as in the first embodiment. In this embodiment, there is no thinning means, and the function of the upsampling means 1306 also serves as the function.
[0116]
The upsampling unit 1306 performs quadrupling upsampling on the output from the buffer memory 1304. In the first embodiment, however, it is important that data to be decimated by the decimating unit is not generated at this time. It is a feature.
[0117]
For this purpose, the upsampling unit 1306 obtains only every two samples by filtering (FIG. 12D).
[0118]
As a result, if the output from the buffer memory 1304 is signal data of 4 samples, the signal data should be 4 times the signal data of 16 samples. Is generated. This is a practical time axis compression operation, and a signal (FIG. 12 (e)) having the same length as the original signal and a frequency doubled is obtained.
[0119]
In this embodiment, as in the first embodiment, when the read address reaches the zero cross point, the read address is reset to the previous zero cross point. Then, a second round of up-sampling processing is performed from the zero cross point.
[0120]
Here, the sample to be obtained in the second round differs depending on the length of the zero cross section, that is, whether the number of samples is even or odd. This will be described with reference to FIG. As shown in FIG. 14A, if the length of the zero cross section is an even number, the same signal data as in the first cycle may be obtained. When the length of the zero cross section is an odd number as shown in FIG. 14B, signal data of a sample not obtained in the first round may be obtained. That is, the sample obtained in the first round is not obtained in the second round.
[0121]
In this way, the number of samples of the input signal and the output signal can be kept constant, and harmonics with little distortion can be generated.
[0122]
The method for obtaining the second overtone has been described above, but the third overtone can be generated by the same operation.
[0123]
For example, consider a case where a third harmonic is generated. The upsampling unit 1306 may obtain signal data by filter processing every three samples. In this case, the zero cross section is divided into three cases of 3n, 3n + 1, and 3n + 2 (n is a natural number). This will be described with reference to FIG.
[0124]
(A) When the zero cross section is 3n FIG.
The same signal data is obtained for all of the first, second, and third rounds.
[0125]
(B) When the zero cross section is 3n + 1 FIG. 15 (b)
The signal data obtained in the second cycle is signal data one sample past the sample in the first cycle. The signal data obtained in the third round is the signal data one sample before the sample in the second round.
[0126]
(C) When the zero cross section is 3n + 2 FIG. 15 (c)
The signal data obtained in the second round is signal data one sample future from the sample in the first round. The signal data obtained in the third round becomes signal data one sample future from the sample in the second round.
[0127]
Next, the operation will be described with a specific example. Here, as in the first embodiment, a signal including zero cross points y (41) and y (104) shown in FIG. 10 will be considered as an example. Hereinafter, as in the first embodiment, the downsampling rate is 1/4, the second harmonic is generated, and the following 16-tap FIR filter F (z) is used as a filter for removing imaging distortion at the time of upsampling. ―¹) Shall be used.
[0128]
F (z-¹) = F (0) + f (1) z^-1+ F (2) z-²+ ・ ・ + F (15) z-^Fifteen
In this example, it is assumed that the overtone y (n) is obtained at each time t. The values of x (4m + 1), x (4m + 2), and x (4m + 3) (m is a natural number) do not exist in the buffer memory, and may be calculated assuming that the value is 0. The multiplication of the value 0 can be omitted.
[0129]
Hereinafter, up to the point where the zero cross section is repeated twice is listed.
[0130]
t = 0, t = 1:
The down-sampled signal is written as x (80).
[0131]
Read x (28), x (32), x (36), x (40)
Generate and output signals y (40) and y (42).
[0132]
t = 2, t = 3:
Read x (32), x (36), x (40), x (44)
Generate and output signals of y (44) and y (46).
[0133]
t = 4, t = 6:
Write as a signal x (84) after downsampling.
[0134]
Read x (36), x (40), x (44), x (48)
Generate and output y (48) and y (50) signals.
[0135]
…
t = 30, t = 31:
Read x (88), x (92), x (96), x (100)
Generate and output signals of y (100) and y (102).
[0136]
t = 32, t = 33:
Write down-sampled signal as x (112)
Read x (28), x (32), x (36), x (40)
Generate and output signals y (40) and y (42).
[0137]
Finally, y (41) and y (43) are output.
[0138]
t = 34, t = 35:
Read x (32), x (36), x (40), x (44)
Generate and output signals of y (44) and y (46).
[0139]
…
t = 62, t = 63:
Read x (88), x (92), x (96), x (100)
Generate and output signals of y (100) and y (102).
[0140]
t = 64, t = 65:
Write down-sampled signal as x (144)
Read x (92), x (96), x (100), x (104)
Generate and output y (104) and y (106) signals.
[0141]
…
Overtones can be generated by such a series of operations.
[0142]
According to the present embodiment, the effect of reducing the capacity of the buffer memory is the same as that of the first embodiment. However, since signal data that is known to be thinned out in advance is not obtained from the beginning, the amount of calculation is reduced. It turns out that it is better in meaning.
[0143]
The harmonic generation device of the present invention can be applied as hardware or software in a computer.
[0144]
(Embodiment 3)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
[0145]
FIG. 16 is a block diagram of a harmonic generation device according to Embodiment 3 of the present invention. In this embodiment, the upsampling unit described in the second embodiment performs processing more efficiently.
[0146]
The harmonic generation device according to the third embodiment includes an input terminal 1601, a downsampling unit 1602, a zero-cross detection unit 1603, a buffer memory 1604, an address management unit 1605, an upsampling unit 1606, and an output terminal 1608. Further, the up-sampling unit 1606 includes a sub-filter operation unit 1611 and a sub-filter coefficient selection unit 1612.
[0147]
Since the entire operation is almost the same as that of the second embodiment, the description of the overlapping portions will be omitted, and the operation of the upsampling unit 1606 and the address management unit 1605, which are the features of the present embodiment, will be mainly described.
[0148]
The address management unit 1605 obtains a read address of a signal from the buffer memory 1604 based on information from the zero-cross detection unit 1603, and controls an output read from the buffer memory 1604. Further, information for designating a sub-filter to be selected is transmitted to sub-filter coefficient selecting section 1612.
[0149]
The sub-filter coefficient selection unit 1612 receives the sub-filter selection information from the address management unit 1605, selects a corresponding sub-filter coefficient sequence, and sends the coefficient sequence to the sub-filter operation unit 1611.
[0150]
The sub-filter operation unit 1611 performs sub-filter processing (product-sum operation) on the coefficient sequence of the sub-filter selected by the sub-filter coefficient selection unit 1611 and the signal read from the buffer memory 1604.
[0151]
FIG. 17 shows the address management unit 1605 and the upsampling unit 1606 more specifically in the overall configuration of the overtone generation device of FIG.
[0152]
The address management unit 1605 increases the address by an order (for example, 2) corresponding to the generated harmonic using a register and an adder provided inside.
[0153]
As a result, the sample is up-sampled every second time, so that the up-sampling process for unnecessary samples as described in the second embodiment can be omitted.
[0154]
Here, when the zero-cross point is reached from the zero-cross point information from the zero-cross detection means 1604, the read address is reset to the previous zero-cross point or a position advanced by several samples from the previous zero-cross point.
[0155]
The lower bits of the address calculated by the address management unit 1605 are sent to the sub-filter coefficient selection unit 1612 as sub-filter selection information.
[0156]
The upper bits of the address calculated by the address management unit 1605 are sent to the buffer memory 1604 as information for reading a data string.
[0157]
Sub-filter coefficient selection section 1612 selects a corresponding sub-filter coefficient sequence based on the transmitted lower bit information.
[0158]
The buffer memory 1604 sends four continuous data strings to the sub-filter operation unit 1611 based on the upper bit information of the read address sent from the address management unit 1605.
[0159]
The sub-filter operation unit 1611 performs a product-sum operation on the coefficient sequence of the sub-filter selected by the sub-filter coefficient selection unit 1612 and the signal read from the buffer memory 1604, and outputs the result to the outside.
[0160]
Here, the principle of upsampling using sub-filter processing will be described. As a numerical example, the number of taps of the FIR filter is 16, and the downsampling rate is 1/4 (upsampling rate 4). A signal taken out from the buffer memory is x (4m), and an up-sampling output is y (n).
[0161]
First, the following FIR filter is taken up.
[0162]
F (z^-1) = F (0) + f (1) z^-1+ F (2) z-²+ ・ ・ + F (15) z-^Fifteen
The FIR filter is divided into four sub-filters.
[0163]
f0 (z^-1)
= F (0) + f (4) z^-4+ F (8) z-⁸+ F (12) z-¹²
f1 (z^-1)
= [F (1) + f (5) z^-4+ F (9) z-⁸+ F (13) z-¹²] Z^-1
f2 (z^-1)
= [F (2) + f (6) z^-4+ F (10) z-⁸+ F (14) z-¹²] Z^-2
f3 (z^-1)
= [F (3) + f (7) z^-4+ F (11) z-⁸+ F (15) z-¹²] Z^-3
Therefore, the up-sampling signal y (n) is obtained by determining to which of the following four sequences the time n belongs, and performing a corresponding sub-filter process.
[0164]
(A) n = 4m series
y (n) = f (0) x (4m) + f (4) x (4m-4)
+ F (8) x (4m-8)
(B) Series of n = 4m + 1
y (n) = f (1) x (4m) + f (5) x (4m-4)
+ F (9) x (4m-8)
(C) Series of n = 4m + 2
y (n) = f (2) x (4m) + f (6) x (4m-4)
+ F (10) x (4m-8)
(D) Series of n = 4m + 3
y (n) = f (3) x (4m) + f (7) x (4m-4)
+ F (11) x (4m-8)
Here, the determination of the sub-filter can be performed based on information from the least significant bit to the least significant two bits when n is represented in bits (binary number representation). This corresponds to information (n−4m) of lower 2 bits from n least significant bits.
[0165]
This operation will be described with a more specific example.
[0166]
Consider obtaining the overtone y (n) at each time t. Consider an example in which the downsampling rate is 1/4 and the second harmonic is generated. It is also assumed that the zero cross points are at y (41) and y (104).
[0167]
First, the signal data x (4m) is read from the buffer memory 14 based on the upper bits (= 4m) of n. Also, based on the lower bits (= n−4m) of n, the sub-filter f0 (z^-1) To f3 (z^-1) Is selected, and the product-sum operation is executed by the filter operation means.
[0168]
The above operations are listed up to the point where the zero cross section is repeated twice.
[0169]
t = 0, t = 1:
Write down-sampled signal as x (80)
Read x (28), x (32), x (36), x (40)
Generate a signal of y (40), f0 (z^-1)use
Generate a signal of y (42), f2 (z^-1)use
t = 2, t = 3:
Read x (32), x (36), x (40), x (44)
Generate a signal of y (44), f0 (z^-1)use
Generate a signal of y (46), f2 (z^-1)use
t = 4, t = 5:
Write down-sampled signal as x (84)
Read x (36), x (40), x (44), x (48)
Generate a signal of y (48), f0 (z^-1)use
Generate a signal of y (50), f2 (z^-1)use
…
t = 30, t = 31:
Read x (88), x (92), x (96), x (100)
Generate a signal of y (100), f0 (z^-1)use
Generate a signal of y (102), f2 (z^-1)use
t = 32, t = 33:
Write down-sampled signal as x (112)
Read x (28), x (32), x (36), x (40)
Generate a signal of y (41), f1 (z^-1)use
Generate a signal of y (43), f3 (z^-1)use
t = 34, t = 35:
Read x (32), x (36), x (40), x (44)
Generate a signal of y (45), f1 (z^-1)use
Generate a signal of y (47), f3 (z^-1)use
…
t = 62, t = 63:
Read x (88), x (92), x (96), x (100)
Generate a signal of y (101), f1 (z^-1)use
Generate a signal of y (103), f3 (z^-1)use
t = 64, t = 65:
Write down-sampled signal as x (144)
Read x (92), x (96), x (100), x (104)
Generate a signal of y (105), f1 (z^-1)use
Generate a signal of y (107), f3 (z^-1)use
…
Overtones can be generated by such a series of operations.
[0170]
Here, when the selection of the sub-filter is viewed in time series, periodicity is seen according to the relationship between the generated harmonic order and the downsampling rate (= upsampling rate).
For example, considering the case where the harmonic order is 2 and the downsampling rate is 4, the selection of the sub-filter is performed as in the above-described example. , Subfilter 1, subfilter 3, subfilter 1, subfilter 3, and so on.
[0171]
Using this periodicity, the change pattern of the coefficient sequence selection is tabulated, and after the first iteration of the coefficient sequence selection at the zero crossing point, the coefficient sequence is selected using this table, so that the coefficient sequence is selected. It is also possible to reduce the number of steps required for selection.
[0172]
Here, an example of generating the second overtone at a downsampling rate of 1/4 has been described. However, the same procedure can be performed for other downsampling rates and kth overtones.
[0173]
According to the present embodiment, the reduction of the capacity of the buffer memory is the same as that of the second embodiment, and the use of a sub-filter eliminates unnecessary product-sum operation processing. It turns out that it is better in terms of reducing the amount.
[0174]
The harmonic generation device of the present invention can be applied as hardware or software in a computer.
[0175]
(Embodiment 4)
Embodiment 4 of the present invention will be described with reference to the drawings.
[0176]
The present embodiment relates to the harmonic generation device of the first embodiment and is extended to generate a plurality of harmonics.
[0177]
As shown in FIG. 18, the downsampling means 1802 and the buffer memory 1804 are shared since all overtone generations are common until they are written to the buffer memory 1804. Then, a zero-cross detecting means 1803a to 1803c, an address managing means 1805a to 1805c, an up-sampling means 1806a to 1806c, and a thinning-out means 1807a to 1807c are provided for each harmonic to be generated, and harmonics may be generated respectively. For each of the generated harmonics, the amplitude level is adjusted by multipliers 1809a to 1809c, added by an adder 1810, and output to the outside.
[0178]
It should be noted that the zero-crossing point has nothing to do with the overtone magnification on the input side or output side of the buffer memory. Therefore, when the signal for detecting the zero-cross point by the zero-cross detecting means is an input signal (FIG. 19) or an output signal of the downsampling means 1802 or a signal stored in the buffer memory 1804, the zero-cross detecting means 1803 Can also be shared.
[0179]
When the zero-cross point is detected by the input signals and output signals of the up-sampling units 1806a to 1806c and the output signals of the thinning units 1807a to 1807c, the zero-cross detection unit 1803 is installed only at the place where the harmonic has the highest degree. It is also possible (FIG. 20). The reason why the magnification of the overtone is set to be the highest is that the read address reaches the next zero cross point earliest.
[0180]
The case where a plurality of harmonics are generated has been described above. Here, as an example, the case where the harmonic generation device shown in Embodiment 1 is extended has been described. However, the harmonic generation device shown in Embodiments 2 and 3 may be extended in the same way. Can be.
[0181]
The harmonic generation device of the present invention can be applied as hardware or software in a computer.
[0182]
(Embodiment 5)
Embodiment 5 of the present invention will be described with reference to the drawings.
[0183]
The present embodiment is an extension of the overtone generation device shown in the first embodiment so as to perform band division processing and generate overtones for each frequency band.
[0184]
In such a case, as shown in FIG. 21, after the downsampling unit 2102, band pass filters 2112a to 2112c for performing band division processing are newly inserted. Then, zero-cross detection units 2103a to 2103c, buffer memories 2104a to 2104c, address management units 2105a to 2105c, upsampling units 2106a to 2106c, and thinning units 2107a to 2107c are provided for each frequency band. With this configuration, harmonic generation is performed for each frequency band.
[0185]
Then, the amplitude levels of the harmonics generated in each frequency band are adjusted by multipliers 2109a to 2109c, added by adder 2110, and output to the outside.
[0186]
The harmonic generation device according to the present embodiment also has an effect that the capacity of the buffer memory can be reduced as in the previous embodiments.
[0187]
In addition, the harmonic generation device according to the present embodiment has an effect of reducing the amount of calculation of the band-pass filter that performs the band division processing. That is, since the band-pass filters 2112a to 2112c for extracting the components of each frequency band are operated at a low sampling frequency, the number of taps of the band-pass filter can be reduced and the number of samples processed per unit time can be reduced. The amount of calculation (the number of multiplications per unit time) can be reduced.
[0188]
Compared to the case without downsampling, the number of times the bandpass filter is called per unit time is 1 / D (D is the downsampling rate), and the number of taps of the bandpass filters 2112a to 2112c is 1 / D (configured by an FIR filter ), The total amount of computation per unit time required for the bandpass filters 2112a to 2112c can be reduced to 1 / D²Can be reduced to That is, it can be seen that there is a great effect in reducing the amount of calculation per unit time.
[0189]
Here, as an example, the case where the harmonic generation device described in the first embodiment is extended has been described. However, the harmonic generation device described in the other embodiments can be extended based on the same concept.
[0190]
The harmonic generation device of the present invention can be applied as hardware or software in a computer.
[0191]
(Embodiment 6)
In the present embodiment, a case will be described in which the overtone generation device according to the present invention described so far is applied to an acoustic signal processing device that improves the low-pitched sound of a small loudspeaker using the virtual pitch effect.
[0192]
FIG. 22 is a block diagram of the acoustic signal processing device. The acoustic signal processing device according to the present embodiment includes an input terminal 2218, a delay 2213, a low-pass filter 2214, a high-pass filter 2215, a harmonic generation device 2216, an adder 2217, and an output terminal 2219.
[0193]
Any of the harmonic generation devices described in Embodiments 1 to 5 is used as the harmonic generation device 2216 as a component.
[0194]
Next, the operation of the acoustic signal processing device shown in FIG.
[0195]
The input signal input from the input terminal 2218 is input to the delay 2213 and the low-pass filter 2214, respectively.
[0196]
The delay 2213 delays the input signal by the delay caused by the processing of the harmonic generation device 2216.
[0197]
The low-pass filter 2214 extracts a low-frequency component from which an overtone is to be generated from the input signal.
[0198]
The harmonic generation device 2216 generates harmonics for the output of the low-pass filter 2214.
[0199]
The output signal of the delay 2213 and the output signal of the harmonic generation device 2216 are added by the adder 2217. The output signal of the adder 2217 is input to the high-pass filter 2215, where the low-frequency component is attenuated. This prevents overload in low frequencies. Finally, the output signal of the high-pass filter 2215 is output to the outside through the output terminal 2219.
[0200]
Further, as shown in FIGS. 22B and 22C, the high-pass filter 2215 may be arranged before or after the delay 2213.
[0201]
As described above, the overtone generation device according to the present invention described in Embodiments 1 to 5 can be applied to an acoustic signal processing device for improving the bass feeling of a small speaker.
[0202]
【The invention's effect】
As described above, according to the present invention, the down-sampled signal is stored in the buffer memory, so that the required capacity of the buffer memory can be reduced, and the effect is great.
[Brief description of the drawings]
FIG. 1 is a first flowchart of a harmonic generation method according to Embodiment 1 of the present invention;
FIG. 2 is a diagram illustrating the principle of a harmonic generation method based on a zero-cross method.
FIG. 3 is a block diagram of a basic harmonic generation device.
FIG. 4 is a diagram illustrating the operation of a basic harmonic generation device.
FIG. 5 is a second flowchart of the harmonic generation method according to the first embodiment of the present invention;
FIG. 6 is an operation explanatory diagram of the overtone generation device according to the first embodiment of the present invention;
FIG. 7 is a block diagram (1) of a harmonic generation device according to the first embodiment of the present invention;
FIG. 8 is a block diagram (2) of the harmonic generation device according to the first embodiment of the present invention.
FIG. 9 is an explanatory diagram of zero cross detection using linear interpolation.
FIG. 10 is a diagram showing a specific example of input and output in the upsampling means.
FIG. 11 is a flowchart of an overtone generation method according to the second embodiment of the present invention.
FIG. 12 is an explanatory diagram of an operation of the harmonic generation device according to the second embodiment of the present invention;
FIG. 13 is a block diagram of a harmonic generation device according to a second embodiment of the present invention.
FIG. 14 is a diagram illustrating an up-sampling output in second harmonic generation.
FIG. 15 is a diagram showing an up-sampling output in third harmonic generation.
FIG. 16 is a block diagram of a harmonic generation device according to a third embodiment of the present invention.
FIG. 17 is a detailed configuration diagram of a harmonic generation device according to Embodiment 3 of the present invention.
FIG. 18 is a block diagram (1) of a harmonic generation device according to Embodiment 4 of the present invention.
FIG. 19 is a block diagram (2) of a harmonic generation device according to a fourth embodiment of the present invention.
FIG. 20 is a block diagram (3) of an overtone generation device according to Embodiment 4 of the present invention;
FIG. 21 is a block diagram of a harmonic generation device according to a fifth embodiment of the present invention.
FIG. 22 is a block diagram of a harmonic generation device according to a sixth embodiment of the present invention.
FIG. 23 is a diagram illustrating the principle of frequency conversion.
FIG. 24 is a block diagram of a conventional frequency converter.
FIG. 25 is an explanatory diagram of an address resetting method based on a zero-cross point.
[Explanation of symbols]
301, 701, 1301, 1601, 1801, 101, 2218, 2411 Input terminals
702, 1302, 1602, 1802, 2102 Down sampling means 303, 703, 1303, 1603, 1803a to 1803c, 2103a to 2103c Zero cross detection means
304, 704, 1304, 1604, 1804, 2104a to 2104c Buffer memory
305, 705, 1305, 1605a, 1805a to 1805c, 2105a to 2105c Address management means
706, 1306, 1606, 1806a to 1806c, 2106a to 2106c Up-sampling means
707, 1807a to 1807c, 2107a to 2107c Thinning means
308, 708, 1308, 1608, 1808, 2108, 2219, 2418 Output terminals
1611 Sub-filter operation unit
1612 Sub-filter coefficient selection unit
1809a-1809c, 2109a-2109c Multiplier
1810, 2110, 2217, 2417 Adder
2112a-2112c Bandpass filter
2213 Delay
2214 Low-pass filter
2215 High-pass filter
2216 Overtone generator
2413 Zero-cross detection circuit
2414 RAM
2415 Read address counter
2416 Write address counter

Claims (5)

A harmonic generation method for generating an overtone of an input signal,
After performing downsampling on the input signal, store it in the buffer memory,
Up-sampling is performed on the signal read from the buffer memory,
A harmonic generation method, wherein a harmonic is generated for the up-sampled signal by a time axis compression operation. A harmonic generation method for generating an overtone whose frequency is k times (k is a natural number) with respect to an input signal,
After performing downsampling on the input signal of length M (M is a natural number), store it in the buffer memory,
The signal read from the buffer memory is up-sampled, and a signal of length M × k is extracted.
A harmonic generation method characterized by generating a harmonic having a length M by extracting a signal at a rate of one sample out of k samples from the up-sampled signal. A harmonic generation method for generating an overtone whose frequency is k times (k is a natural number) with respect to an input signal,
After down-sampling the input signal, the input signal is stored in a buffer memory at an update speed p (p is a natural number) of a write address,
A method for generating harmonics by upsampling a signal read out from the buffer memory at a read address update rate of p × k at a rate of one sample out of k samples. An overtone generation device that generates an overtone of the input signal,
Downsampling means for performing a thinning process on the input signal,
Zero-crossing detection means for detecting a zero-crossing point for a predetermined signal;
A buffer memory for storing an output signal of the downsampling means;
Address management means for setting a read address from the buffer memory based on information of the zero-cross point detected by the zero-cross detection means and a magnification of an overtone to be generated;
Upsampling means for performing an interpolation process of a signal with respect to an output signal from the buffer memory,
The output signal of the up-sampling unit, according to the degree of harmonics to be generated, performing a thinning process, comprising a thinning unit to generate an output signal,
In the zero-cross detection means, the predetermined signal to be detected for a zero-cross point is an input signal to the down-sampling means, or a signal stored in the buffer memory, or an input signal to the buffer memory, or An overtone generation device, which is one of an output signal from the buffer memory, an output signal from the upsampling unit, and an output signal from the thinning unit. An overtone generation device that generates an overtone of the input signal,
Downsampling means for performing a thinning process on the input signal,
Zero-crossing detection means for detecting a zero-crossing point for a predetermined signal;
A buffer memory for storing an output signal of the downsampling means;
Address management means for setting a read address from the buffer memory based on information of the zero-cross point detected by the zero-cross detection means and an order of a generated harmonic;
Upsampling means for selecting a filter coefficient used in upsampling from the information of the read address from the address management means, performing signal interpolation processing and generation of harmonics on the output signal from the buffer memory, and generating an output signal And
In the zero-cross detection means, the predetermined signal to be detected for a zero-cross point is an input signal to the down-sampling means, or a signal stored in the buffer memory, or an input signal to the buffer memory, or An overtone generation device, which is either an output signal from the buffer memory or an output signal from the upsampling unit.

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