JP2004328163A - Phase lock discrimination circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase lock discrimination circuit capable of discriminating whether or not a phase lock state is established in various frequency regions independently of a converging phase difference between a reference signal and a comparison signal in a PLL circuit. <P>SOLUTION: Comparator circuits (91, 92) compare a phase difference between the reference signal (11) of the PLL circuit and the comparison signal (21) of the PLL circuit with a period of any of the signals whose phase is advanced more, and when the phase difference exceeds the period, an output circuit (93) generates an out of phase lock signal for denoting that the phase lock state between the reference signal (11) and the comparison signal (21) is unlocked. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a phase lock determination circuit, and more particularly to a phase lock determination circuit that determines whether a reference signal and a comparison signal of a PLL (Phase Locked Loop) circuit are in a phase locked state.
[0002]
[Prior art]
Conventionally, there are an analog type and a digital type as a phase lock determination circuit for determining whether or not a reference signal and a comparison signal of a PLL circuit are in a phase locked state.
[0003]
In the following, each of the conventional example (1) (general PLL circuit), the conventional example (2) (analog phase lock determination circuit), and the conventional example (3) (digital phase lock determination circuit) will be described. The configuration and operation will be described.
General PLL circuit FIG. 4 shows an example in which a conventional analog phase lock determination circuit is connected to a general PLL circuit.
[0004]
The PLL circuit 100 shown in FIG. 1 includes a frequency divider 1, a frequency phase comparator 3, a charge pump circuit 4, a loop filter 5, and a voltage controlled oscillator (VCO) 6, which are connected in this order. 2 is connected between the voltage controlled oscillator 6 and the other input terminal of the frequency / phase comparator 3 which is different from the frequency divider 1 to form a feedback loop.
[0005]
In operation, first, the frequency divider 1 divides the frequency of the PLL input signal 10 input to the PLL circuit 100 and supplies the frequency-divided signal as the reference signal 11 to the frequency-phase comparator 3. Is divided and applied to the frequency / phase comparator 3 as a comparison signal 21.
[0006]
The frequency phase comparator 3 compares the reference signal 11 with the comparison signal 21, and outputs a pump-up signal 36 when the phase of the reference signal 11 is ahead of the phase of the comparison signal 21, and outputs the pump-up signal 36. Is higher than the phase of the reference signal 11, the pump-down signal 37 is output and given to the charge pump circuit 4.
[0007]
The charge pump circuit 4 outputs pump-up and pump-down signals in accordance with the pulse widths of the input pump-up signal 36 and pump-down signal 37, respectively. It is given to the control oscillator 6.
[0008]
The voltage controlled oscillator 6 outputs the PLL output signal 60 at an output frequency controlled by the input voltage, and is fed back to the frequency phase comparator 3 as the comparison signal 21 via the frequency divider 2.
FIG. 5 shows a general configuration example of the frequency-phase comparator 3. As shown, the frequency phase comparator 3 can be configured using two D flip-flops 31 and 32, a NAND circuit 33, and two inverters 34 and 35.
[0009]
A fixed potential _VDD is applied to each terminal D of the D flip-flops 31 and 32 in the same figure, and a reference signal 11 and a comparison signal 21 are input to each clock terminal CK. The output signal from each output terminal Q is output as a pump-up signal 36 and a pump-down signal 37 via inverters 34 and 35, respectively, and is given to each reset terminal R as a reset signal via a NAND circuit, respectively. Can be
[0010]
Thus, the output from the terminal Q of the D flip-flop 31, after being set in the 'H' level corresponding to a fixed potential V _DD by striking the fixed potential V _DD at the rising edge of the reference signal 11, the comparison signal 21 And the output from the terminal Q of the D flip-flop 32 is similarly set at the rising edge of the comparison signal 21 and then reset at the rising edge of the reference signal 11.
[0011]
Since the pump-up signal 36 is a signal obtained by inverting the output from the terminal Q of the D flip-flop 31 by the inverter 34, it is reset at the rising edge of the reference signal 11 and then at the rising edge of the comparison signal 21. Set.
On the other hand, since the pump-down signal 37 is a signal obtained by inverting the output from the terminal Q of the D flip-flop 32 by the inverter 35, it is reset at the rising edge of the comparison signal 21 and then at the rising edge of the reference signal 11. Set.
[0012]
As described above, the pump-up signal 36 and the pump-down signal 37 are pulse signals corresponding to the phase difference of the reference signal 11 and the comparison signal 21 leading from the other by negative logic.
It should be noted that some common PLL circuits use a phase comparison circuit that only compares the phase of the reference signal and the comparison signal without pulling in the frequency, instead of the frequency phase comparator 3. As an example of such a phase comparison circuit, one that always outputs an output signal having a pulse width equivalent to one of the two input signals, regardless of the phase difference between the reference signal and the comparison signal that are the two input signals. (For example, see Patent Document 1).
[0013]
Analog phase lock determination circuit The analog phase lock determination circuit 7 shown in FIG. 4 determines whether the reference signal 11 and the comparison signal 21 of the PLL circuit 100 configured as described above are in a phase locked state. The determination is made using the pump-up signal 36 and the pump-down signal 37 output from the frequency-phase comparator 3. The NAND circuit 71, the transistor 72, the resistors 73 and 74, the inverter 75, and the capacitor 76 It is configured.
[0014]
In operation, the NAND circuit 71 outputs the NAND of the pump-up signal 36 and the pump-down signal 37. That is, the signal goes to the “H” level only when there is a phase difference between the reference signal 11 and the comparison signal 21. The transistor 72 is turned ON only when the signal from the NAND circuit 71 is at the “H” level, and the electric charge of the capacitor 76 flows through the resistor 73 → the transistor 72. It changes toward 'GND' with the time constant of the resistance value R1 and the capacitance C of the capacitor 76.
[0015]
Therefore, only when a large phase difference corresponding to the time width exceeding the forward threshold voltage of the inverter 75 occurs, the phase lock determination signal 70 output from the inverter 75 rises from the “L” level to the “H” level, An unlock can be detected. Conversely, when the phase difference is small, the phase lock determination signal 70 does not exceed the forward threshold voltage of the inverter 75, so that the phase lock determination signal 70 remains at the “L” level (ie, the phase lock state).
[0016]
Digital phase lock determination circuit FIG. 6 shows an example in which a conventional digital phase lock determination circuit is connected to a general PLL circuit.
The PLL circuit 200 shown in FIG. 7 has the same configuration as the PLL circuit 100 shown in FIG. 4 except that a frequency divider 86 is connected between the frequency divider 1 and the frequency / phase comparator 3. ing.
[0017]
That is, in the PLL circuit 200 of FIG. 6, the frequency divider 1, the frequency divider 86, the frequency phase comparator 3, the charge pump circuit 4, the loop filter 5, and the voltage controlled oscillator (VCO) 6 are connected in this order. , The frequency divider 2 is connected between the voltage controlled oscillator 6 and the other input terminal of the frequency / phase comparator 3 which is different from the frequency divider 1 to form a feedback loop.
[0018]
In the configuration shown in the figure, after the PLL input signal 10 is frequency-divided by the frequency divider 1, the reference signal 11 frequency-divided by the frequency divider 86 to 1 / N and the PLL output signal 60 from the voltage-controlled oscillator 6 are frequency-divided. The frequency-phase comparator 3 compares the comparison signal 21 divided by the comparator 2 with the comparison signal 21.
The digital phase lock determination circuit 8 shown in FIG. 3 determines whether the reference signal 11 and the comparison signal 21 of the PLL circuit 200 configured as described above are in a phase locked state by the frequency / phase comparator 3. The determination is made by using the pump-up signal 36 and the pump-down signal 37 output from the inverter and the output signal of the frequency divider 1. The NAND circuit 81, the D flip-flop 82, the RS flip-flop 83, the timer 84, and the AND It is composed of a circuit 85.
[0019]
As shown, the NAND circuit 81 outputs the NAND of the pump-up signal 36 and the pump-down signal 37, similarly to the NAND circuit 71 in the analog phase lock determination circuit 7 shown in FIG. This output is input to the terminal D of the D flip-flop 82.
[0020]
The output signal of the frequency divider 1 is supplied to the input terminal IN of the timer 84 as a timer input signal 841, and the timer input signal is inputted to the D flip-flop 82 at the falling edge of the output signal of the frequency divider 1. The inverted signal of the signal 841 is input to the terminal CK of the D flip-flop 82.
[0021]
Further, the output terminal Q of the D flip-flop 82 is connected to the set terminal S of the RS flip-flop, and the inverted output terminals XQ of the D flip-flop 82 and the RS flip-flop 83 are connected to the timer 84 via the AND circuit 85. Connected to reset terminal R.
[0022]
The output terminal OUT of the timer 84 is connected to the reset terminal R of the RS flip-flop 83.
When the frequency divider 86 is driven at the rising edge of the output signal of the frequency divider 1, the reference signal 11 output from the frequency divider 86 changes in synchronization with the rising edge of the output signal of the frequency divider 1. By operating the flip-flop 82 at the falling edge of the output signal 841 of the frequency divider 1, the phase difference signal output from the NAND circuit 81 is reduced to half of the cycle of the output signal of the frequency divider 1 (timer input signal 841). Is monitored as a threshold value, and when the phase difference exceeds the threshold value, it is possible to detect a phase lock loss.
[0023]
An operation example of the phase lock determination circuit 8 having the above configuration will be described below with reference to a time chart shown in FIG.
7, the input signal 841, the reference signal 11, the comparison signal 21, the output of the NAND circuit 81, the outputs Q and XQ of the D flip-flop 82, and the outputs of the RS flip-flop 83 are shown in order from the top. Q, XQ, the terminal R of the timer 84, the output terminal OUT of the timer 84, and the operation of the timer 84 are shown.
[0024]
In the illustrated example, the reference signal 11 is a signal obtained by dividing the frequency of the timer input signal 841 by the frequency divider 86 having the frequency division ratio N = 4. The timer 84 operates when the signal input to the terminal R is at the “L” level, and is reset and stops operating when the signal is at the “H” level. In the example shown in the figure, the timer 84 operates so as to set the signal of the output terminal OUT to the “H” level when the rising edge of the timer input signal 841 has been counted two times after the start of the operation. The signal is held when the input signal of the terminal R of the timer 84 is at the "L" level, and cleared when the input signal is at the "H" level.
[0025]
Paying attention to the reference signal 11 and the comparison signal 21 in the same figure, since the phase of the two is shifted, the output of the NAND circuit 81 gradually spreads in the order of the pulse width (1) → (2) → (3). go.
Since the pulse width {circle around (1)} is equal to or less than a half cycle of the timer input signal 841, the output Q of the D flip-flop 82 remains at the “L” level.
[0026]
Since the pulse widths (2) and (3) are equal to or longer than a half cycle of the timer input signal 841, the output Q of the D flip-flop 82 is set to the “H” level and the next timer input signal 841 Reset by the falling edge of
In this case, the output Q of the RS flip-flop 83 is set to the “H” level at the same time as the output Q of the D flip-flop 82, but the reset is performed based on a signal from the output terminal OUT of the timer 84.
[0027]
The timer 84 is for adjusting the pulse width of the phase lock determination signal 80 (the output Q of the RS flip-flop 83) when detecting the phase lock loss, and is compared with the reference signal 11 output from the NAND circuit 81. Even if the pulse widths of the phase difference from the signal 21 are different as shown in (2) and (3), it is possible to indicate that the phase is out of lock with a fixed pulse width.
[0028]
[Patent Document 1]
JP-A-9-130238 (Summary, FIG. 1)
[0029]
[Problems to be solved by the invention]
As described above, in the conventional analog and digital phase lock determination circuits, the phase difference between the reference signal 11 and the comparison signal 21 based on the pump-up signal 36 and the pump-down signal 37 output from the frequency-phase comparator 3 Is monitored at a certain threshold.
[0030]
That is, for the pulse width that increases or decreases according to the phase difference between the rising edges of the reference signal 11 and the comparison signal 21, the forward threshold voltage of the inverter 75 is used as a constant threshold in the case of the analog method, and Detects out of phase lock by monitoring using a half cycle of the timer input signal 841.
[0031]
In this case, in both systems, the phase of the reference signal and the phase of the comparison signal at the time of locking must be once matched (that is, the convergence phase difference must be zero).
However, in a PLL circuit that handles various frequencies, it has conventionally been difficult to make the phase difference between the reference signal and the comparison signal coincide in the entire frequency region.
[0032]
In addition, since the analog phase lock determination circuit 7 includes a resistor, a capacitor, and a transistor, not only is the detection accuracy low, but also it is difficult to switch the detection width and the extension time according to the frequency handled by the PLL circuit. there were.
On the other hand, in the digital phase lock determination circuit 8, since it is necessary to use a signal having a higher frequency than the reference signal 11 input to the frequency phase comparator 3 of the PLL circuit 200 as the timer input signal 841, the frequency divider 86 Is required, and the circuit scale of the PLL circuit 200 including the phase lock determination circuit 8 increases. For this reason, when handling high frequencies, power consumption also increases.
[0033]
Therefore, the present invention provides a phase lock determination circuit capable of determining whether or not a phase lock state is established in various frequency regions regardless of a convergence phase difference between a reference signal of a PLL circuit and a comparison signal. That is the purpose.
It is another object of the present invention not to increase the circuit scale of a PLL circuit including a phase lock determination circuit.
[0034]
[Means for Solving the Problems]
In order to achieve the above object, a phase lock determination circuit according to the present invention includes a comparator for comparing a phase difference between a reference signal of a PLL circuit and a comparison signal of the PLL circuit with a period of a signal whose phase is advanced. And an output circuit for generating, when the phase difference exceeds the period, a phase lock loss signal indicating that a phase lock state between the reference signal and the comparison signal has been released. And
[0035]
That is, while the phase locked state between the reference signal of the PLL circuit and the comparison signal of the PLL circuit is maintained, the phase difference between the reference signal and the comparison signal is equal to the period of the signal whose phase is advanced. However, if the phase lock state is lost and the frequency of the reference signal and the frequency of the comparison signal deviate from each other, the phase difference gradually increases, and the period, which is a threshold, is eventually reduced. At this time, it is determined that the phase lock state has been released.
[0036]
As a matter of course, it is determined that the phase locked state is maintained until it is determined that the phase locked state is released.
As described above, comparing the phase difference between the reference signal and the comparison signal with the cycle of the signal whose phase is advanced leads to monitoring the respective frequencies of the reference signal and the comparison signal with each other. Therefore, it is not necessary to once match the phases of the reference signal and the comparison signal in the phase locked state (that is, to make the convergence phase difference zero) as in the related art.
[0037]
In addition, since one of the periods in which the phase of the reference signal and the comparison signal is advanced is used as the threshold for determining the loss of the phase lock, it can be applied to a PLL circuit that handles various frequencies. is there.
Thus, regardless of the presence or absence of the convergence phase difference between the reference signal and the comparison signal, it is possible to determine the phase locked state in a wide frequency range.
[0038]
The above-mentioned phase difference only needs to be detected by the frequency phase comparator in the PLL circuit based on the reference signal and the comparison signal.
Further, the comparison circuit has a first comparison unit that compares the phase difference with the cycle of the reference signal, and a second comparison unit that compares the phase difference with the cycle of the comparison signal. The output circuit may generate the out-of-phase signal based on a comparison result of the first comparison unit or the second comparison unit.
[0039]
In this case, the first and second comparison units may be D flip-flops, and the output circuit may be an AND circuit.
As described above, the phase lock determination circuit can be configured by a small-scale circuit using only two D flip-flops and one AND circuit.
[0040]
Therefore, in particular, as compared with the conventional digital phase lock determination circuit, the circuit scale can be reduced because an extra frequency divider for determining the phase lock state is not required. Even with a PLL circuit that handles high frequencies, an increase in power consumption can be suppressed.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a case where a phase lock determination circuit 9 is connected to a PLL circuit 300 as an embodiment of a phase lock determination circuit according to the present invention.
The PLL circuit 300 shown in FIG. 2 includes a frequency divider 1, a frequency phase comparator 3, a charge pump circuit, similarly to the general PLL circuit 100 to which the conventional analog phase lock determination circuit 7 shown in FIG. 4, a loop filter 5, and a voltage controlled oscillator (VCO) 6 are connected in this order, and the frequency divider 2 is different from the voltage controlled oscillator 6 and the frequency divider 1 of the frequency phase comparator 3 on the other side. It is connected between the input terminals and forms a feedback loop.
[0042]
Further, the phase lock determination circuit 9 includes two D flip-flops 91 and 92 and an AND circuit 93.
As shown in the figure, the reference signal 11 output from the frequency divider 1 and supplied to the frequency-phase comparator 3 is input to a terminal CK of the D flip-flop 91, and the pump-up signal 36 output from the frequency-phase comparator 3 is input to the D flip-flop 91. Input to terminal D.
[0043]
On the other hand, the comparison signal 21 output from the frequency divider 2 and supplied to the frequency-phase comparator 3 is input to the terminal CK, and the pump-down signal 37 output from the frequency-phase comparator 3 is output to the terminal D to the D flip-flop 92. Is input to
The output terminals Q of the two D flip-flops 91 and 92 are connected to an AND circuit 93.
[0044]
Note that, unlike the conventional digital phase lock determination circuit 8 shown in FIG. 6, the phase lock determination circuit 9 of the present embodiment does not use a signal having a higher frequency than the reference signal 11. A frequency divider corresponding to the frequency divider 86 is unnecessary.
In operation, the first D flip-flop 91 taps the pump-up signal 36 input to the terminal D at the rising edge of the reference signal 11 input to the terminal CK.
[0045]
Further, the second D flip-flop 92 taps the pump-down signal 37 input to the terminal D at the rising edge of the comparison signal 21 input to the terminal CK.
Further, the AND circuit 93 obtains the logical product of the outputs of the terminals Q of the two D flip-flops 91 and 92. Therefore, when the phase lock determination signal 90 output from the AND circuit 93 is at the “H” level, the phase lock state is established. When the signal is at the “L” level, it indicates that the phase is out of lock.
[0046]
FIG. 2 shows an operation in which the frequency-phase comparator 3 resets the pump-up signal 36 at the rising edge of the reference signal 11 and sets it at the rising edge of the comparison signal 21, that is, the phase of the reference signal 11 FIG. 5 is a time chart showing a process in which the phase lock determination circuit 9 of FIG. 1 detects a phase lock loss when the frequency of the reference signal 11 or the comparison signal 21 is shifted when the phase advances.
[0047]
The time chart of FIG. 8 shows, from the top, the reference signal 11, the comparison signal 21, the pump-up signal 36, the pump-down signal 37, the output signal of the flip-flop 91, the output signal of the flip-flop 92, and the phase lock determination signal 90. ing.
Further, for convenience of description, broken lines T1 to T9 and alternate long and short dash lines t1 to t8 are drawn in accordance with rising edges of the reference signal 11 and the comparison signal 21.
[0048]
As shown, when the phase of the reference signal 11 is ahead of the phase of the comparison signal 21, the pump-down signal 37, which is the output of the frequency-phase comparator 3, is always at the "H" level, and the pump-up signal 36 is at the "H" level. The time of the L ′ level corresponds to the phase difference between the reference signal 11 and the comparison signal 21. That is, the phase difference between the reference signal 11 and the comparison signal 21 gradually increases in the order of the interval between T1 and t1, the interval between T2 and t2, the interval between T3 and t3,. It appears as the time when the signal 36 is at the "L" level.
[0049]
Paying attention to the output signal of the D flip-flop 91, since each rising edge T1 to T7 of the reference signal 11 is a clock when the pump-up signal 36 is at the “H” level, the output signal of the D flip-flop 91 is Remains at the “H” level.
Then, after the rising edge T7 of the reference signal 11, the next rising edge T8 of the reference signal 11 comes before the rising edge t7 of the comparison signal 21, so that the pump-up signal 36 is at the "L" level. The period exceeds the period of the reference signal 11 (the interval between the rising edges T7 and T8).
[0050]
In this case, at the rising edge T8 of the reference signal 11, since the pump-up signal 36 is at the "L" level, the output signal of the D flip-flop 91 is inverted from the "H" level to the "L" level as shown in the figure. Similarly, the phase lock determination signal 90 output from the AND circuit 93 is also inverted from “H” level to “L” level. This makes it possible to detect the phase lock loss.
[0051]
FIG. 3 shows an operation in which the frequency-phase comparator 3 resets the pump-down signal 36 at the rising edge of the comparison signal 21 and sets it at the rising edge of the reference signal 11, that is, When the phase of the reference signal 11 advances with respect to the phase of the reference signal 11 and the frequency of the reference signal 11 or the comparison signal 21 shifts, the phase lock determination circuit 9 of FIG. This is shown in FIG.
[0052]
Also in FIG. 3, dashed lines T1 to T8 and alternate long and short dash lines t1 to t9 are drawn in synchronization with the rising edges of the reference signal 11 and the comparison signal 21, as in FIG.
As shown in FIG. 3, when the phase of the comparison signal 21 is ahead of the phase of the reference signal 11, the pump-up signal 36, which is the output of the frequency-phase comparator 3, always becomes “H” level, and the pump-down signal 36 Corresponds to the phase difference between the comparison signal 21 and the reference signal 11. That is, the phase difference between the comparison signal 21 and the reference signal 11 gradually increases in the order of the interval between t1 and T1, the interval between t2 and T2, and the interval between t3 and T3. It appears as a time that is at the L ′ level.
[0053]
Therefore, paying attention to the output signal of the D flip-flop 92, the next rising edge t8 of the comparison signal 21 comes after the rising edge t7 of the comparison signal 21 and before the rising edge T7 of the reference signal 11. The period during which the pump-down signal 37 is at the “L” level exceeds the cycle of the comparison signal 21 (the interval between the rising edges t7 and t8).
[0054]
In this case, at the rising edge t8 of the comparison signal 21, since the pump-down signal 37 is at the "L" level, the output signal of the D flip-flop 92 is inverted from the "H" level to the "L" level as shown. Similarly, the phase lock determination signal 90 output from the AND circuit 93 is also inverted from “H” level to “L” level. This makes it possible to detect the phase lock loss.
(Appendix 1)
A comparison circuit that compares a phase difference between a reference signal of the PLL circuit and a comparison signal of the PLL circuit with a cycle of a signal whose phase is advanced;
An output circuit for generating, when the phase difference exceeds the period, a phase lock loss signal indicating that a phase lock state between the reference signal and the comparison signal has been lost. Lock determination circuit.
(Supplementary Note 2) In Supplementary Note 1,
The phase lock determination circuit, wherein the phase difference is detected by a frequency phase comparator in the PLL circuit based on the reference signal and the comparison signal.
(Supplementary Note 3) In Supplementary note 1 or 2,
The comparison circuit has a first comparison unit that compares the phase difference with the cycle of the reference signal, and a second comparison unit that compares the phase difference with the cycle of the comparison signal. A phase lock determination circuit, wherein a circuit generates the phase lock loss signal based on a comparison result of the first comparison unit or the second comparison unit.
(Supplementary Note 4) In supplementary note 3,
The first and second comparators are each a D flip-flop, and the output circuit is an AND circuit.
[0055]
【The invention's effect】
As described above, according to the phase lock determination circuit of the present invention, the comparison circuit compares the phase difference between the reference signal of the PLL circuit and the comparison signal of the PLL circuit with the cycle of the signal whose phase is advanced. When the phase difference exceeds the period, the output circuit is configured to generate a phase lock loss signal indicating that the phase lock state between the reference signal and the comparison signal has been released. Irrespective of the convergence phase difference between the reference signal and the comparison signal, it is possible to determine whether or not the phase is locked in various frequency ranges.
[0056]
In addition, since the above-described comparison circuit can be constituted by two D flip-flops and the output circuit can be constituted by an AND circuit, the phase lock judgment circuit can be constituted by a small-scale circuit. The circuit scale of the PLL circuit including the circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a phase lock determination circuit according to the present invention.
FIG. 2 is a diagram showing an operation time chart (1) in the embodiment of the phase lock determination circuit of FIG. 1 according to the present invention;
FIG. 3 is a diagram showing an operation time chart (2) in the embodiment of the phase lock determination circuit of FIG. 1 according to the present invention;
FIG. 4 is a block diagram showing a configuration of a conventional analog phase lock determination circuit.
FIG. 5 is a block diagram showing a configuration of a frequency phase comparator used in a general PLL circuit.
FIG. 6 is a block diagram showing a configuration of a conventional digital phase lock determination circuit.
FIG. 7 is a diagram showing an operation time chart of the phase lock determination circuit of FIG. 6;
[Explanation of symbols]
1, 2, 85 frequency divider 3 frequency phase comparator 4 charge pump circuit 5 loop filter 6 voltage controlled oscillator (VCO)
7, 8, 9 Phase lock determination circuit 10 PLL input signal 31, 32, 82, 91, 92 D flip-flop 60 PLL output signal 70, 80, 90 Phase lock determination signal 71, 81 NAND circuit 83 RS flip-flop 84 Timer 85 , 93 AND circuits 100, 200, 300 In the PLL circuit diagram, the same reference numerals indicate the same or corresponding parts.

Claims (3)

A comparison circuit that compares a phase difference between a reference signal of the PLL circuit and a comparison signal of the PLL circuit with a cycle of a signal whose phase is advanced;
An output circuit for generating, when the phase difference exceeds the period, a phase lock loss signal indicating that a phase lock state between the reference signal and the comparison signal has been lost. Lock determination circuit. In claim 1,
The phase lock determination circuit, wherein the phase difference is detected by a frequency phase comparator in the PLL circuit based on the reference signal and the comparison signal. In claim 1 or 2,
The comparison circuit has a first comparison unit that compares the phase difference with the cycle of the reference signal, and a second comparison unit that compares the phase difference with the cycle of the comparison signal. A phase lock determination circuit, wherein a circuit generates the phase lock loss signal based on a comparison result of the first comparison unit or the second comparison unit.

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