JP2004328005A - Semiconductor memory element, and semiconductor memory and control method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory element suitable for high integration in a small area, and a semiconductor memory, and a control method for the semiconductor memory. <P>SOLUTION: The semiconductor memory element includes a source area and a drain area. The drain area 77 is formed above or below the source area 76 via an insulating film, while the source area is connected to the drain area via a channel area 78. The channel area is connected to a gate electrode 80 via the gate insulating film 81. The semiconductor memory element also has a carrier enclosing area 79 near the channel area, and carriers are retained in the carrier enclosing area to change the threshold voltage of the semiconductor element and execute a memory operation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, a semiconductor memory device, and a control method thereof.

  Conventionally, a nonvolatile memory device such as a flash EEPROM has been realized by using a MOSFET having a floating gate and a control gate. The information is stored and read out by utilizing the fact that the threshold voltage of the MOSFET changes by accumulating carriers in the floating gate. Generally, polycrystalline silicon is used for the floating gate. By using this MOSFET with a floating gate, one-bit information can be stored over a long period with only one transistor. As a memory cell structure of a flash EEPROM, a conventional structure and a contactless cell structure described in Nikkei Electronics no. 444 pp 151-157, 1988 are exemplified.

  Other prior art related to the present invention include K. Yano et al, IEEE International Electron Devices Meeting pp 541-544, 1993, and K. Yano et al, IEEE International Solid-State Circuits Conference pp 266-267, 1996. A single-electron memory using the described polycrystalline silicon is given. In this technique, a channel as a current path and a storage region for capturing electrons are simultaneously formed by a polycrystalline silicon thin film. Information is stored by utilizing the fact that the threshold voltage changes when electrons are captured in the storage area. The feature is that one bit is stored by storing one electron. By utilizing the crystal grains of polycrystalline silicon, a structure that is effectively smaller than the dimension processed is realized, and operation is possible even at room temperature.

  In a flash EEPROM, in order to realize a desired threshold change in the operation of injecting and extracting carriers (writing and erasing operations) into the floating gate, the storage state is monitored after a high voltage (or low voltage) is applied, and the desired state is monitored. A verify operation is performed in which a voltage is applied again to a cell in which a threshold change has not been realized to adjust the threshold.

  Conventional techniques include T. Tanaka et al, IEEE J. Solid-State Circuits, vol. 29, no.11 pp. 1366-1372, 1994, and K. Kimura et al, IEICE Trans. Electron., Vol. E78. -C No.7 The verification operation described in pp832-837, 1995 is given.

T. Tanaka et al, IEEE J. Solid-State Circuits, vol. 29, no.11 pp. 1366-1372, 1994

  Due to advances in microstructure, memory cells of various memories such as DRAM, SRAM, and flash memory have been reduced in area. If a memory cell can be configured with a small area, the chip area can be reduced and the yield can be improved. Many chips can be obtained on the same wafer, which is advantageous in terms of cost. Also, since the wiring length can be shortened, there are many advantages such as high-speed operation. is there.

  The correspondence between the processing size and the cell area is largely determined by the memory system. For example, assuming that the processing size is F, a unit cell is formed of 8F2 for a folded bit line type DRAM and 6F2 for an AND type flash memory. At present, a flash memory of one cell can realize a cell having the smallest area with one transistor, but this is almost the limit in a memory having a MOS structure formed on a substrate surface. If a memory cell smaller than this is to be constructed, a three-dimensional structure is indispensable. Furthermore, assuming that the memory cell is reduced by using the three-dimensional structure, and when the data line pitch or the word line pitch is made smaller than the minimum of 2F, how to wire the data lines and word lines and connect them to peripheral circuits, Another important issue is how to control the cell array by a peripheral circuit.

  On the other hand, utilizing the fact that Coulomb repulsion works effectively when moving electrons into and out of minute dots of metal or semiconductor, a single-electron element that controls electrons one by one is, in principle, a very small element of about 10 nm. It has advantages such as operation with a small structure and low power consumption. A single-electron memory, which is one of the single-electron elements, is a memory that can store information with a small number of stored electrons. One element can store one or more bits of information, and the stored charge can be stored in units of one. Because it is controllable, there is a possibility that it can operate even at the nanometer level. Further, since the number of stored electrons is small, a dramatic improvement in the rewriting time and the number of rewriting can be expected. However, in actual device fabrication, processing dimensions are limited by lithography technology and the like. Further, in the conventional device, no device structure has been proposed that takes advantage of the advantage that the size of the lead-out portion such as the source region and the drain region is large and can be integrated and reduced.

  In addition, the inventors have prototyped and evaluated a single-electron memory that operates at room temperature, and in the process, the time required to accumulate electrons even when the same write voltage is applied to the same element for the same time. Was observed to be mixed. Conversely, it has been found that when the same write voltage is applied for the same time, the number of accumulated electrons differs from time to time. This can be interpreted as that the single-electron element uses a small number of electrons for operation, so that the stochastic behavior of a phenomenon such as tunneling or thermal excitation appears directly.

  2. Description of the Related Art A semiconductor memory has achieved a large storage capacity by improving the storage density by promoting miniaturization. However, as the miniaturization progresses, the cost of manufacturing equipment increases. By performing multi-value storage in which two or more bits are stored in one cell, high-density storage becomes possible without miniaturization. In multilevel storage, it is most important that many storage states can be clearly distinguished in writing, erasing, and reading.

  Further, the single-electron memory is required to handle a small amount of electric charge, and the peripheral circuits are required to have low noise. Differential amplifiers are widely used as sense amplifiers in semiconductor memories. Here, as the positional relationship between the sense amplifier and the data line, there are known an open type in which a pair of data lines are arranged on both sides of the sense amplifier and a folded type in which a pair of data lines are arranged in the same direction. The open type has the advantage that the memory cells can be arranged at all the intersections of the data line and the word line and has a high degree of integration, but has the disadvantage that the noise due to the word line drive is large. On the other hand, the folded type has an advantage that noise due to word line driving is small, but there is a problem that memory cells cannot be arranged at all intersections of data lines and word lines, and the degree of integration is low.

  In addition to the sense amplifier, peripheral circuits having a large area include a register for temporarily holding data to be written to a memory cell at the time of writing, a register for holding a flag indicating that writing has been completed at the time of write verification, and a register for writing. There is a circuit that compares the value read from the memory cell after the operation with the value of the write end flag to rewrite the flag.

  SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a single-electron memory cell having a small area and suitable for high integration, a semiconductor memory device resistant to variation in operation due to stochastic phenomena, and a control method therefor, which break the conventional limitations. And a semiconductor memory device suitable for multi-value storage and a control method therefor. Further, a small-area peripheral circuit that does not impair the features of a small-area, highly-integrated single-electron memory cell, and a charge amount to be handled are It is an object of the present invention to provide a peripheral circuit with low noise suitable for a single electronic memory which is low in noise and low in noise and a control method thereof.

  The present invention is characterized in that it can be manufactured with a small area by providing a source region and a drain region above and below and running a channel in a vertical direction.

  More specifically, a semiconductor device according to a representative embodiment of the present invention has a source and a drain region, and the drain region is provided above or below the source region via an insulating film, and the source region is a channel region. And the channel region is connected to the gate electrode via the gate insulating film, and has a carrier confinement region near the channel region. Storage is performed by changing the threshold voltage of the semiconductor element by holding carriers in the carrier confinement region.

  In addition, an embodiment in which a plurality of gate electrodes are provided in the vertical direction and a channel is provided on the side surface of the step can be manufactured with a small area. A plurality of gate electrodes provided, a channel region provided on a side surface of the gate electrode via an insulating film, a source region connected to the drain region via the channel region, and a carrier near the channel region. It has a confinement region and performs storage by changing the threshold voltage of the semiconductor element by holding carriers in the carrier confinement region. The carrier confinement region is formed from semiconductor or metal fine particles having an average minor axis of 10 nm or less. It is characterized by becoming.

  Further, the present invention is characterized in that by performing a verify operation, an accurate storage operation of a storage device using a storage element in which a stochastic phenomenon clearly appears in characteristics like a single electronic element is realized.

  More specifically, a method for controlling a semiconductor device according to a representative embodiment of the present invention includes a source region and a drain region, wherein the source region is connected to the drain region via a channel region, and the channel region is an insulating film. A semiconductor memory element that has a carrier confinement region near the current path in the channel region and that changes the threshold voltage by holding the carrier in the carrier confinement region. In a semiconductor memory device having a structure in which a plurality of semiconductor memory elements are arranged in a matrix, a first step of applying a write voltage to the semiconductor memory element and reading of information stored in the element after the first step And writing again on the semiconductor memory element in which information writing in the second step is insufficient. Having a third step of applying only a voltage.

In addition, the inventors independently studied multi-valued storage, and it was better to use an element whose characteristics changed stepwise rather than an element whose characteristics continuously changed with the number of stored electrons as in a flash memory. Focusing on its advantages from the point of view, he came to the idea of using a single-electron memory that had been found to have stepwise characteristics from actual measurements.
In other words, the present invention is characterized by realizing a multi-value storage element in which the storage state can be clearly distinguished by utilizing the characteristics of a single electronic element, or a storage device using the multi-value storage element. .

  A semiconductor device according to an embodiment having this feature has a source region and a drain region, the source region is connected to the drain region via a channel region, and the channel region is connected to a gate electrode via an insulating film. A semiconductor storage element having a carrier confinement region in the vicinity of the current path in the channel region and performing storage by changing a threshold voltage by holding carriers in the carrier confinement region; In a semiconductor memory device having a structure of arranging in a matrix, one semiconductor memory element is controlled by controlling a matrix of semiconductor memory elements by data lines and word lines and using a plurality of values for a write voltage applied to a word line. To store two or more bits.

  Further, as a peripheral circuit having a small area and being strong against noise, each local data line of memory cells stacked vertically is connected to a global data line via a separate selection MOS, and read and written in a time multiplex manner. By doing so, peripheral circuits such as global data lines and sense amplifiers are shared to prevent an increase in area. In addition, by utilizing the hierarchical data lines and the fact that memory cells (floating electrode cells) are non-destructive for reading, a memory is provided at all intersections of word lines and data lines while having a folded data line structure. Allows cells to be placed. Specifically, when one of the paired global data lines is read out to the sense amplifier, the influence can be eliminated by turning off the selection MOS of the local data line connected to the other global data line. it can. Thus, low-noise reading can be performed without sacrificing high integration of the stacked memory cells.

  In addition, the same dummy cell is used as a threshold voltage reference in any of the read, write verify, and erase verify operations, thereby improving the margin for noise.

  As a method of further reducing the area of the peripheral circuit, a register that temporarily holds data to be written to a memory cell at the time of writing and a register that holds a flag indicating that writing has been completed at the time of write verification are also used. The specific operation will be described below. In this description, the case where the threshold voltage of the memory cell is high is “1”, and the case where the threshold voltage is low is “0”. The logic is positive logic, and the high level is "1" and the low level is "0". Writing is performed by temporarily lowering (erasing) the threshold voltages of all the memory cells, and then applying a high voltage to the word lines to raise the threshold values of the memory cells. At this time, in the memory cell to which "0" is to be written, the voltage of the data line and the source line is increased, and the voltage difference between the word line and the word line is relatively reduced to suppress the rise of the threshold voltage. Of course, these polarities may be reversed.

  Data obtained by inverting “1” and “0” is input to a register that temporarily holds data to be written to a memory cell at the time of writing. This is directly regarded as a write end flag. That is, when writing “1”, the value of the register is “0”, which indicates that writing “1” is not completed, and when writing “0”, the value of the register is “1”. This indicates that writing “1” is not necessary from the end or from the beginning. Therefore, only when the value of the memory cell is "1" after the write operation, "1" may be written to the register as it is.

  This eliminates the need to prepare both a register for temporarily storing data to be written and a write end flag, compare the respective values, and then rewrite the value of the write end flag. One "nMOS" is used as the "circuit passing only" 1 "". The global data line is connected to the gate of the nMOS, the drain is connected to the high level of the power supply, and the source is connected to the input of the register. Then, when the value of the global data line is “1”, the nMOS is turned on, and “1” is input to the input of the register. When the value of the global data line is “0”, the nMOS remains off and the register changes. do not do. According to the “pass-through circuit for only“ 1 ””, the write end flag can be rewritten by one nMOS (even if the control pMOS is placed between the nMOS and the high level of the power supply).

  According to the present invention, it is possible to provide a semiconductor memory device having a small area and suitable for high integration and a control method thereof.

  Other means, objects and features of the present invention will be apparent from the following embodiments.

Example 1
Hereinafter, a storage element, a storage device, and a control method thereof according to a specific embodiment of the present invention will be described. For the sake of explanation, a part of the semiconductor memory device will be described. Actually, the device functions as a memory device including contacts and peripheral circuits.

  FIG. 1 is a structural diagram of a storage element according to the present embodiment. FIG. 1A is a bird's-eye view, and FIG. 1B is a cross-sectional view. The source (76) and the drain (77) are regions made of high impurity concentration n-type polycrystalline silicon, and have an SiO2 insulating film (82) therebetween. A channel portion (78) of P-type polycrystalline silicon having a thickness of 20 nm and a width of 150 nm is formed on the side surface of the SiO2 insulating film (82), and a carrier made of polycrystalline silicon is separated by a thin insulating film (87). A confinement region (79) is formed. The channel portion (78) and the carrier confinement region (79) are connected to the gate electrode (80) via the SiO2 insulating film (81). The distance between the gate electrode (80) and the carrier confinement region (79) is 30 nm.

  By separately providing the channel portion (78) and the carrier confinement region (79), it is possible to design and form each separately, as compared with the structure in which the channel portion and the carrier confinement region described later in Embodiment 3 are formed collectively. Therefore, there is a feature that there is much freedom. In particular, there is an advantage that the height and width of the potential barrier can be artificially determined by selecting the material and thickness of the insulating film (87) between the channel portion (78) and the carrier confinement region (79). In this embodiment, the source is lower than the drain and the drain, but the order may be reversed. Further, in this embodiment, the carrier is an electron, and in the following embodiments, the carrier is also an electron. However, the carrier may be a hole.

  In the storage element of this embodiment, the source (76) and drain (77) regions are vertically overlapped, and the area can be reduced accordingly. Further, the channel area (78) also has a vertically running structure, so that the element area is reduced. More storage can be performed by repeatedly arranging the storage elements of this embodiment. This is the same for the storage elements of the following embodiments.

  The operation of the storage element of this embodiment will be described. Writing and erasing are performed by changing the potential of the gate electrode (80). When a constant voltage is applied between the source (76) and the drain (77) and a gate voltage is applied, electrons are induced in the polycrystalline silicon thin film of the channel (78), and a current starts to flow. When a large gate voltage is applied, the potential difference between the channel region (78) and the carrier confinement region (79) increases, and eventually the electrons cross the potential barrier of the insulating film (87) by tunneling or thermal excitation. It is injected into the carrier confinement region (79). As a result, the threshold value shifts to a larger value, and the current value decreases even at the same gate voltage. Reading of information is performed by checking the magnitude of the current value. Erasing is performed by swinging the gate voltage in the reverse direction.

Next, the manufacturing process of this embodiment will be described with reference to FIG. After oxidizing the surface of the P-type substrate (86) to form a SiO2 film (84), an n-type polycrystalline silicon film, an SiO2 film, an n-type polycrystalline silicon film, and an SiO2 film are deposited in this order, and a total of four layers are deposited. The source (76), the drain (77) regions, and the SiO2 films (82) and (83) are formed by etching all at once using the photoresist as a mask (FIG. 16A). Since they are formed in a lump as described above, the increase in the number of lithography steps is small even in a laminated structure. Next, after a (amorphous) -Si of 20 nm is deposited, crystallization is performed by heat treatment. This polycrystalline silicon is etched using a photoresist as a mask, and is processed into a line connecting the source (76) and drain (77) regions to form a channel portion (78) (FIG. 16B).
In this etching step, the SiO2 film (83) provided on the source (76) and drain (77) regions prevents unnecessary shaving on the drain (77) region. Thereafter, after depositing a thin SiO2 film (87), polycrystalline silicon in the carrier confinement region (79) is deposited and etched. Then, after depositing a SiO2 film (81), an n-type polycrystalline silicon film is deposited and etched using a photoresist as a mask to form a gate electrode (80).

Example 2
FIG. 15 shows a structural diagram of a storage element according to another embodiment of the present invention. The source (1) and the drain (2) are regions made of high impurity concentration n-type polycrystalline silicon, and have an SiO2 insulating film (7) therebetween. A channel portion (3) of non-doped polycrystalline silicon having a thickness of 10 nm and a width of 20 nm is formed on the side surface of the SiO2 insulating film (7), and a plurality of silicon crystals having an average diameter of 6 nm are separated by a thin insulating film. A carrier confinement region (4) made of particles is formed. The channel portion (3) and the carrier confinement region (4) are connected to the gate electrode (4) via the SiO2 insulating film (6). The distance between the gate electrode and the carrier confinement region (4) is 30 nm. The element is provided on the SiO2 insulating film (8). The point that the element is provided on the insulating film is the same in the following embodiments unless otherwise specified. In this embodiment, the channel (3) and the carrier confinement region (4) are formed separately. However, there is also a method of integrally forming them, and this method may be adopted. This is the same in the following embodiments. Further, the SiO2 film (18) formed on the drain (2) and having the same width as the source (1) and the drain (2) is the same as the SiO2 film (83) described in the first embodiment. Prevent sharp scraping.

  The operation of the storage element according to the present embodiment, which is different from the first embodiment, will be described. In the present embodiment, when carriers are captured in the carrier confinement region (4), the capacitance between the gate electrode (5) and the channel (3) becomes smaller because the channel (3) is narrower. I can put it out. In this embodiment, three electron accumulations can be read as a threshold voltage shift of about 1V. However, a desired threshold voltage shift may be realized by increasing the channel width and preparing a large number of silicon crystal grains in the carrier confinement region to increase the number of accumulated electrons. If the channel width is increased, a large current can flow, and the lithography process is easy. The size of the carrier confinement region is 10 nm or less, and the total capacitance with the surroundings is 3 aF or less. Accordingly, even when room temperature is assumed and thermal disturbance is taken into account, the number of stable carriers in the carrier confinement region is determined in units of one. Therefore, phenomena such as excessive carriers entering and accumulated carriers coming out hardly occur. Erasing is performed by swinging the gate voltage in the reverse direction.

Example 3
FIG. 2 shows a third embodiment of the present invention. The present embodiment differs from the second embodiment only in that the channel portion and the carrier confinement region (11) are integrally formed, and the channel portion (11) is provided on both sides of the source (9) and the drain (10). different. The material of the channel portion and the carrier confinement region (11) is a non-doped polycrystalline silicon thin film having an average thickness of about 3 nm. In this embodiment, utilizing the fact that the potential undulation in the polycrystalline silicon thin film having an average thickness of 5 nm or less is severe, the channel and the carrier confinement region are naturally formed in the thin film (11). Therefore, there is an advantage that a small structure suitable for room temperature operation can be effectively realized by a simple manufacturing process. In the present embodiment, the size of the crystal grains is also suppressed to about 10 nm in the lateral direction since the thickness is about 3 nm, and the size of each carrier confinement region is also about this.

  By providing a channel portion and a carrier confinement region (11) on both sides of the source (9) and the drain (10) and controlling them with the same gate electrode (12), the channel width is effectively doubled and the channel current is reduced. There is a feature that can be taken large. When the current value is increased by increasing the channel line width, the area generally increases, but this structure does not increase the area. In particular, in the structure in which the channel portion and the carrier confinement region are provided integrally, there is a problem that a simple increase in the channel line width acts in a direction to reduce the threshold voltage fluctuation due to carrier capture. This problem does not occur when a plurality of channels are prepared.

Example 4
FIG. 3 shows a fourth embodiment of the present invention.

  The third embodiment differs from the third embodiment in that it has two drain regions and has a three-layer structure of a drain 1 (13), a source (14), and a drain 2 (15). In the structure of the present embodiment, it is possible to realize twice the storage capacity of the structure of the first embodiment without increasing the area. The source (14) is used in common, and the source (14), the drain 1 (13), the channel section connecting them and the carrier confinement region (16) are used to store data, and in addition, the source (14) and the drain 2 (15) are used. The data is also stored in the channel section and the carrier confinement area (88) connecting them. The two channel portions and the carrier confinement regions (16) and (88) are deposited and formed at the same time, and their roles differ only in the positional relationship between the source and the drain. These have the same gate electrode (17), but only one of them can be written and erased by changing the voltage of the drain 1 (13) and the drain 2 (15). In addition, since the source (14), the drain 1 (13), and the drain 2 (15) can be collectively processed, and the channel portion and the carrier confinement regions (16) (88) can be collectively processed, the number of steps is reduced. There is an advantage that the increase is small. In this embodiment, the channel portion and the carrier confinement region are formed integrally, but they may be formed separately.

Example 5
FIG. 4 shows a fifth embodiment of the present invention.

  The present embodiment is characterized in that the gate electrode has a laminated structure, unlike the first to fourth embodiments in which the source and the drain have a laminated structure. Source (21) and drain (22) regions are provided outside the laminated gate electrode 1 (19) and gate electrode 2 (20) with an SiO2 insulating film (26) therebetween. A non-doped polycrystalline silicon thin film (23) having a thickness of about 3 nm is provided in a shape connecting the source (21) and the drain (22). The thin film 23 functions as a channel portion and a carrier confinement region. The polycrystalline silicon thin film (23) is very thin and has crystal grains in an island shape, and has a high threshold voltage.

  Therefore, only the thin film portion beside the gate electrode shows conductivity when the gate voltage is applied, and the thin film portion (24) on the side surface of the gate electrode 1 (19) and the thin film portion (25) on the side surface of the gate electrode 2 (20) are etched. Although they are not separated, they become independent channel portions and carrier confinement regions, respectively. Therefore, this device can store two or more bits. In this embodiment, only two gate electrodes are stacked, but more gate electrodes may be stacked. In the structure in which the source and the drain are stacked as in the third embodiment, it is difficult to use a common structure of the drain and the drain. However, this structure has an advantage that the storage capacity can be increased by the number of stacked gate electrodes.

Example 6
FIG. 5 shows a sixth embodiment of the present invention.

  This embodiment is a storage element for storing information of 2 bits or more. The element structure and operation of the present embodiment are basically the same as the case where two elements of the third embodiment are formed, and are different only in a manufacturing method for realizing this structure.

  The manufacturing process of this embodiment will be described. After oxidizing the surface of the P-type substrate, an n-type polycrystalline silicon film, a SiO2 film, and an n-type polycrystalline silicon film are sequentially deposited, and the source (27), the drain (28), and SiO2 (31) is formed. Next, a thin Si3N4 film of 15 nm is deposited, and a SiO2 film (32) is further deposited. Thereafter, the SiO2 film and the Si3N4 film are etched using a photoresist having a hole pattern including a step at the end of the drain (27) region as a mask (FIG. 5A). At this time, the side surface (30) of the Si3N4 film appears. Next, 3 nm of a-Si is deposited on the surface of the Si3N4 film (30). At this time, when the underlayer is SiO2, the time from the start of flowing the gas source to when Si actually starts to contact the wafer surface is longer than when the underlayer is Si3 N4. Does not accumulate. Therefore, an a-Si fine wire having a width of about 15 nm is formed on the surface of the Si3N4 film (30) in a shape connecting the source (27) and the drain (28). The a-Si is crystallized by heat treatment to form a channel portion and a carrier confinement region integrally. After depositing the SiO2 film (33), an n-type polycrystalline silicon film is deposited and etched using a photoresist as a mask to form a gate electrode 1 (29) and a gate electrode 2 (34) (FIG. 5B).

  In this embodiment, two gate electrodes (29) and (34) can store data separately, and can store at least 2 bits. If multi-value storage is performed, storage of a larger number of bits is possible. This embodiment is characterized in that a fine line can be formed with good controllability. The variation between elements can be reduced, and a large threshold voltage shift can be achieved with a small number of stored electrons. In the present embodiment, a hole is formed so as to include one step at the end of the drain (28) region, but holes are formed on both sides, two channel portions and a carrier confinement region are provided, and control is performed by the same gate electrode. It may be. This structure has a feature that a large channel current can be obtained. Further, in this embodiment, only two layers of the source (27) and the drain (28) are stacked, but a three-layer structure of the drain 1, the source, and the drain 2 may be taken as in the fourth embodiment, so that higher density storage is possible. It becomes.

Example 7
FIG. 6 shows a seventh embodiment of the present invention.

  The present embodiment is different from the sixth embodiment only in that the channel portion and the carrier confinement region are separately provided, and two channel portions formed in the same hole pattern are controlled by the same gate electrode (35). different. The advantage of separately providing the channel portion and the carrier confinement region is the same as in the first embodiment. Further, by adopting a structure in which two channel portions formed in the same hole pattern are controlled by one gate electrode (35), there is a feature that processing of the gate electrode (35) is easy. The difference between the sixth embodiment and the sixth embodiment is that a step of depositing a thin SiO2 film immediately after channel deposition and forming silicon crystal grains in a carrier confinement region is included.

Example 8
FIG. 7 shows an eighth embodiment of the present invention.

  This embodiment is different from the seventh embodiment in the manufacturing process and the positional relationship between the channel portion and the carrier confinement region. The differences between the sixth embodiment and the manufacturing process will be described. After forming the source (36) and drain (37) regions, a 15 nm thin Si3N4 film (38) is deposited, a 5 nm SiO2 film (40) is deposited, and a 10 nm Si3N4 film (39) is deposited. Thereafter, the steps of depositing an SiO2 film (41) and etching the SiO2 film and the Si3N4 film using a hole pattern photoresist including a step at the end of the drain (37) region as a mask are the same as those of the sixth embodiment. The deposited film thickness of a-Si is 5 nm. In this structure, in the step of depositing a-Si, a carrier is formed on the side of the other Si3N4 film (39) beside the channel portion that can form the source (36) and the drain (37) on the side of the Si3N4 film (38). A confinement region is formed. This structure has a feature that the controllability of the distance between the channel and the carrier confinement region is good.

Example 9
FIG. 8 shows a ninth embodiment of the present invention.

  Four memory elements according to the first embodiment are arranged in a matrix, two elements share a source and a drain, and two elements share a gate electrode. The row and column can be controlled by using the two drains (42) and (43) as data lines and the two gates (46) and (47) as word lines. The number of elements sharing a source and a drain may be increased, in other words, the number of elements controlled by the same data line may be increased. Further, the number of elements sharing the gate electrode may be increased, in other words, the number of elements controlled by the same word line may be increased. These are the same for the other embodiments. There is a method of backing with a metal material (for example, Al, W, TiN, WSi2, MoSi, TiSi, etc. is conceivable) in order to lower the resistance of the data line, and this method may be adopted. The word lines may also be lined with a metal material to reduce resistance. This is the same for the other embodiments.

Example 10
FIG. 9 shows a tenth embodiment of the present invention.

  Four storage elements according to the fourth embodiment are arranged in a matrix, and two elements share a source, a drain 1 and a drain 2 and two elements share a gate electrode. The shared polysilicon of the drain and the gate can be used as it is as the data line and the word line. In this embodiment, it is controlled by a total of four data lines 1 to 4 (48) to (51) and word lines 1 (54) and 2 (55), and can store information of 8 bits or more. Here, the data lines 1 to 4 and (48) to (51) in the drawing correspond to the ascending numbers, and will be described in this meaning in the following. In this embodiment, the lowermost layer of the n-type polycrystalline silicon stacked in three layers is the data lines 1 (48), 3 (50), the upper layer is the source lines 1 (52), 2 (53), and The uppermost layer is the data lines 2 (49) and 4 (51).

  In this embodiment, it is illustrated including the contact portion. The contact step will be described. First, an n-type polycrystalline silicon film for forming the data lines 1 (48) and 3 (50), a SiO2 film, and an n-type polycrystalline silicon film for forming the source lines 1 (52) and 2 (53) are respectively deposited. I do. Here, an n-type polycrystalline silicon film for forming the source lines 1 (52) and 2 (53) is cut by the first hole pattern (56). Next, after depositing an SiO 2 film and an n-type polycrystalline silicon film for forming the data lines 2 (49) and 4 (51), the data lines 2 (49) and 4 (51) are further formed by the second hole pattern (57). ) Polycrystalline silicon for formation is also shaved. After that, when the SiO2 film is deposited and the data lines and the source lines are collectively formed, the contact portions are processed into a shape (pattern of (58), (59), and (60)) connecting the contact patterns. As a result, in (60), the data line 2 is the uppermost layer of polycrystalline silicon, but in (59), the polycrystalline silicon of the data line 2 is no longer shaved and the polycrystalline silicon of the source line is the lowest. It is the upper layer. Further, in (58), both the polycrystalline silicon of the data line 2 and the polycrystalline silicon of the source line are missing, and the polycrystalline silicon of the data line 1 is the uppermost layer. Therefore, it is not necessary to prepare separate steps for forming contact holes in each of the above layers. This contact step is also effective for other laminated structures, and may be used for a structure in which gate electrodes are laminated as in the fifth embodiment, for example. Of course, a contact step other than this method may be used, and this is the same in other embodiments.

Example 11
10 to 12 and 17 show an eleventh embodiment of the present invention.

  Eight storage elements of Example 4 are arranged in a 4 × 2 matrix, and the source, drain 1 and drain 2 are shared by four elements, and the gate electrode is shared by two elements. is there. The drain and gate polycrystalline silicon shared as in the tenth embodiment can be used as they are as data lines and word lines. The three-layer polycrystalline silicon to be collectively etched is stacked in the order of data line 1, source line, and data line 2 from the lower layer. In this embodiment, the data line is shown including the selection transistor portion. The cell portion is a portion (61) surrounded by a dotted line. In this embodiment, it is controlled by four data lines (62), four selection transistor gates (63), and word lines (64), and can store information of 16 bits or more. As the memory cell becomes smaller, it is necessary to reduce the area of the contact and the peripheral circuit portion. In particular, when the source, the drain, or the gate has a laminated structure as in the present invention, the layout may not be possible if the contacts and peripheral circuit portions are large.

The structure will be described simultaneously with the manufacturing process. First, a select transistor is formed on a silicon substrate (FIG. 10A). (66), (67) and (68) in the figure are diffusion layers. At the same time, other peripheral circuits are also formed, but here, only a transistor for selecting a data line is shown.
After forming the gate electrode (63) of the select transistor, an oxide film is deposited, and a memory cell is formed on the field oxide film (69). The method of forming the cell portion is almost the same as that of the fourth embodiment, and different portions will be described below. Before depositing the n-type polycrystalline silicon film of the lower data line 1, the oxide film is etched using a photoresist as a mask to expose a part of the diffusion layer (66) of the select transistor (70) (FIG. 10B). .

  FIG. 11 shows a continuation of the manufacturing process. After depositing the n-type polysilicon film of the lower data line 1 and before depositing the n-type polysilicon film of the source line, the polysilicon of the data line 1 is etched using a photoresist as a mask (71) (FIG. 11) (a)). Further, after depositing the SiO2 film, the n-type polycrystalline silicon film of the source line, the SiO2 film, and the n-type polycrystalline silicon film of the data line 2, before the collective etching of the data and the source line, the hole pattern (72) shown in FIG. The polycrystalline silicon film of the data line 2 is etched. Therefore, when the data and source lines are simultaneously etched, there is no polycrystalline silicon of the data line 1 outside the pattern shown by (71), and there is no polycrystalline silicon of the data line 2 in the pattern part shown by (72). .

  By performing the above steps, the data line 1 is directly connected to the diffusion layer (66) of the selection transistor without any metal after the batch etching of the data and source lines (FIG. 11B). There is no need to perform a separate step, which simplifies the step and reduces the area. The common source lines are connected to each other by polycrystalline silicon, and the polycrystalline silicon of the upper data line 2 has been removed from a portion (65) of the common source lines. Therefore, the contact and the wiring need only be formed in this portion, and the area can be small.

  FIG. 12 shows a continuation of the manufacturing process. After oxide film deposition, polycrystalline silicon deposition, and word line processing, an oxide film deposition and planarization process are performed, and after contact holes are formed, a first metal wiring (75) is performed as shown in FIG. 12 (a). ). As a result, the data line 2 (73) is connected to the diffusion layer (68) of the selection transistor.

  FIG. 17 is a cross-sectional view taken along a line AB in FIG. However, in FIG. 12, the metal wiring for the gate (63) of the selection transistor and the word line (64) is omitted to avoid complexity of the drawing. Further, a contact hole to the diffusion layer (67) of the select transistor is made, and a second-layer metal wiring (62) is formed as shown in the figure. As a result, by selecting the voltage applied to the two gate electrodes of the selection transistors, the metal data line (62) is electrically connected to only one of the data line 1 and the data line 2.

  In this embodiment, a small-scale storage is used to simply show the structure. However, when a storage device is actually realized, the number of data lines and word lines is larger. For example, storage elements are arranged in a matrix having 1000 stacked data line and source line sets and 16 word lines, and a selection transistor is provided for each data line as in this embodiment. This structure is called a block for convenience. A storage device is realized by repeatedly arranging a plurality of blocks in a direction perpendicular to a word line. The set of stacked data lines 1 and 2 can be controlled by a single data line outside the block using select transistors. The metal data lines of the plurality of blocks are connected to each other. As a result, it is sufficient that there are metal data lines of the number of data lines of one block. Such a structure in which blocks are arranged in units of blocks has a feature that the data line portion of polycrystalline silicon can be short and the resistance does not increase.

Example 12
FIG. 13 shows a twelfth embodiment of the present invention.

  This embodiment differs from the fifth embodiment only in that the source line (74) is not made of polycrystalline silicon but a diffusion layer of a substrate is used. The source line may be common to each cell, and uses the substrate surface. This embodiment is characterized in that the resistance of the source line (74) is small, and the process is short because less polycrystalline silicon is required. Such a structure in which the source line is used as the diffusion layer of the substrate can be used in the device of the first embodiment.

Example 13
FIG. 14 shows a thirteenth embodiment of the present invention.

  This embodiment has a structure in which the storage elements of the first embodiment are arranged and further stacked in two layers. FIG. 14 shows a cross-sectional view along the data line. Since the storage element and the storage device of the present invention can be formed over an insulating film, they can be stacked unlike storage elements formed over a substrate surface. It has the feature that higher integration can be realized by taking a stacked structure. In addition, in the case of employing such a stacked structure, the storage element and the storage device of the present invention are affected by the gate electrode of the upper or lower cell compared to the planar structure because the channel runs vertically. It has the characteristic of being difficult.

Example 14
18 to 29 show a fourteenth embodiment of the present invention.

  FIG. 18 shows a structural diagram of a part of a memory cell array constituting the storage device of this embodiment. FIG. 18A is a view after forming a channel, and FIG. 18B is a view after forming a word line. The data line 1 (A1), the source line (A3), and the data line 2 (A2) are made of high impurity concentration n-type polycrystalline silicon, and are sequentially stacked from below with an SiO2 insulating film (A4) (A5) therebetween. Has been. A 2.5 nm thick, 50 nm wide channel portion (A6) (A7) made of a non-doped polycrystalline silicon thin film is formed on the side surface of the SiO2 insulating film (A4) (A5). Upper and lower common word lines (A9) made of polycrystalline silicon are formed with the film (A8) interposed therebetween. Here, the basic structure of the array is shown by preparing two stacked data line structures and two word lines. However, actually, more data lines and word lines are arranged to form a memory cell array. Two upper and lower memory cells are formed at each of the four intersections, and 8-bit storage is possible even when multi-bit storage is not used.

  FIG. 19 shows a view of this structure as viewed from above. The data line 1 (A1), the source line (A3), and the data line 2 (A2) are vertically overlapped (A10), and the area can be reduced accordingly. The unit structure (A11) is 4F2, and since this structure contains 2 cells, the area per cell is 2F2.

  The operation of this storage element will be described with reference to FIG. 20 (FIG. 20). Since the thickness of the polycrystalline silicon thin film is extremely small and the potential undulation in the film is severe, the current path (A12) which is a continuous low potential region path and the carrier confinement region (A13) which is an isolated low potential region are formed. Formed naturally in thin films. Since the thickness of the crystal grains of this film is about 2.5 nm, it is also suppressed to about 10 nm in the lateral direction, and the size of each carrier confinement region (A13) is also about this. There is an advantage that a small structure suitable for operation at room temperature can be effectively realized by a simple manufacturing process. Of course, the carrier confinement region and the current path may be provided in independent steps.

  In this case, if fine particles having a diameter of 10 nm or less are used in the carrier confinement region, the effect of Coulomb brocade can be obtained even at room temperature. Writing and erasing are performed by changing the potential of the word line (A9). When a constant voltage is applied between the source line (A3) and the data line 1 (A1) and the word line voltage is applied, electrons are induced in the polycrystalline silicon thin film of the channel portion (A6) and current starts to flow. . When a large gate voltage is applied, the potential difference between the current path (A12) and the carrier confinement region (A13) increases, and eventually the electrons pass through the barrier of the high potential portion by tunneling or thermal excitation, and the carrier confinement region (A13). As a result, the threshold value shifts to a larger value, and the current value decreases even at the same gate voltage. Reading of information is performed by checking the magnitude of the current value. Erasing is performed by swinging the gate voltage in the reverse direction.

  Next, the structure of a memory mat which is a basic unit constituting a large-scale cell array using the above-described memory cells will be described.

  21, 22, 23, 24, 25, 26, and 27 show layout diagrams of the memory mat. These are views of the same part at different stages of the manufacturing process. The manufacturing process will be described later.

  The memory cells described above have a shape suitable for being arranged in a matrix, and can be arranged on a large scale as they are. However, a long polycrystalline silicon data line is used, and the resistance becomes too large. Therefore, a certain amount of contact is made, and a long distance wiring is made of a low-resistance material such as a metal. This small unit is called a memory mat. In this embodiment, eight data lines and eight word lines are arranged, and a unit memory mat is composed of a total of 128 cells, two cells each at 64 intersections.

  For the sake of distinction, the polycrystalline silicon data line 1 and data line 2 for wiring in the unit mat are called local data lines, and the low-resistance data line for wiring between mats are called global data lines. Since two lines of the data line 1 and the data line 2 are overlapped at one pitch, a MOS transistor for selecting up and down in units of mats is provided on the substrate surface. Thereby, since only one global data line is required outside the mat, difficulty in pitch can be avoided. Considering the element isolation region, the selection transistor pitch is larger than the data line pitch. Therefore, the selection transistors of the adjacent local data lines are separately arranged above and below the memory mat.

  Next, the layout of this embodiment will be described together with the manufacturing process (FIGS. 21 to 27). An area (A22) surrounded by a dotted line in the figure is a unit memory mat. First, a selection n-type transistor is formed on the surface of a P-type substrate. A layout is adopted in which the gate electrode (A15) runs in common in the active areas (A16) arranged in parallel. At this time, a CMOS of a peripheral circuit is simultaneously formed outside the memory cell array. In order to use several kinds of voltages, the MOS transistor adopts a triple well structure. Since the withstand voltage may be different between the high withstand voltage transistor for a word drive circuit and transistors such as a decoder and a sense amplifier, MOS transistors having at least two types of gate lengths are formed. Although a SOI substrate was not used in this embodiment, a triple well structure is not necessarily required when a thin SOI substrate is used. Then, after depositing the SiO2 film, the SiO2 film is etched using the resist as a mask to expose a part (A14) of the diffusion layer of the selective MOS. After depositing an n-type polycrystalline silicon film having a thickness of 50 nm, the polycrystalline silicon is etched using the resist pattern (A33) as a mask (FIG. 21). By this step, since the local data line 1 (A1) is directly connected to the diffusion layer of the selection MOS, there is an advantage that a step of taking contact with the local data line 1 (A1) later becomes unnecessary. Further, an SiO2 film (thickness of 100 nm), an n-type polycrystalline silicon film (thickness of 50 nm), an SiO2 film (thickness of 100 nm), an n-type polycrystalline silicon film (thickness of 50 nm), and an SiO2 film (thickness of 30 nm) are arranged in this order. A total of six layers are deposited and are etched collectively using a resist as a mask to form a laminated structure (A17) of a source line (A3), a local data line 1 (A1), and a local data line 2 (A2). (FIG. 22).

  Since the memory structure is formed in a lump as described above, the number of lithography steps can be reduced as compared with a case where a single-layer memory structure is simply formed twice. A dummy data line pattern (A18) is formed at the boundary between the memory mats. This is because, in the data line lithography process, it is easier to find the optimal condition of exposure (drawing in the case of the EB process) if the pattern has a repetitive structure of the same size. Furthermore, by making the structure on both sides of each local data line the same, the local data line and the surrounding capacitance can be made the same for each local data line, and also from the viewpoint of stable operation of the memory. There are advantages. Next, after a (amorphous) -Si having a thickness of 2.5 nm is deposited, crystallization is performed by heat treatment. Thereafter, an SiO2 film having a thickness of 15 nm is deposited, and thereafter, a resist pattern (A19) having a line width of 0.1 μm and running in a direction perpendicular to the data lines is formed (FIG. 23).

  Using this resist pattern (A19) as a mask, wet etching is performed to form an SiO2 film (A6) between the local data line 1 (A1) and the source line (A3) and a local data line 2 (A2) and the source line (A3). A thin line of SiO2 running perpendicular to the substrate is formed on the side surface of the SiO2 film (A7) therebetween. Here, by preparing a dummy pattern pattern (A20), a measure is taken to prevent a resist pattern having a small line width from falling down. Next, the SiO2 pattern formed parallel to the substrate is removed by anisotropic dry etching. By performing this step, it is possible to prevent adjacent local data lines from being connected by a polycrystalline silicon thin film. Next, the polycrystalline silicon thin film is oxidized in an O2 plasma atmosphere. At this time, since the oxidation proceeds only up to about 10 nm, the polycrystalline silicon thin film below the previously formed thin line of SiO2 is not oxidized, and a fine line pattern of an ultra-thin polycrystalline silicon thin film can be formed. This method is superior to the thin line processing by dry etching in the following points. One is that a pattern finer than a resist can be formed by the side etch effect and the oxidation effect in wet etching. The inventors have found in the preliminary study stage that when the ratio of the width and length of the channel thin line of the ultra-thin polycrystalline silicon thin film is 2 or more, a sufficient threshold shift can be obtained before and after writing. As in the example, when the thickness of the SiO2 film (A4) between the local data line 1 (A1) and the source line (A3) is 100 nm, it is necessary to form a pattern of about 0.05 micron. In the prototype of the inventors, a resist pattern having a width of 0.1 micron was used, and a thin SiO2 wire of 0.07 micron was formed at the end of wet etching. The effect of oxidation from the side is added to this, and it is considered that a thin line of an ultra-thin polycrystalline silicon thin film having a width of about 0.05 μm is formed after the oxidation. The second advantage is that the oxidation by the O2 plasma stops at about 10 nm, so that there is no possibility that the data lines are excessively cut off during channel processing. After the channel processing, a thin SiO2 film (A8) serving as a gate insulating film is deposited, then an n-type polycrystalline silicon film is deposited and etched using a photoresist as a mask to form a word line (A21) (FIG. 24). ).

  At this time, if an n-type polycrystalline silicon film thicker than half the width between the data lines is deposited, a high step created by forming the data lines can be buried, and the formation of a resist pattern becomes easy. Due to the existence of the dummy pattern of the preceding data line, the groove width between the data lines is substantially constant, and this embedding effect can be obtained even at the boundary of the memory mat. Further, by performing etch-back after the deposition of the n-type polycrystalline silicon film, depositing the silicide after reducing the film thickness, a word line having a lower resistance can be formed. After forming a word line, an insulating film is deposited and planarized, and then a contact step is performed (FIG. 25). At this time, the contact (A26) to the local data 2 (A2), the contact (A27) to the diffusion layer (A16) of the selection MOS, the contact (A25) to the gate electrode (A15) of the selection MOS, and the word line (A21) The contact (A34) can be obtained by etching the insulating film deposited on the upper portion. On the other hand, since the source line (A3) is below the local data line 2 (A2), the contact hole (A23) to the source line (A3) is formed through the local data line 2 (A2). Further, since the active region width of the select transistor cannot be widened due to the pitch, the contact hole (A24) for connecting the global data line and the select transistor is provided with the local data line 2 (A2) and the source line (A3). ). This structure enables a layout in which the contact holes and the data overlap. Here, the local data line 1 (A1) does not exist in this contact area because the local data line 1 (A1) is shaved after deposition. In order to avoid a short circuit with the layer in the middle of the through hole, a sidewall of the insulating film is formed inside the hole by depositing the insulating film after the formation of the contact hole and etching back by anisotropic dry etching.

  FIG. 29 shows a cross-sectional view of the contact in the select MOS portion after the formation of the side wall.

  FIG. 28 shows a contact (A34) to the word line at the end of the memory array. A large dummy pattern (A35) made of the same material as the stacked data line and different from the dummy data line is provided, and a contact (A34) is formed thereon. Outside the data line pattern, the effect of embedding the trench by the data line due to polycrystalline silicon deposition as described in the word line processing cannot be obtained, and is a means for avoiding this. Thereafter, a metal is deposited and etched using a photoresist as a mask to form a first-layer metal wiring M1 (FIG. 26).

By backing the polycrystalline silicon gate electrode (A15) with the M1 wiring (A29), the resistance can be reduced. The wiring (A28) to the source line (A3) is also performed by M1.
In addition, connection (A30) between the local data line 2 (A2) and the diffusion layer of the selection MOS is also performed. Further, after depositing the interlayer insulating film, a contact hole is opened, a metal is deposited, and etching is performed using a photoresist as a mask to form a second-layer metal wiring M2 (FIG. 27). The global data line (A31) is formed by M2. Since the entire memory mat runs at a narrow pitch, if a global data line is formed with M1, other wiring cannot be performed. Therefore, it is necessary to use a wiring of M2 or higher for the global data line (A31). This is also true for a read circuit connected outside the memory cell array, and it is necessary to connect the read circuit in a layer below the global data line, for example, M1. The same effect as that of the local data line can be obtained by arranging the dummy pattern at the boundary of the memory mat also in the global data line.

Example 15
FIGS. 30 and 32 show a fifteenth embodiment of the present invention.

  FIG. 30 is a structural diagram of a part of the memory cell array constituting the storage device of this embodiment. FIG. 30A is a diagram after forming a channel, and FIG. 30B is a diagram after forming a word line. In the storage element of the fourteenth embodiment, the upper and lower two cells are vertically stacked. In the present embodiment, one cell is different, but other structures and operation principles are the same.

  A channel (A38) runs so as to connect the local data line (A37) and the source line (A36) vertically, and the potential of the channel is controlled by a word line (A47). Although the degree of integration is lower than that of the structure of the fourteenth embodiment, it is characterized in that the steps during processing are small and the process margin is large.

  FIG. 32 shows a top view of the memory mat. FIG. 26 is a view up to the contact step, which corresponds to FIG. 25 in the fourteenth embodiment. Again, the local data line is connected to the global data line via a MOS transistor in units of mats. In the fourteenth embodiment, the local data line was connected via a transistor for the purpose of selecting upper and lower cells. The purpose is to reduce the capacity of local data lines that are electrically connected to the lines. If the capacity of the global data line can be reduced, the potential can be changed faster and more greatly with the same current, and high-speed operation can be performed. Such an effect is not limited to the structure in which the channel runs perpendicular to the substrate as in the present embodiment and the fourteenth embodiment, but is also common to the structure in which the channel runs parallel to the substrate as shown in FIG. .

  FIG. 31 is a top view showing an array structure of six cells, which is a basic cell array. FIG. 31A shows a state after forming a channel, and FIG. 31B shows a state after forming a word line. A common source line (A40) has a local data line 1 (A39) and a local data line 2 (A41). The potential of the channel is controlled by the word line (A43). The unit cell structure is 6F2 with respect to the processing dimension F, and is characterized in that it is easier to manufacture than the three-dimensional structure as in this embodiment. Returning to the description of FIG. The contact hole (A46) for the source line (A36), the contact hole (A47) for the MOS gate electrode, and the contact hole (A48) for connecting the MOS diffusion layer to the global data line must be formed in the same process. And the number of steps is smaller than in the case of the fourteenth embodiment. The step of contacting the local data line (A37) is the same as in the fourteenth embodiment.

  Hereinafter, Embodiments 16 to 22 show embodiments for performing write, erase, write verify, erase verify, refresh, and multi-value storage of a cell array.

  FIG. 33 shows a typical cell array, which will be described with reference to FIG. Of course, other memory cell structures shown so far may be used.

Example 16
FIG. 34 shows an operation sequence of read, write, and erase operations of the cell array. The read condition is a condition for reading information of cell 1 and cell 2, the erase condition is a condition for erasing information of cell 1 and cell 2, and the write condition is information "1" for cell 1 and information "0" for cell 2. "Is a condition for writing. In the read operation, first, precharge is performed (step 1), and then a predetermined read voltage is applied between the source, data line and word line (step 2). The information held in the cell 1 is read out by the current flowing through the data line 1, and the information held in the cell 2 is read out by the current flowing through the data line 2. The potential of the word line 1 is set so that the current flowing when information "0" is held is sufficiently larger than the current flowing when information "1" is held, so that the two states can be easily distinguished.

By setting the potential of the word line 2 lower than the threshold voltage when information "0" is held, almost no current flows through the cells 3 and 4 regardless of the held information. The same applies to the case where more cells are arranged, and the read voltage is applied only to the word line controlling the cell to be read, and the other word lines connected to the same data line are set to a low potential.
Next, the erasing operation will be described. The erasing operation is performed on the cells 1 and 2 collectively. In addition, a storage unit corresponding to a list of cells to be erased is required for an erase bit-by-bit verify operation. First, a write voltage is applied before applying a voltage for erasing (step 1).

  By performing this operation, it is possible to prevent an erasing voltage from being continuously applied to a cell to which a writing operation has not been performed after the erasing operation before the erasing operation, and to suppress an undesirable characteristic variation. Next, the potential of the data line is set corresponding to the cell list (step 2).

  A potential (for example, 5 V) applied to a data line connected to a cell which has not been erased is set higher than a potential (for example, 0 V) applied to a data line which has been erased, so that a potential difference from a word line is increased. After a low voltage (for example, -10 V) for erasing is applied to the word line (step 3), a predetermined voltage (for example, 0.5 V) is applied to the word line to check the state of the cell, and the potential variation of the data line is changed. Is sensed (steps 4 and 5).

  As a result, if the threshold value of the cell is lower than the predetermined value, the cell is deleted from the list. Thereafter, if the list is empty, the erasing operation is completed; otherwise, the process returns to step 2. The voltage applied to the data line of the cell deleted from the list in step 2 is low (0 V in this case) and the potential difference from the word line (10 V in this case) is small, so that excessive erasure is not performed. By repeating this loop, a threshold voltage equal to or lower than a predetermined value is realized for all cells to be erased.

  In the write operation, an operation of writing information “0” and “1” to cell 1 and cell 2 respectively is shown. In the write operation, first, the potential of the data line is set in correspondence with the list of cells to which information "1" is written (step 1).

  The potential (eg, 0 V) applied to the data line of the cell where “1” writing has not been completed is set lower than the potential (eg, 5 V) applied to the data line where “1” writing or “0” writing has been completed. Is increased. Next, a high voltage (for example, 15 V) for writing is applied to the word line (Step 2), and then a predetermined voltage (for example, 2.5 V) is applied to the word line to check the state of the cell. The fluctuation is sensed (steps 3 and 4).

  As a result, if the threshold value of the cell is higher than a predetermined value, the cell is deleted from the list. Thereafter, if the list is empty, the write operation is completed. Otherwise, the process returns to step 2. The voltage applied to the data line of the cell deleted from the list in step 2 is high (here, 5 V) and the potential difference with the word line (here, 10 V) is small, so that excessive threshold value fluctuation can be prevented. Here, the list is a cell in which “1” is written. However, the list is composed of cells in which “1” has been written or cells in which “0” is written, and the list is increased while performing a verify operation. The writing operation may be completed at the time of joining the list. The same applies to the contents of the list in the erasing operation. In the following, for simplicity, the definitions are unified and described here.

  In this embodiment, polycrystalline silicon is used for the data lines, source lines, word lines, and channels, but these need not be made of the same material, and other semiconductors or metals may be used. Alternatively, bulk silicon may be used for a data line, a source line, or a channel using an SOI substrate. When bulk silicon is used, the resistance is reduced, and the speed of the memory can be increased. Although non-doped polycrystalline silicon is used for the channel, impurities may be contained therein. Further, in the present embodiment, the polycrystalline silicon thin film portion (1) of the channel also has a function of charge storage for performing storage simultaneously with the current path, but the thin film portion has only a function of a current path between low-resistance regions, In addition, a charge storage unit for performing storage may be provided. At this time, the material of the charge storage portion may be a semiconductor or a metal. At this time, as described in the description of the operation principle of the element, it is essential that the charge storage section has a small structure surrounded by a high potential. In the case of this structure, the current path and the charge storage portion can be separately designed, so that there is a feature that the degree of freedom in size, material, and the like increases.

Example 17
35 and 36 show a seventeenth embodiment of the present invention.

  FIGS. 35 and 36 show an implementation example using the cell list register described in FIG. 34 of the sixteenth embodiment. FIG. 35 shows the operation sequence, and FIG. 36 shows the configuration of the storage device. By sequentially exchanging data with the outside using the shift register, the number of output and input lines can be reduced. The structure and principle of the memory cell are the same as those of the sixteenth embodiment. Each bit of the register is associated with each data line. In this embodiment, cell 1 (and cell 3) corresponds to the first bit of the register, and cell 2 (and cell 4) corresponds to the next bit of the register. In the erasing operation, the state where the erasing is not completed is 1 and the state where the erasing is completed is 0. That is, the fact that the register is {1, 0} in the erasing operation of the cells 1 and 2 indicates that the erasing of the cell 2 has been completed but the erasing of the cell 1 has not been completed. Thereafter, when returning to step 2, when the bit of the register corresponding to the data line is 1, the potential of the erasing condition (for example, 5 V) is applied to the data line, and when the bit is 0, a lower potential (for example, 0 V) is applied. give. When all the bits of the register become 0, the erase verify loop ends.

In the write operation, when data is loaded in step 1, the value of each bit of the register represents bit inversion information of information to be written to a cell connected to the corresponding data line. That is, the fact that the register is {0, 1} in step 1 means that information “1” is written in cell 1 and information “0” is written in cell 2.
Thereafter, in step 2 and subsequent steps, when the information "1" has been written into the cell, 0 is inserted into the corresponding register bit. In step 1, when the bit of the corresponding register is 1, the potential of the erasing condition (for example, 0 V) is applied to the data line, and when it is 0, a higher potential (for example, 5 V) is applied. When all the bits of the register become 0, the write verify loop ends.

Example 18
FIG. 37 shows an eighteenth embodiment of the present invention.

  In this embodiment, the erase verify is not performed for each bit, and the end point of the erase loop is determined when all cells to be erased are smaller than a predetermined threshold. In this method, an erase voltage is applied to all cells selected in step 2 of the erase sequence. This method has a feature that the operation is simple because it is not necessary to perform control for each bit. In order to avoid excessive erasing, it is necessary to maintain the state stability for an extra erasing voltage application time. Depending on the cell characteristics, electron injection is defined as erasing, and all cells to be erased have a predetermined threshold. A method of determining the end point of the erasing loop by increasing the size may be adopted. In this method, since the cell whose threshold value has risen is the erased cell, current does not flow in most cells when the loop is repeated, so that the power consumption of the erase operation can be reduced.

Example 19
FIGS. 38 and 39 show a nineteenth embodiment of the present invention.

  The structure of the memory cell portion is the same as that of the seventeenth embodiment. The present embodiment is characterized in that a refresh operation is performed in storage retention in addition to a verify operation in writing and erasing. As described in the first embodiment, since the number of electrons to be accumulated is small, an essentially stochastic phenomenon called thermal excitation or tunnel appears clearly at the time of writing. The same applies to memory retention, which causes memory retention instability. However, the means for stabilizing the holding by increasing the thickness of the insulating film (or increasing the potential barrier width) between the charge supply portion and the charge storage portion undesirably increases the write time at the same time. . The memory of the present invention has a characteristic that it can perform writing and erasing at a higher speed than a flash memory, but if a control method of performing a refresh operation at the time of holding data is used, it is possible to achieve both high-speed writing and erasing and stable data holding. It is possible. DRAMs capable of high integration are widely used as volatile memories. However, the memory cell of the present invention can be formed with one transistor in one transistor area, and the memory cell structure is simple, so that higher integration is achieved. Memory can be realized.

  FIG. 38 shows a configuration diagram of the storage device of this embodiment. Unlike the seventeenth embodiment, a feature is that two types of registers are prepared. FIG. 39 shows a sequence of the refresh operation. Four adjacent cells will be described in the same manner as in the sixteenth embodiment. The reading, erasing, and writing operations of the seventeenth embodiment are performed in this order, and are repeated while sequentially selecting the word lines. First, data of the selected word line is read, and the contents are stored in the register 1. Here, the information of each bit of the register 1 is inverted information of the cell information. Next, the erase operation described in the seventeenth embodiment is performed. If the register 1 is used as it is in the erase operation, previously read data will be lost. Therefore, a register 2 different from the register 1 is prepared. Next, the data of the register 1 is written into the memory cell again. This series of operations is performed while moving the word line for sequentially selecting. Refreshing is performed in a cycle sufficiently shorter than the average time during which storage of the memory cell is lost, thereby realizing stable storage. The register 1 or the register 2 is used for verifying the write and erase operations. Here, a method of temporarily transferring the information of the register 1 to the register 2 and then using the register 1 in the erasing operation may be used. In this case, after the erasing operation, the information in the register 2 is transferred to the register 1, and then the writing operation is performed. The operation of writing, erasing, and reading information may be the same as in the seventeenth embodiment. However, when the potential barrier width or the height of the potential barrier between the charge storage portion and the outside is reduced in order to realize faster writing and erasing, the read operation also needs to be changed. In this case, the read information is rewritten in order to prevent the stored information from being lost by the reading operation. The operation sequence is the same as the refresh operation, and differs only in that the read information is sent to the outside. This is the same in the embodiment in which another refresh operation is performed.

Example 20
40 and 41 show a twentieth embodiment of the present invention. FIG. 40 shows the configuration of the memory, and FIG. 41 shows the sequence of the refresh operation.

  This embodiment is different from the nineteenth embodiment in that the erase verify is not performed for each bit, and the end point of the erase loop is determined when all cells to be erased are smaller than a predetermined threshold value. The other points are the same as those of the nineteenth embodiment, but since the erase verify is not performed for each bit, there is no need to prepare a register for each data line in the erase operation, and the second register is unnecessary. .

Example 21
FIG. 42 shows the configuration of the twenty-first embodiment of the present invention.

  This embodiment is characterized in that more than one bit of information is stored in one cell (multi-value storage).

  The structure of the memory cell portion is the same as that of the sixteenth embodiment.

  FIG. 43 shows an experimental result on unit cell characteristics. In this figure, the source line is set to 0 V, the data line is set to 2 V, and the word line is set to 9 V, and the time change of the current flowing through the data line is shown. The potential of the word line was not increased so much, the electron injection was delayed, and the current change was easily observed. As can be seen from the drawing, when electrons are accumulated one by one in the storage area, the current changes stepwise in response to the discrete shift of the threshold value. Each of the discrete threshold values is made to correspond to information, and multi-value storage is possible. For example, a state in which one electron is stored is information "0,0", a state in which two electrons are stored is information "0,1", a state in which three electrons are stored is information "1,0", and a state in which four electrons are stored. Corresponds to information "1, 1", so that 2-bit storage is possible. There is a feature that the state can be easily distinguished as compared with the case where the multi-value storage is performed by classifying continuous characteristics. The configuration of the storage device is the same as that of the nineteenth embodiment, except that the register corresponding to each word line has multiple bits, and the voltage and time setting of the write operation and the read operation are different. In this embodiment, one electron is made to correspond to one piece of information. However, as described repeatedly, a probability phenomenon of injection and emission of electrons appears in the characteristics, and variations in storage retention, writing, and erasing characteristics increase. In order to realize stable storage, it is effective to perform a verify operation in writing and erasing and a refresh operation in storing and holding. Writing of multi-valued information is performed by changing a writing time (a writing pulse width or a sum of writing pulse widths) depending on the information. This writing time uses an equal value. As described in the sixteenth embodiment, the probability that the next electron is injected by one electron injection is affected because the storage area is small. This change causes an exponential dependence on the number of injected electrons. Because we have. Note that information may be separately written by using a plurality of values for the write voltage instead of the write time. This writing voltage uses an equal ratio value. This is because the probability that the next electron will be injected only when a voltage enough to cancel the potential change of the storage region due to the electron injection is applied becomes similar. Of course, these may be combined and different voltages and different times may be used together. In the reading operation, a reference potential generating circuit for reading a plurality of states is required. Further, in order to perform the verify operation or the refresh operation in the multi-value storage, a multi-value information holding means is required.

  If the number of stored electrons corresponding to the information is not one but a plurality (for example, five electrons correspond to the information), more stable storage can be realized. The configuration and operation sequence of the memory are the same. Since the storage is performed with more electrons, the effect of the stochastic phenomenon is relatively smaller than that of the storage of one electron, so that it is possible to realize more stable storage. Therefore, there is also a feature that the cycle of the refresh operation can be lengthened and the power consumption can be reduced.

Example 22
FIG. 44 shows a refresh operation according to the twenty-second embodiment of the present invention.

  The present embodiment is characterized in that a refresh operation is performed at the time of holding data, but no verify operation is performed in writing and erasing. The same structure as that of Embodiment 22 is used for the memory cell, but the diameter of the silicon crystal grain in the storage region is about 4 nm. Take a write operation as an example and focus on one of the crystal grains. When one electron is injected, the probability of a second electron being injected is significantly reduced. In other words, the time until the injection of the second electron is significantly longer than that of the first electron. Therefore, taking into account stochastic fluctuations, set the time so that the write voltage is applied for a time sufficiently longer than the average time during which one electron is injected, and that time is sufficiently shorter than the average time during which the second electron is injected. Becomes possible. Therefore, a stable storage operation can be realized without a verify operation in both 1-bit 1-cell storage and 1-cell multi-bit storage.

  Hereinafter, in the twenty-third to twenty-fifth embodiments, a small-area peripheral circuit which does not impair the features of the small-area and highly-integrated memory cell described above, and a single-electron memory which is small in the amount of electric charges to be handled and is susceptible to noise. A specific example of a peripheral circuit with low noise and a control method for the peripheral circuit suitable for the present invention will be described.

  FIG. 45 shows the definitions of the symbols. In the following description, the semiconductor memory device according to the present invention is distinguished from a normal FET by indicating a carrier confining region with a black circle symbol as shown in FIG.

Example 23
In the twenty-third embodiment, the structure of a read, erase and write circuit of a semiconductor memory device will be described with reference to FIGS.

  FIG. 46 is a circuit diagram of the present embodiment.

  FIG. 47 is a circuit diagram of a memory cell portion. FIG. 46 shows only a pair of data lines for simplicity. However, in an actual semiconductor memory device, many of the same data lines are arranged in the horizontal direction. In FIG. 46, memory cells (MM1), (MM2), (MM3), and (MM4) are vertically stacked memory cell arrays, and MOSs (M3) and (M4) are local data line selection MOSs. MM1 and MM3 are lower-layer memory cells, which are connected to the lower-layer local data line (LDL). MM2 and MM4 are upper-layer memory cells, which are connected to upper-layer local data lines (LDU). The source line is common to the upper and lower cells. LDL is connected to global data line D1 through M3. The LDU is connected to D1 through M4. Hereinafter, the set including the memory cell array and the local data line selection MOS is referred to as a block. There is also a global data line (D2) paired with D1, which includes dummy memory cell arrays (DMM1), (DMM2), (DMM3), (DMM4) and local data line selection MOSs (M1), (M2). Are connected in the same manner as the memory cell block.

  48 and 49 are diagrams illustrating the operation of the circuit. D1 and D2 are connected to pre / discharge MOSs (M5) and (M6) for charging and discharging the same. Further, D1 and D2 are connected to a sense amplifier (differential amplifier) including M13, M14, M15, and M16 via transfer MOSs (M7) and (M8).

  Power supply MOSs (M11) and (M12) for activating the sense amplifier are connected to the sense amplifier. Both input / output lines (D3) and (D4) of the sense amplifier are provided with sense amplifier discharge MOSs (M9) and (M10) for discharging the same.

  Next, read, erase, and write operations of this embodiment will be described. This embodiment is characterized in that reading and writing are performed by switching upper and lower memory cells. However, erasing is performed simultaneously on the upper and lower memory cells. In the following description, the case where the threshold voltage of the memory cell is high is “1”, and the case where the threshold voltage is low is “0”. The logic is positive logic, and the high level is "1" and the low level is "0". Of course, these can be reversed.

  FIG. 47 shows an example of a voltage applied to a memory cell in each case of reading, erasing, and writing before describing a specific operation of the circuit.

  For reading, the local data line of the memory cell to be read (in this case, MM1) and the corresponding dummy memory cell (in this case, DMM1) are precharged (for example, 2.5 V), and the word line (W1) and the dummy word line This is performed by applying a read voltage (for example, 2.5 V) to (DW1), turning on MM1 and MM2, and discharging the local data line (LDL) and the dummy local data line (DLDL). The threshold voltage of the dummy memory cell DMM1 is set in advance to an intermediate value between "1" and "0". Then, when the data of MM1 is "0", the voltage of LDL decreases quickly, and when the data of MM1 is "1", DLDL decreases faster and the voltage of LDL is kept high.

  For erasing, the upper and lower local data lines (LDL) (LDU) and the source line (S) are set to a high level (for example, 5 V), an erasing voltage (for example, -10 V) is applied to the word line (W1), and all the memory cells are erased. This is done by lowering the threshold voltage.

  For writing, the source line (S) is set to a high level (for example, 5 V), the local data line (LDL) of the memory cell (MM1 in this case) to which "1" is to be written is 0 V, and the memory cell to which "0" is to be written (in this case). Sets the local data line (LDU) of the MM2) to a high level (for example, 5V) and applies a write voltage (for example, 15V) to the word line (W1). Since 15 V is applied between the data line and the word line of MM1, the threshold voltage rises. This is called "1" writing. Since only 10 V is applied between the data line and the word line and between the source line and the word line in the MM2, the rise of the threshold voltage is suppressed. This is called “0” writing.

  The voltage values in the above description are examples. The write voltage is so high that the threshold voltage of the memory cell rises in a sufficiently short time and does not break down, and the erase voltage is low enough that the threshold voltage of the memory cell falls in a sufficiently short time and does not break down. The voltage of the local data line and the source line of the cell is as high as possible to suppress the rise of the threshold voltage for the memory cell of "1" write, and the word line voltage and the local data line voltage at the time of reading are unnecessary threshold voltages. It is essential that the temperature is low enough that no rise occurs.

  A specific read operation will be described using the memory cells (MM1) and (MM2) and the dummy memory cells (DMM1) and (DMM2). Here, it is assumed that "0" is written in the lower memory cell (MM1) and "1" is written in the upper memory cell (MM2).

FIG. 48 is a timing chart for performing reading. First, LD1 and DLD1 are set to high level, the local data line selection MOS (M3) and the dummy local data line selection MOS (M1) are turned on, and the local data line (LDL), the global data line (D1), and the dummy local data line (DLDL) and the global data line (D2). Next, the PDG is set to a high level, the precharge MOSs (M5) and (M6) are turned on, and LDL, DLDL, D1, and D2 are precharged. Further, the SADG is set to the high level, the sense amplifier discharge MOSs (M9) and (M10) are turned on, and the voltages at both ends (D3) and (D4) of the sense amplifier are lowered to the ground level. Next, the word line (W1) and the dummy word line (DW1) are turned on, and the discharge of the data line is started. At this time, since "0" is written in the memory cell (MM1), the threshold value is lower than that of the dummy memory cell (DMM1), and the discharge is performed faster, so that the voltage of D1 is lower than that of D2. Next, T1G is set to the high level, the transfer MOSs (M7) and (M8) are turned on, and the voltages of the global data lines (D1) and (D2) are transferred to the sense amplifier.
Subsequently, the SAP is set to low level and the SAN is set to high level to turn on the sense amplifier activating MOS transistors (M11) and (M12) to activate the sense amplifier and activate the two input / output lines (D3) and (D4). Is amplified to the power supply voltage. As a result, data in the lower memory cell (MM1) can be read. Similarly, the upper memory cell (MM2) is read. However, at this time, M2 and M4 (signal lines are LD2 and DLD2) are used as local data line selection MOSs. When the word line (W1) and the dummy word line (DW1) are turned on and the discharge of the data line is started, the threshold voltage of MM2 is higher than the threshold voltage of DMM4, so that D1 is higher than D2. Discharge is slow and is maintained at a high voltage.

  Next, the erasing operation will be described. Before erasing, all cells are once written. This is necessary in order to prevent a cell to which "0" is continuously written (the threshold voltage does not rise) from being excessively erased. LD1 and LD2 are set to the high level, the local data line selection MOSs (M1) and (M2) are turned on, and the upper and lower local data lines (LDL) and (LDU) are connected to the global data line (D1). The PDD is set to a low voltage, the PDG is set to a term voltage, and the data line pre / discharge MOSs (M5) and (M6) are turned on. When the voltages of the LDL and LDU become low, a write voltage is applied to the word line (W1). The PDD is set to a high voltage with M1, M2, and M5 turned on. When the voltages of the upper and lower local data lines (LDL) and (LDU) become high level, an erase voltage is applied to the word line (W1). Thereby, the upper and lower cells can be erased simultaneously.

Next, a write operation will be described. The case where "0" is written in the lower memory cell (MM1) and "1" is written in the upper memory cell (MM2) will be described. At the time of writing, the upper and lower roll data lines must have different voltages. In addition, since the memory cell is strongly turned on at the time of writing, the voltage of the local data line must be statically applied. Therefore, writing is performed separately for the upper and lower cells. However, when writing one cell, the voltage of the local data line is applied dynamically, but not adversely, to the other cell. The input / output line (D3) of the sense amplifier is set to low level, LD2 is set to high level, the local data line selection MOS (M4) is turned on, and the upper local data line (LDU) is set to low level. Next, the voltage is dynamically applied by setting LD2 to low level and turning off M4.
Next, D3 is set to the high level, LD1 is set to the high level, the local data line selection MOS (M3) is turned on, and the lower local data line (LDL) is set to the high level. Subsequently, a write voltage is applied to the word line (W1) with M3 turned on. As a result, "0" is written to MM1. At this time, since MM2 is strongly turned on, the voltage of LDU rises, and writing "1" of MM2 is insufficient.

  Next, the voltage of LDL is dynamically given by turning off LD3 and turning off M3. Next, D3 is set to low level, LD2 is set to high level, M4 is turned on, and LDU is set to low level. Subsequently, a write voltage is applied to W1. As a result, "1" is written to MM2. At this time, although MM1 is strongly turned on, the voltage of LDL does not change, and "0" is written to MM1.

  The feature of this embodiment is that the local data lines of the memory cells stacked vertically are connected to one global data line via a selection MOS transistor, and are sequentially switched when reading and writing are performed. In addition, even if the memory cells are stacked, the number of global data lines and sense amplifiers does not increase, and the area of the peripheral circuit can be prevented from increasing.

In this embodiment, the memory cells have two layers, but this may be three or more layers. Further, the local data lines may be arranged on a plane instead of the stacked type. Further, a set of local data lines stacked by combining them may be arranged on a plane.
Example 24
In the twenty-fourth embodiment, another configuration of the read, erase, and write circuits of the semiconductor memory device will be described with reference to FIG. FIG. 50 differs from FIG. 46 in that memory cells are arranged at all intersections of a data line and a word line forming a pair.

  As the positional relationship between the data lines and the sense amplifiers, there are known an open type in which a pair of data lines are arranged on both sides of the sense amplifier and a folded type in which the data lines are arranged in the same direction. The open type has the advantage that the memory cells can be arranged at all the intersections of the data line and the word line and has a high degree of integration, but has the disadvantage that the noise due to the word line drive is large. Conversely, in the folded type, memory cells cannot be arranged at all the intersections of the data line and the word line, but there is an advantage that noise due to word line driving is small. In this embodiment, memory cells are placed at all the intersections of the data lines and the word lines despite the folded data line structure. When reading the memory cell MM1, the cells MM7 and MM8 are also activated. However, since the local data line selection MOS transistors M7 and M8 are off, the global data line D2 is not affected. Since the memory cell is non-destructive for reading, the data written in MM7 and MM8 does not change. Single-electron memories are advantageous for miniaturization, but have the drawback that they handle a small amount of current and are susceptible to noise. Thus, a folded data line structure resistant to noise can be obtained without sacrificing high integration of the memory cells.

  In this embodiment, four operations are performed to read all the memory cells on the same word line. However, since the writing is independent for each global data line, it is sufficient to perform the erasing twice and the erasing once, as in the twenty-third embodiment.

    In this embodiment, the memory cells have two layers, but this may be three or more layers. Further, the local data lines may be arranged on a plane instead of the stacked type. Further, a set of local data lines stacked by combining them may be arranged on a plane. Further, the number of local data lines may be one. It is essential that the memory cells are arranged at all the intersections of the global data line and the word line which form a pair.

  In this embodiment, a single-electron memory has been described. However, this can be applied to other floating gate memories, flash memories, and the like as long as the reading of a memory cell is non-destructive.

Example 25
In the twenty-fifth embodiment, the configuration of the input / output and verify circuit of the semiconductor memory device will be described with reference to FIG. The input / output and verify circuit includes a transfer unit for transferring data from the sense amplifier to the shift register, an All "0" determination circuit for checking whether all read data are "0", and all read data of "1". An All "1" determination circuit for checking whether the data is "1" and a shift register for temporarily storing data from the sense amplifier and sequentially outputting the data to the outside. The shift register is also used for externally inputting write data and transferring the write data to a memory cell. It is also used as a storage location of a write end flag at the time of write verification. The shift registers correspond to the upper and lower memory cells, and two columns are provided for each global data line, that is, four columns in total.

  In FIG. 51, the circuits of the shift registers (2), (3), and (4) are omitted, and only the signal lines are shown. Although the memory cell array shown in Embodiment 24 is used. Of course, this could be something else.

  Hereinafter, read, write, erase verify, and write verify will be described in this order.

  First, the read operation will be described. When the data of the memory cell MM1 is read by the procedure shown in the embodiments 23 and 4, the data appears on the input / output line D3 of the sense amplifier. Next, P0 of the transfer circuit is set at a high level and P1 is set at a low level, and M21 and M22 are turned on. If the data of D3 is "0", M23 is turned on, and "0" appears on the input / output line D5 of the shift register through M21 and M23. If the data of D3 is "1", M24 turns on, and "1" appears on the input / output line D5 of the shift register through M22 and M24. Next, SRMF1 is set to low level, the feedback of the master unit of the shift register (1) is turned off, SRI1 is set to high level, M39 is turned on, and data is input to the shift register (1). Thereafter, SRMF1 is set to a high level to turn on M41, and the data is held by applying the feedback of the master unit of the shift register (1). The same procedure is repeated for MM2, MM7, and MM8, and the respective data is input to shift registers (2), (3), and (4). Finally, SRMF and SRSF1, SRSF2, SRSF3, and SRSF4 are alternately inverted to operate the four shift registers simultaneously and output data to the outside.

  Next, a write operation will be described. Data to be input to the shift register is prepared in DI1, DI2, DI3, and DI4, and SRMF and SRSF1, SRSF2, SRSF3, and SRSF4 are alternately inverted to operate the four shift registers at the same time and to transfer data to a predetermined data line. Transfer to At the end of the transfer, SRSF is at a low level, SRMF1, SRSF2, SRSF3, and SRSF4 are at a high level, and only the master unit is fed back. Thereafter, at the timing shown in the second embodiment, SRO1, SRI1, and T2G are set to a high level, M44, M39, and M25 are turned on, and data is transferred to the input / output line D3 of the sense amplifier to perform writing.

  Next, the erase verify operation will be described. Erase verify refers to reading data from a memory cell that has been erased once, confirming that the data has been erased normally, and performing erasing again only on a memory cell that has not been sufficiently erased. The first erasure can be performed simultaneously on the upper and lower memory cells as shown in the second embodiment, but the erasure at the time of the erase verify must be performed separately on the upper and lower memory cells. First, reading is performed, and data is input to the shift register. Next, A0G is set to a high level, M31 and M33 are turned on, and the input / output lines D5 and D6 of the shift register are set to the ground level. Next, AL0 is set to a high level and then set to a high impedance state. Next, SRO1 is set at a high level to turn on M44, and the data of the shift register (1) is output. Similarly, the data of the shift registers (2) to (4) are sequentially output. If all the output data is "0", M32 and M34 are not turned on, and the voltage of AL0 is kept high. If at least one output data is "1", M32 is turned on and the voltage of AL0 falls. Therefore, the voltage of AL0 is monitored, and if it drops, it is found that the erasure is incomplete.

Next, the write verify operation will be described. In the case of erase verify, it was sufficient to check that all read data is "0". However, in the case of write verify, a write end flag is required for each memory cell because data to be written differs for each memory cell. . In this embodiment, this flag is also used as a shift register. At the time of the first writing, the inverted data is written in the shift register (this is more convenient in order to match the value of the shift register with the voltage of the local data line). This is regarded as an end flag for writing “1”. That is, in the case of "0", the writing of "1" has not been completed, and in the case of "1", the writing of "1" has been completed or it is not necessary to start from the beginning ("0" writing). Therefore, reading is performed after writing, the data in the shift register is rewritten to “1” only when the read data is “1”, and it is determined whether all the data in the shift register is “1”. To rewrite the data of the shift register to “1” only when the read data is “1”, the following is performed. At the time of reading after writing, unlike normal reading, P1 is set to low level, but P0 is not set to high level. Then, only when the read data is "1", a high level is transmitted via M22 and M24, and when the read data is "0", neither M21 nor M24 is turned on, and the data in the shift register is retained. After the update of the write end flag is completed, it is checked whether or not all are “1”.
First, A1G is set to low level to turn on M35 and M37, and the input / output lines D5 and D6 of the shift register are precharged. Next, AL1 is set to a low level and then to a high impedance state. Next, SRO1 is set to a high level to output the data of the shift register. Similarly, the data of the shift registers (2) to (4) are sequentially output. If all the output data is "1", M36 and M38 are not turned on, and the voltage of AL1 is kept low. If any one of the output data is "0", M36 and M38 are turned on, and the voltage of AL1 rises. Therefore, the voltage of AL1 is monitored, and when it rises, it is understood that writing is incomplete.

  According to this embodiment, the logic of rewriting the write end flag only when the read data is "1" at the time of the write verify can be realized by using one side of the transfer circuit. By also using the register, an increase in the area of the peripheral circuit can be suppressed. In addition, the same dummy cell is used as a threshold voltage reference in any of the read, write verify, and erase verify operations. This improves the noise margin.

  The shift register is not limited to the one shown in FIG. 51, but may be any one that can perform a static operation. If a latch for transferring data to a memory cell is separately provided, a shift register having a dynamic operation can be used.

Example 26
FIG. 52 shows a twenty-sixth embodiment. This embodiment is a semiconductor memory device in which a decoder, a driving circuit, and a control circuit are added to the embodiment 26. At the center is a block of memory cells, one of which is a dummy memory block. Hereinafter, the operation will be described. First, commands indicating reading, erasing, writing, and the like are input to the command predecoder. Then, a power supply voltage corresponding to each command is supplied to each drive circuit by the voltage switching circuit. Next, an address signal is input to the address decoder to select a memory cell. In this state, if each signal is input at the timing shown in the twenty-fifth embodiment, reading, erasing, and writing to a desired memory cell are performed.

  The method of selecting a memory cell will be described in more detail. The address signal is input to an address predecoder and a local data line decoder. The signal from the address predecoder is divided into two parts, and is inputted to the block decoder and the word line decoder. As a result, one word line in one block is selected.

  Selection of upper and lower local data lines is performed by a signal from a local data line decoder. The local data lines may be selected separately in the upper and lower portions, or may be selected at the same time. The distinction is made by the command predecoder. According to this embodiment, a large-scale semiconductor memory device can be realized.

Example 27
FIG. 53 shows a twenty-seventh embodiment. In this embodiment, another set of registers is provided in addition to the shift register of the twenty-seventh embodiment, and a refresh operation can be performed.

1 is a structural diagram of a semiconductor device according to a first embodiment of the present invention. (a) is a bird's-eye view, and (b) is a cross-sectional view. FIG. 9 is a structural diagram of a semiconductor device according to a third embodiment of the present invention. (a) is a bird's-eye view, and (b) is a cross-sectional view. FIG. 9 is a structural diagram of a semiconductor device according to a fourth embodiment of the present invention. (a) is a bird's-eye view, and (b) is a cross-sectional view. FIG. 9 is a structural diagram of a semiconductor device according to a fifth embodiment of the present invention. (a) is a bird's-eye view, (b) is a cross-sectional view including a section including a channel portion, and (c) is a cross-sectional view including a source. FIG. 13 is a structural diagram of a semiconductor device according to a sixth embodiment of the present invention. (a) is a bird's-eye view when a channel is formed, and (b) is a bird's-eye view after a gate is formed. FIG. 13 is a structural diagram of a semiconductor device according to Example 7 of the present invention. FIG. 13 is a structural diagram of a semiconductor device according to an eighth embodiment of the present invention. (a) is a bird's-eye view when a channel is formed, and (b) is a bird's-eye view after a gate is formed. FIG. 14 is a diagram illustrating a semiconductor device according to a ninth embodiment of the present invention. (a) is a bird's-eye view, and (b) is a top view. FIG. 14 is a diagram illustrating a semiconductor device according to a tenth embodiment of the present invention. (a) is a bird's-eye view, and (b) is a top view. FIG. 32 is a top view illustrating a manufacturing step of the semiconductor device according to Embodiment 11 of the present invention; FIG. 32 is a top view illustrating a manufacturing step of the semiconductor device according to Embodiment 11 of the present invention; FIG. 21 is a top view illustrating a semiconductor device of Example 11 of the present invention and a manufacturing process thereof. FIG. 16 is a structural diagram of a semiconductor device according to Example 12 of the present invention. FIG. 21 is a diagram showing a semiconductor device according to a thirteenth embodiment of the present invention. FIG. 6 is a diagram illustrating a semiconductor device according to a second embodiment of the present invention. (a) is a bird's-eye view, and (b) is a cross-sectional view. FIG. 5 is a bird's-eye view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 21 is a cross-sectional view illustrating a structure of a contact portion of a semiconductor device according to Embodiment 11 of the present invention. FIG. 21 is a structural diagram of a semiconductor memory element which is a component of the semiconductor device according to Embodiment 14 of the present invention. (a) is a bird's-eye view after forming a channel, and (b) is a bird's-eye view after forming a word line. FIG. 34 is a top view of a semiconductor storage element which is a component of the semiconductor device according to Example 14 of the present invention. FIG. 19 is a model diagram illustrating the operation principle of a semiconductor memory element that is a component of the semiconductor device according to Example 14 of the present invention. FIG. 34 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 14 of the present invention. FIG. 3 is a diagram before a memory cell is formed. FIG. 34 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 14 of the present invention. FIG. 4 is a diagram after a data line is formed. FIG. 34 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 14 of the present invention. FIG. 4 is a view after forming a resist for forming a channel. FIG. 34 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 14 of the present invention. FIG. 6 is a view after a word line is formed. FIG. 34 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 14 of the present invention. It is a figure after forming a contact hole. FIG. 34 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 14 of the present invention. FIG. 7 is a diagram after a first-layer wiring is formed. FIG. 26 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 14 of the present invention. FIG. 11 is a diagram after a second-layer wiring is formed. FIG. 34 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 14 of the present invention. It is a figure after forming a contact hole. FIG. 6 is a diagram showing a contact pattern for a word line at an end of a cell array. FIG. 21 is a cross-sectional view illustrating a contact structure of a selection MOS of a memory mat that is a component of a semiconductor device according to Embodiment 14 of the present invention. FIG. 15 is a structural diagram of a semiconductor memory element which is a component of the semiconductor device according to Embodiment 15 of the present invention. (a) is a bird's-eye view after forming a channel, and (b) is a bird's-eye view after forming a word line. FIG. 21 is a structural diagram of a semiconductor memory element having a different shape, which is a constituent element of the semiconductor device according to Embodiment 15 of the present invention. (a) is a bird's-eye view after forming a channel, and (b) is a bird's-eye view after forming a word line. FIG. 35 is a top view of a memory mat which is a component of the semiconductor device according to Embodiment 15 of the present invention. It is a figure after forming a contact hole. FIG. 27 is a diagram showing a cell array used for describing Examples 16 to 22 of the present invention. FIG. 32 is a diagram showing an operation sequence of reading, erasing, and writing of the semiconductor memory device according to Embodiment 16 of the present invention. FIG. 26 is a diagram showing an operation sequence of reading, erasing, and writing of the semiconductor memory device of Embodiment 17 of the present invention. FIG. 21 is a configuration diagram of a semiconductor memory device according to Embodiment 17 of the present invention. FIG. 32 is a view showing an operation sequence of reading, erasing, and writing of the semiconductor memory device according to Example 18 of the present invention. 19 is a configuration diagram of a semiconductor memory device according to Example 19 of the present invention. FIG. FIG. 39 is a view showing a sequence of a refresh operation of the semiconductor memory device of Embodiment 19 of the present invention. FIG. 21 is a configuration diagram of a semiconductor memory device according to a twentieth embodiment of the present invention. FIG. 39 is a view illustrating a sequence of a refresh operation of the semiconductor memory device according to Example 20 of the present invention. 21 is a configuration diagram of a semiconductor memory device according to Embodiment 21 of the present invention. FIG. 23 is a time change of a drain current of a memory cell of the semiconductor memory device according to Example 21 of the present invention. FIG. 35 is a diagram illustrating a sequence of a refresh operation of the semiconductor memory device according to Example 22 of the present invention. FIG. 4 is a diagram for defining symbols representing a memory cell having a floating gate. FIG. It is a drawing showing a twenty-third embodiment of the present invention. 1 shows a circuit for reading and writing a stacked memory cell in a temporal multiplex. 38 is a diagram illustrating an example of voltages applied to memory cells at the time of reading, erasing, and writing according to a twenty-third embodiment of the present invention. FIG. 39 is a diagram showing a read timing chart of the twenty-third embodiment of the present invention. 31 is a diagram showing a timing chart of erasing and writing according to a twenty-third embodiment of the present invention. It is a drawing showing a 24th embodiment of the present invention. 5 is a diagram showing a circuit in which memory cells can be arranged at all intersections of a word line and a data line while having a folded data line structure. It is a drawing showing a 25th embodiment of the present invention. 3 is a diagram illustrating an input / output circuit and a verify circuit according to the present invention. 35 is a configuration diagram of a semiconductor memory device according to Example 26 of the present invention. FIG. 28 is a configuration diagram of a semiconductor memory device according to Embodiment 27 of the present invention. FIG.

Claims (84)

Having source and drain regions,
The drain region is provided above or below the source region via an insulating film,
The source region is connected to a drain region via a channel region,
The channel region is connected to a gate electrode via a gate insulating film,
Having a carrier confinement region near the channel region,
A semiconductor memory device wherein data is stored by changing a threshold voltage of a semiconductor device by holding carriers in the carrier confinement region. The semiconductor device according to claim 1,
A semiconductor memory element in which a carrier confinement region is made of semiconductor or metal fine particles having an average minor axis of 10 nm or less. The semiconductor device according to claim 1,
A semiconductor memory element wherein a channel region is made of a semiconductor thin film having an average thickness of 10 nm or less. Having a source region and two drain regions, the source region and the two drain regions are provided above and below in order of a drain region, a source region, and a drain region via an insulating film,
The source region is connected to each drain region via a channel region,
The channel region is connected to a gate electrode via a gate insulating film,
Having a carrier confinement region near the channel region,
A semiconductor memory device wherein data is stored by changing a threshold voltage of a semiconductor device by holding carriers in the carrier confinement region. Having source and drain regions,
Having a plurality of gate electrodes provided above and below each other via an insulating film,
Having a channel region provided on the side surface of the gate electrode via an insulating film,
The source region is connected to a drain region via a channel region,
Having a carrier confinement region near the channel region,
The storage is performed by changing the threshold voltage of the semiconductor element by holding the carrier in the carrier confinement region,
A semiconductor memory element in which a carrier confinement region is made of semiconductor or metal fine particles having an average minor axis of 10 nm or less. Having source and drain regions,
Having a plurality of gate electrodes provided above and below each other via an insulating film,
Having a channel region provided on the side surface of the gate electrode via an insulating film,
The source region is connected to a drain region via a channel region,
Having a carrier confinement region near the channel region,
The storage is performed by changing the threshold voltage of the semiconductor element by holding the carrier in the carrier confinement region,
A semiconductor memory element wherein a channel region is made of a semiconductor thin film having an average thickness of 10 nm or less. Having source and drain regions,
Having a plurality of gate electrodes provided above and below each other via an insulating film,
Having a channel region provided on the side surface of the gate electrode via an insulating film,
The source region is connected to a drain region via a channel region,
A semiconductor memory element, wherein one element stores information of a bit number equal to or more than the number of the plurality of gate electrodes. Having source and drain regions,
The drain region is provided above or below the source region via an insulating film,
The source region is connected to a drain region via a channel region,
The channel region is connected to a gate electrode via a gate insulating film,
Having a carrier confinement region near the channel region,
The storage is performed by changing the threshold voltage of the semiconductor element by holding the carrier in the carrier confinement region,
A semiconductor memory element, wherein an insulating film made of a material different from that of the insulating film between the source region and the drain region is in contact with both the source region and the drain region. Having source and drain regions,
The drain region is provided above or below the source region via an insulating film,
The source region is connected to a drain region via a channel region,
The channel region is connected to a gate electrode via a gate insulating film,
Having a carrier confinement region near the channel region,
In a semiconductor device that performs storage by changing a threshold voltage of a semiconductor device by holding carriers in the carrier confinement region,
Forming at least two types of insulating films of different materials after the formation of the source region and the drain region,
After the step of forming the at least two types of insulating film, having an etching step to expose the source region or the drain region,
A semiconductor memory device comprising a deposition or epitaxial growth step for forming a channel region after the etching step. Having source and drain regions on the insulating film,
The drain region is provided above or below the source region via an insulating film,
The source region is connected to a drain region via a channel region,
The channel region is connected to a gate electrode via a gate insulating film,
Having a carrier confinement region near the channel region,
The storage is performed by changing the threshold voltage of the semiconductor element by holding the carrier in the carrier confinement region,
A semiconductor element, wherein a lowermost region of the source region and the drain region is in electrical contact with a part of a semiconductor substrate without a metal. The semiconductor device according to any one of claims 1 to 4, and 8 to 10,
A semiconductor device comprising a step of processing the source region and the drain region collectively by using the same resist pattern. The semiconductor device according to claim 11,
A step of etching a source region or a drain region other than the uppermost region before forming the uppermost region of the source region and the drain region. element. The semiconductor device according to any one of claims 5 to 7,
A semiconductor device comprising a step of processing the plurality of gate electrodes collectively with the same resist pattern. The semiconductor memory device according to claim 11,
A semiconductor element, comprising a step of forming an insulating layer on the uppermost layer of the source region and the drain region before the batch processing of the source region and the drain region. The semiconductor memory device according to claim 13,
A semiconductor device comprising a step of forming an insulating layer on an uppermost layer of a plurality of gate electrodes before the batch processing of the plurality of gate electrodes. The semiconductor device according to any one of claims 1 to 15,
A semiconductor device having a plurality of channel regions separated from each other and controlled by the same gate electrode. The semiconductor device according to any one of claims 1 to 16,
A semiconductor element, wherein a channel region and a storage region are formed integrally. The semiconductor device according to any one of claims 1 to 16,
A semiconductor element, wherein a channel and a storage region are formed separately. The semiconductor device according to any one of claims 3, 4, 6 to 18,
A semiconductor memory element in which a carrier confinement region is made of semiconductor or metal fine particles having an average minor axis of 10 nm or less. The semiconductor device according to any one of claims 2, 5, 11 to 19,
A semiconductor memory element comprising a plurality of semiconductor or metal fine particles forming a carrier confinement region. The semiconductor memory device according to claim 1, wherein
A semiconductor memory device, wherein at least one of the source region and the drain region is provided in a semiconductor substrate. The semiconductor memory device according to claim 1, wherein
A semiconductor memory device, wherein the source region or the drain region is made of polycrystalline silicon. The semiconductor device according to any one of claims 1 to 22,
A semiconductor device having a minimum effective width of a channel region of 20 nm or less. The semiconductor device according to any one of claims 1 to 23,
A semiconductor element including a step of forming an amorphous thin film having a thickness of 10 nm or less for forming a carrier confinement region. The semiconductor device according to any one of claims 1 to 24,
A semiconductor device, wherein a material between a channel region and a carrier confinement region is different from a material between a carrier confinement region and a gate electrode.   26. The semiconductor device according to claim 1, wherein the channel region is made of a semiconductor thin film having an average thickness of 10 nm or less. A plurality of the semiconductor elements according to any one of claims 3, 6, and 26 are arranged,
A semiconductor memory device, wherein semiconductor thin films in channel regions of the plurality of semiconductor elements are not separated by etching. The semiconductor device according to any one of claims 5 to 7, 13, and 15,
A semiconductor memory element, wherein a semiconductor thin film in each channel region controlled by the plurality of gate electrodes is not separated by etching. A plurality of the semiconductor elements according to any one of claims 1 to 26, 28 are arranged,
A semiconductor memory device, wherein the plurality of semiconductor elements are controlled by word lines and data lines. 28. The semiconductor memory device according to claim 27,
A semiconductor memory device, wherein the plurality of semiconductor elements are controlled by word lines and data lines. 31. The semiconductor memory device according to claim 29,
A semiconductor memory device, wherein the plurality of semiconductor elements are controlled by word lines and data lines.   30. A semiconductor memory device comprising the semiconductor element according to claim 1 formed in two or more layers in a stacked manner. A plurality of the semiconductor elements according to any one of claims 1 to 28 and 30 are arranged in the same plane,
A structure in which a plurality of the above semiconductor elements are arranged is formed in two or more layers in a stacked state,
A semiconductor memory device, wherein the plurality of semiconductor elements are controlled by word lines and data lines. A plurality of the semiconductor elements according to claim 4 are arranged,
Connecting the gate regions of the semiconductor element to each other,
The two drain regions of the semiconductor element, which are in a vertical positional relationship with each other, are connected to the same data line via respective select transistors,
A semiconductor memory device, wherein the plurality of semiconductor elements are controlled by the gate region connected to the data line. The semiconductor memory device according to any one of claims 29 to 33,
A semiconductor memory device, wherein at least two drain regions of a semiconductor memory element included in the semiconductor memory device, which are vertically positioned with respect to each other, are connected to the same data line via a selection transistor. It has a source line, two local data lines and a global data line,
The source line and the two local data lines are respectively provided above and below the local data line, the source line, and the local data line with the insulating film interposed therebetween,
A channel region on a side surface of the insulating film separating the source line and the local data line, wherein the source line is connected to upper and lower local data lines via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
Upper and lower two semiconductor storage elements are formed at the intersection of the local data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor memory elements are arranged in a matrix by arranging a plurality of local data lines and word lines,
The upper and lower two local data lines are connected to the same global data line via select transistors each having a different gate electrode,
Between the contact holes connecting the upper and lower local data lines and the select transistor,
A semiconductor memory device having a contact hole for connecting a global data line and a select transistor. It has a source line, two local data lines and a global data line,
The source line and the two local data lines are respectively provided above and below the local data line, the source line, and the local data line with the insulating film interposed therebetween,
A channel region on a side surface of the insulating film separating the source line and the local data line, wherein the source line is connected to upper and lower local data lines via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
Upper and lower two semiconductor storage elements are formed at the intersection of the local data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor memory elements are arranged in a matrix by arranging a plurality of local data lines and word lines,
The upper and lower two local data lines each have a different gate electrode, and are further connected to the same global data line via a select transistor having a shared structure of a diffusion layer,
A semiconductor memory device, wherein the connection hole between the shared diffusion layer and the global data line penetrates at least one local data line. It has a source line and a data line,
The source line and the data line are provided above and below each other with an insulating film interposed therebetween,
Having a channel region on the side of the insulating film separating the source line and the data line,
The source line is connected to a data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
A semiconductor storage element is formed at the intersection of the data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor storage elements are arranged in a matrix by arranging a plurality of data lines and word lines,
Formed of the same material parallel to the data line,
Has substantially the same line width as the data line,
A semiconductor memory device having a dummy data line not used for storing information. It has a source line and a data line,
The source line and the data line are provided above and below each other with an insulating film interposed therebetween,
Having a channel region on the side of the insulating film separating the source line and the data line,
The source line is connected to a data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
A semiconductor storage element is formed at the intersection of the data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor storage elements are arranged in a matrix by arranging a plurality of data lines and word lines,
A semiconductor memory device, wherein an insulating film is formed on an inner wall of a contact hole for the source line or the data line. It has a source line and a data line,
The source line and the data line are provided above and below each other with an insulating film interposed therebetween,
Having a channel region on the side of the insulating film separating the source line and the data line,
The source line is connected to a data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
A semiconductor storage element is formed at the intersection of the data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor storage elements are arranged in a matrix by arranging a plurality of data lines and word lines,
A semiconductor memory device comprising an insulating film formed by oxidizing a deposited semiconductor on a side surface of the insulating film separating the source line and the data line. Having a source line and a data line provided on the insulating film,
The source line and the data line are provided above and below with an insulating film interposed therebetween,
Having a channel region on the side of the insulating film separating the source line and the data line,
The source line is connected to a data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
By performing the storage by changing the threshold voltage of the semiconductor storage element by holding the carrier in the carrier confinement region,
In addition, in a semiconductor storage device having a semiconductor element provided on a surface of a semiconductor substrate,
A semiconductor memory device having a structure in which at least one of the source line and the data line and a position of a contact hole to a diffusion layer or a gate electrode of a semiconductor element provided on a surface of the semiconductor substrate overlap. It has a source line and a data line,
The source line and the data line are provided above and below each other via an insulating film,
Having a channel region on the side of the insulating film separating the source line and the data line,
The source line is connected to a data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
A semiconductor storage element is formed at the intersection of the data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In the semiconductor memory device in which the data lines and the word lines are arranged in a matrix,
It is made of the same material as the data line, has a dummy pattern not used as the data line,
A semiconductor memory device having a structure in which a contact hole for a word line is located on the dummy pattern. It has a source line and a data line,
The source line and the data line are provided above and below each other via an insulating film,
Having a channel region on the side of the insulating film separating the source line and the data line,
The source line is connected to a data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
A semiconductor storage element is formed at the intersection of the data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In the semiconductor memory device in which the data lines and the word lines are arranged in a matrix,
It is made of the same material as the data line, has a dummy pattern not used as the data line,
A semiconductor memory device characterized in that a semiconductor film exists on the side of the insulating film of the dummy pattern over a length of 1 μm or more in the longitudinal direction of the dummy pattern. It has a source line and a data line,
The source line and the data line are provided above and below each other with an insulating film interposed therebetween,
Having a channel region on the side of the insulating film separating the source line and the data line,
The source line is connected to a data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
A semiconductor storage element is formed at the intersection of the data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor storage elements are arranged in a matrix by arranging a plurality of data lines and word lines,
A semiconductor memory device, wherein a power supply line of a memory information read circuit of the semiconductor memory element is parallel to a word line. It has a source line, a local data line, and a global data line,
The source line and the local data line are provided above and below with an insulating film interposed therebetween,
A channel region on an insulating film side surface separating the source line and the local data line, wherein the source line is connected to the local data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor memory elements are arranged in a matrix by arranging a plurality of local data lines and word lines,
The local data line is connected to a global data line via a selection transistor,
A semiconductor memory device, wherein the global data line is formed using a second metal wiring layer from the bottom or an upper metal wiring layer. Having a global data line composed of a source line, a local data line, and a metal,
The source line and the local data line are provided above and below with an insulating film interposed therebetween,
A channel region on an insulating film side surface separating the source line and the local data line, wherein the source line is connected to the local data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor memory elements are arranged in a matrix by arranging a plurality of local data lines and word lines,
The local data line is connected to a global data line,
A read circuit for reading information stored in the semiconductor storage element connected to the global data line;
A semiconductor memory device, wherein wiring of an upper memory information reading circuit is performed using a metal wiring layer lower than a global data line. Having a global data line composed of a source line, a local data line, and a metal,
A channel region connecting the source line and the local data line,
The source line is connected to a local data line through the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor memory elements are arranged in a matrix by arranging a plurality of local data lines and word lines,
A semiconductor memory device, wherein the local data line is connected to a global data line via a MOS transistor. 48. The semiconductor memory device according to claim 47,
In the semiconductor memory elements arranged in a matrix,
The source line and the local data line are provided above and below with an insulating film interposed therebetween,
A semiconductor memory device having a channel region on a side surface of an insulating film separating the source line and the local data line. It has a source line, two local data lines and a global data line,
The source line and the two local data lines are respectively provided above and below the local data line, the source line, and the local data line with the insulating film interposed therebetween,
A channel region on a side surface of the insulating film separating the source line and the local data line, wherein the source line is connected to upper and lower local data lines via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
Upper and lower two semiconductor storage elements are formed at the intersection of the local data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In a semiconductor memory device in which semiconductor memory elements are arranged in a matrix by arranging a plurality of local data lines and word lines,
The upper and lower two local data lines are connected to the same global data line via select transistors each having a different gate electrode,
Different gate electrodes to which the upper and lower two local data lines are connected,
A method for controlling a semiconductor memory device, wherein signals opposite to each other are input. It has a source line and a data line,
The source line and the data line are provided above and below each other via an insulating film,
Having a channel region on the side of the insulating film separating the source line and the data line,
The source line is connected to a data line via the channel region;
A carrier confinement region surrounded by a potential barrier around the channel region;
The channel region is connected to a word line via a gate insulating film,
A semiconductor storage element is formed at the intersection of the data line and the word line,
The semiconductor storage element performs storage by changing a threshold voltage by holding carriers in the carrier confinement region,
In the semiconductor memory device in which the data lines and the word lines are arranged in a matrix,
Using a MOS transistor circuit for the word line drive circuit,
A semiconductor memory device, wherein the MOS transistor circuit includes a triple well MOS transistor. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
In a semiconductor memory device having a structure in which a plurality of the semiconductor memory elements are arranged in a matrix,
A first step of applying a write voltage to the semiconductor storage element;
A second step of reading the information stored in the element after the first step,
A semiconductor memory device having a third step of applying a write voltage again to the semiconductor memory element in which information writing in the second step is insufficient, and a control method thereof. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
In a semiconductor memory device having a structure in which a plurality of the semiconductor memory elements are arranged in a matrix,
Means for holding information (or a list of elements for writing information “1” or information “0”) to be written to the semiconductor storage element outside the semiconductor storage element;
A semiconductor memory device and a control method therefor, further comprising control means for performing a write operation again when the information held in the information holding means does not match the storage state of the semiconductor memory element after application of a write voltage. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
In a semiconductor memory device having a structure in which a plurality of the semiconductor memory elements are arranged in a matrix,
Means for holding a list of elements for writing information “1” or information “0” outside the semiconductor storage element;
A first step of selectively applying a write voltage to the semiconductor storage element according to the above list;
A second step of reading the information stored in the element after the first step,
A third step of updating the list with the read result in the second step,
A semiconductor memory device having a fourth step of determining whether to return to the first step again or end the write operation based on the list result updated in the third step, and a control method therefor. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
In a semiconductor memory device having a structure in which a plurality of the semiconductor memory elements are arranged in a matrix,
Means for holding a list of elements to be erased outside the semiconductor memory element, a first step of selectively applying an erase voltage to the semiconductor memory element according to the list,
A second step of reading the information of the element after the first step,
A third step of updating the list with the read result in the second step,
A semiconductor memory device having a fourth step of determining whether to return to the first step or end the erase operation based on the list result updated in the third step, and a control method therefor. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
In a semiconductor memory device having a structure in which a plurality of the semiconductor memory elements are arranged in a matrix,
A first step of applying an erase voltage to the selected plurality of semiconductor storage elements,
A second step of reading the information of the element after the first step,
A third step of determining whether the erasure of the plurality of storage elements has been completed by the read result in the second step,
A method for controlling a semiconductor memory device, comprising: a fourth step of returning to the first step or terminating the erase operation according to the result of the third step. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
In a semiconductor memory device having a structure in which a plurality of the semiconductor memory elements are arranged in a matrix,
The matrix-shaped semiconductor storage elements are controlled by data lines and word lines,
A means for periodically applying a read voltage to the word line,
A semiconductor memory device comprising: means for writing the same information into the semiconductor memory element again in accordance with a result of reading stored information of the semiconductor memory element controlled by the word line to which the voltage is applied. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
Having a structure in which a plurality of the semiconductor storage elements are arranged in a matrix,
In a semiconductor memory device for controlling the matrix-like semiconductor memory elements by data lines and word lines,
A first step of selecting the word line and applying a read voltage to the semiconductor storage element controlled by the selected word line;
A second step of holding the result read in the first step,
A third step of rewriting the information held in the second step to the semiconductor storage element,
A method for controlling a semiconductor memory device, wherein the first to third steps are repeated while sequentially shifting the word line. The control method of a semiconductor memory device according to claim 57,
In the word line selection performed while sequentially shifting,
A method for controlling a semiconductor memory device, characterized in that a time difference when different word lines are selected is constant. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
Having a structure in which a plurality of the semiconductor storage elements are arranged in a matrix,
In a semiconductor memory device for controlling the matrix-like semiconductor memory elements by data lines and word lines,
A first step of applying a read voltage to the semiconductor storage element controlled by the same word line;
A second step of holding the result read in the first step,
A method for controlling a semiconductor memory device, comprising a third step of writing the information held in the second step to the semiconductor memory element. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
In a semiconductor memory device having a structure in which a plurality of the semiconductor memory elements are arranged in a matrix,
The matrix-shaped semiconductor storage elements are controlled by data lines and word lines,
A semiconductor memory device wherein two or more bits are stored in one semiconductor memory element by using a plurality of values for a write voltage applied to the word line. 61. The semiconductor memory device according to claim 60,
A semiconductor memory device, wherein an equal value is used for the plurality of write voltage values. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the carrier confinement region;
Having a structure in which a plurality of the semiconductor storage elements are arranged in a matrix,
The matrix-shaped semiconductor storage elements are controlled by data lines and word lines,
A semiconductor memory device wherein two or more bits are stored in one semiconductor memory element by using a plurality of values for a write pulse width applied to the word line. 63. The semiconductor memory device according to claim 62,
A semiconductor memory device, wherein an equal value is used for the plurality of write pulse widths. 55. The method of controlling a semiconductor memory device according to claim 54,
Before the first step above,
Applying a write voltage to a semiconductor memory element from which the stored information is erased. The control method of a semiconductor memory device according to any one of claims 57 to 59,
A method of controlling a semiconductor memory device, comprising the step of performing an erase operation on the semiconductor memory element controlled by the word line after the second step and before the third step. A control method of a semiconductor memory device according to any one of claims 51 and 53,
In addition to the control method of the above claim,
A method for controlling a semiconductor memory device, comprising using the method for controlling a semiconductor memory device according to any one of claims 54, 55, and 64. The method for controlling a semiconductor memory device according to claim 65,
Using the control method according to claim 54 for the erasing operation,
A storage unit for storing a read result in the control method according to claim 65;
55. A semiconductor memory device and a control method thereof according to claim 54, wherein storage control means for storing a cell list to be erased in said control method is different. The method for controlling a semiconductor memory device according to claim 65,
Using the control method according to claim 54 for the erasing operation,
Before the step corresponding to the third step of the control method according to claim 54, the contents of the storage means holding the read result in the control method according to claim 65 are transferred to another storage means. A semiconductor memory device and a control method thereof. The control method of a semiconductor memory device according to any one of claims 51, 53 to 55, 64, and 66,
In addition to the control method of the above claim,
A method for controlling a semiconductor memory device, comprising using the method for controlling a semiconductor memory device according to any one of claims 57 to 59, 65, 67, and 68. The control method of a semiconductor memory device according to any one of claims 51, 53 to 5, 64, 66, and 69,
In addition to the control method of the above claim,
A method for controlling a semiconductor memory device, comprising using the method for controlling a semiconductor memory device according to any one of claims 60 to 64. 71. The semiconductor memory device or the method for controlling a semiconductor memory device according to claim 51,
A semiconductor memory device or a control method thereof, wherein the source region and the drain region of the semiconductor memory element are connected to each other via a semiconductor having an average thickness of 8 nm or less. 72. The semiconductor memory device or the method for controlling a semiconductor memory device according to claim 71,
A semiconductor memory device or a control method thereof, wherein a semiconductor connecting the source region and the drain region of the semiconductor memory element is made of polycrystalline silicon. 72. The semiconductor memory device or the method for controlling a semiconductor memory device according to claim 51,
The storage area of the semiconductor storage element,
A semiconductor memory device or a control method thereof, wherein a semiconductor connecting the source region and the drain region of the semiconductor memory element is formed integrally. A first source region and a first drain region;
The first source region is connected to the first drain region via a first channel region;
The first channel region is connected to a first gate electrode via an insulating film,
A first carrier confinement region near the current path of the first channel region;
A first semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the first carrier confinement region;
A second source region and a second drain region;
The second source region is connected to the second drain region via a second channel region;
The second channel region is connected to a second gate electrode via an insulating film,
A second carrier confinement region near the current path of the second channel region;
A second semiconductor storage element that performs storage by changing a threshold voltage by holding carriers in the second carrier confinement region;
The first drain region of the first semiconductor memory element is connected to a first local data line,
The second drain region of the second semiconductor memory element is connected to a second local data line,
In a semiconductor memory device in which the first gate electrode of the first semiconductor memory element and the second gate electrode of the second semiconductor memory element are connected to the same word line,
The first and second local data lines are connected to a common global data line via select transistors each having a different gate electrode, and the first and second semiconductors are sequentially or simultaneously selected by selecting the select transistors. A semiconductor memory device for driving a memory element.   75. The semiconductor memory device according to claim 74, wherein said first and second local data lines are vertically stacked.   75. The semiconductor memory device according to claim 74, wherein said first and second local data lines are arranged in a plane. A first source region and a first drain region;
The first source region is connected to the first drain region via a first channel region;
The first channel region is connected to a first gate electrode via an insulating film,
A first carrier confinement region near the current path of the first channel region;
A first semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the first carrier confinement region;
A second source region and a second drain region;
The second source region is connected to the second drain region via a second channel region;
The second channel region is connected to a second gate electrode via an insulating film,
A second carrier confinement region near the current path of the second channel region;
A second semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the second carrier confinement region;
Having a differential amplifier,
The first drain region of the first semiconductor memory element is connected to a first local data line,
The second drain region of the second semiconductor memory element is connected to a second local data line,
The first local data line is connected to a first global data line via a first selection transistor;
The second local data line is connected to a second global data line via a second selection transistor;
The first global data line drives a first input terminal of the differential amplifier; the second global data line drives a second input terminal of the differential amplifier; In a semiconductor memory device for reading information of the semiconductor memory element by reading a signal,
The first gate electrode of the first semiconductor storage element and the second gate electrode of the second semiconductor storage element are connected to the same word line, and the first and second selection transistors are sequentially or simultaneously connected. A semiconductor memory device wherein the first and second semiconductor memory elements are driven by selection. A first source region and a first drain region;
The first source region is connected to the first drain region via a first channel region;
The first channel region is connected to a first gate electrode via an insulating film,
A first carrier confinement region near the current path of the first channel region;
A semiconductor memory element that performs storage by changing a threshold voltage by holding carriers in the first carrier confinement region;
A second source region and a second drain region;
The second source region is connected to the second drain region via a second channel region;
The second channel region is connected to a second gate electrode via an insulating film,
A second carrier confinement region near the current path of the second channel region;
A dummy semiconductor storage element that performs storage by changing a threshold voltage by holding carriers in the second carrier confinement region;
Having a differential amplifier,
The first drain region is connected to a first data line,
The second drain region is connected to a second data line,
The first data line drives a first input terminal of the differential amplifier;
The second data line drives a second input terminal of the differential amplifier;
In a semiconductor memory device for reading information of the semiconductor memory element by reading an output signal of the differential amplifier,
When reading information from the semiconductor storage element,
Determining whether or not the writing has been completed after performing the writing operation on the semiconductor storage element;
A semiconductor memory device characterized in that a threshold voltage of the dummy semiconductor memory element is used as a reference in any case of determining whether erasure is completed after performing an erase operation on the semiconductor memory element. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A plurality of semiconductor storage elements that perform storage by changing a threshold voltage by holding carriers in the carrier confinement region;
A first operation of erasing information stored in the semiconductor storage element;
A second operation of performing erasure again on the semiconductor element which has been insufficiently erased after the first operation;
A third operation of writing information "1" or information "0" to the semiconductor storage element, a fourth operation of writing again to the semiconductor element having insufficient writing after the third operation,
In a semiconductor memory device having a fifth operation of reading information stored in the semiconductor element,
A register for holding information “1” or information “0” outside the semiconductor memory device;
Means for holding a list of the semiconductor storage elements that are insufficiently erased after the first operation or a list of the semiconductor storage elements that have been erased,
Means for holding information to be written to the semiconductor storage element at the time of the third operation; and a list of the semiconductor storage elements for which writing is insufficient after the third operation or a list of the semiconductor storage elements for which writing has been completed. Means for holding;
A semiconductor memory device, wherein the same register is used as a means for holding information read from the semiconductor memory element at the time of the fifth operation. A source region and a drain region,
The source region is connected to the drain region via a channel region,
The channel region is connected to a gate electrode via an insulating film,
A carrier confinement region near the current path in the channel region;
A plurality of semiconductor storage elements that perform storage by changing a threshold voltage by holding carriers in the carrier confinement region;
A first operation of writing information “1” or information “0” to the semiconductor memory element; and a second operation of writing again to the insufficiently written semiconductor element after the first operation. And
A semiconductor memory device having a register that holds a list of the semiconductor memory elements that are insufficiently written after the first operation or a list of the semiconductor memory elements that have been written.
A semiconductor memory circuit having means for updating the value of the register for the semiconductor memory element for which writing has been completed. 81. The semiconductor memory device according to claim 80,
When the information indicating that the writing is completed is represented by a high-level voltage,
The means for updating the value of the register includes one p-type MOS transistor and one n-type MOS transistor,
The source of the p-type MOS transistor is connected to a high-level power supply,
A drain of the p-type MOS transistor is connected to a drain of the n-type MOS transistor,
Information indicating that the writing has been completed is input to the gate of the n-type MOS transistor,
A source of the n-type MOS transistor is connected to an input terminal of a register that holds information indicating that the writing is completed;
A semiconductor memory device, wherein a control signal is input to a gate of the p-type MOS transistor. 81. The semiconductor memory device according to claim 80,
When the information indicating that the writing is completed is represented by a low-level voltage,
The means for updating the value of the register includes one n-type MOS transistor and one p-type MOS transistor,
The source of the n-type MOS transistor is connected to a low-level power supply,
A drain of the n-type MOS transistor is connected to a drain of the p-type MOS transistor;
Information indicating that the writing has been completed is input to the gate of the p-type MOS transistor,
A source of the p-type MOS transistor is connected to an input terminal of a register that holds information indicating that the writing is completed;
A semiconductor memory device, wherein a control signal is input to a gate of the n-type MOS transistor.   83. The semiconductor memory device according to claim 74, wherein the region for confining the carrier is made of semiconductor or metal fine particles of 10 nm or less. A semiconductor memory device including a plurality of memory cells that store information by accumulating or discharging electric charges, and is formed on a substrate, wherein the memory cells are arranged in pairs in a direction perpendicular to the substrate, The plurality of memory cells are respectively connected to a data line and a word line, and when selecting at least one of the plurality of memory cells, an address signal is input to an address pre-decoder and a local data line decoder, , One word line is selected by a signal from the local data line decoder, and a data line is selected by a signal from the local data line decoder. The selection of the data line is performed by selecting the data lines of the memory cells arranged in pairs in the vertical direction. Are selected simultaneously or separately.

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