JP2004327976A - Pressure welding type semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve ESD resistance and surge resistance at a smaller chip area without employing complex isolation structure in a transverse type MOSFET used for an integrated intelligent switch device, an incoming signal transfer IC of double integrated type, or an integrated power IC. <P>SOLUTION: In a semiconductor device provided with a transistor and a diode which are formed on a same substrate and connected in parallel, resistance of the diode at the time of yield operation is smaller than that of the transistor at the time of yield operation, and secondary breakdown current of the diode is greater than that of the transistor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a semiconductor device having a transistor having high ESD (Electro Static Discharge) resistance and high noise resistance including EMC (Electro Magnetic Compatibility).

2. Description of the Related Art Conventionally, automobile electric equipment and various industrial equipment, motor control, OA (office automation) equipment, mobile (portable) equipment, home electric equipment, and the like, which require high ESD resistance and high noise resistance including EMC (Electro Magnetic Compatibility) are required. , An integrated intelligent switch device in which a plurality of power semiconductor elements (switch elements) and a drive control circuit and the like are integrated on the same chip is used.
In the integrated intelligent switch device, a surge absorbing element is formed on the same semiconductor substrate to protect each element in the device from surge voltage and noise (for example, see Patent Document 1).
FIG. 3 is a cross-sectional view showing a configuration in which a horizontal MOSFET and a vertical diode as a surge absorbing element are formed on the same semiconductor substrate. As shown in FIG. 3, a horizontal power MOSFET 20 and a vertical diode 30 as a surge absorbing element are formed on a semiconductor substrate 10.

The semiconductor substrate 10 comprises a low-concentration n-layer 12 on a high-concentration n-layer 11, p-wells 21 and 31 are formed in a surface region of the low-concentration n-layer 12, and a lateral MOSFET 20 is formed in the p-well 21. A vertical diode 30 is formed in a p-well 31.
The surface of the p-well 31 is connected to an anode electrode 33 via a high-concentration p-layer 32, and the anode electrode 33 is connected to the source electrode 27 of the lateral MOSFET 20 connected via the high-concentration n-layer 22 on the surface of the p-well 21. 35. 25 and 26 are a drain electrode and a gate electrode of the lateral MOSFET 20, respectively.
The electrode 13 formed on the back surface of the semiconductor substrate 10 becomes a cathode electrode of the diode 30 and is connected by a wiring 36 to the drain electrode 25 of the lateral MOSFET 20 connected via the high-concentration n-layer 24 on the surface of the p-well 21. .

In the configuration of FIG. 3, when ESD or surge is applied to the drain electrode of the lateral MOSFET 20, the energy of the ESD or surge is absorbed by the vertical diode 30 and the lateral MOSFET 20 is protected.
JP-A-3-49257 (FIG. 3, etc.)

However, when the above-described device is used for an automobile for which the requirements for ESD resistance and surge noise resistance are strict, an extremely high ESD resistance of 10 kv to 15 kv (test conditions: 150 pF, 150Ω) is required, and in particular, a power semiconductor element. Requires a high ESD resistance of 25 kv or more.
If the above requirements cannot be met with power ICs equipped with MOSFETs, etc., it is necessary to provide external components such as capacitors, diodes, and resistors as discrete components, increasing the number of components and the number of man-hours for assembly and the like. However, there are problems such as an increase in cost.
On the other hand, by employing the configuration shown in FIG. 3, the number of external components can be reduced.

However, a surge absorbing element that satisfies the above requirements is formed with a margin for the desired surge absorbing ability, so that the chip area increases.
In order to reduce the chip area by integrating a plurality of elements on a single chip and increasing the withstand voltage and miniaturization, the area of the surge absorbing element increases because the chip area is reduced and the cost is reduced. Is a big problem. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and does not require an excessive surge absorption capacity, and has a semiconductor device having a lateral MOSFET having high ESD resistance and high surge resistance required in a smaller chip area. The purpose is to provide.

In order to achieve the above object, the present inventors have intensively studied. The contents will be described. The present inventors conducted an experiment to determine the ESD resistance with respect to the element region area of the horizontal MOSFET 20, the vertical MOSFET 20 'and the vertical Zener diode 30 rated at 60V. The result is shown in FIG. The substrate, process conditions and breakdown voltage of the device are the same. In addition, the measurement was performed under the conditions of 150 pF-150Ω mainly used in automobiles in Japan as a measurement condition of the ESD resistance. The ESD withstand voltage required for this automotive use is 10 kV to 15 kV or more, and the actual withstand voltage required for the MOSFETs 20 and 20 ′ is 25 kV or more.
Conventionally, when the above requirements cannot be satisfied, power ICs and the like including the MOSFETs 20 and 20 'have been put to practical use by adding protective capacitors, diodes, resistors, and the like as external discrete components. Instead, there is the disadvantage of increased costs. As can be seen from FIG. 4, the element area needs to be sufficiently large in order to satisfy the above-mentioned ESD resistance requirement using the MOSFETs 20 and 20 '. In particular, the lateral MOSFET 20 requires a large area exceeding 10 mm ² to achieve an ESD withstand voltage of 10 kV. On the other hand, the vertical Zener diode 30 can achieve an ESD resistance of 30 kV with a small element area of 0.2 mm ² at the pad electrode level.

In the lateral MOSFET 20, the on-resistance per unit area is reduced due to miniaturization, and it has been developed to 1 mΩcm ² at a rated voltage of 60V. At present, in the on-resistance region of several hundred mΩ, which is the largest for automotive applications, the element area of the lateral MOSFET ^{20 is} about several mm ² is sufficient. In the future, the device area mounted on the power IC will become smaller and the ESD tolerance will tend to decrease. This time, the present inventors quantified the relationship between the ESD tolerance and the element area of the lateral MOSFET 20, the vertical MOSFET 20 'and the vertical Zener diode 30 on the same scale as data. As a result, it becomes possible to quantitatively deal with the tendency and the problem of the ESD resistance of the horizontal MOSFET 20, the vertical MOSFET 20 'and the vertical Zener diode 30.
In view of the above, in the present invention, in a semiconductor device including a transistor and a diode formed on the same substrate and connected in parallel, the resistance of the diode at the time of breakdown operation is determined by the resistance of the transistor at the time of breakdown operation. The secondary breakdown current of the diode may be smaller than the secondary breakdown current of the transistor. In the above structure, the breakdown voltage of the diode may be smaller than the breakdown voltage of the transistor, or the secondary breakdown voltage of the diode may be smaller than the secondary breakdown voltage of the transistor. What is necessary is just to make the secondary breakdown current of the diode larger than the surge current flowing through the diode.

In each of the above structures, it is preferable that the transistor is constituted by a lateral MOSFET and the diode is constituted by a vertical Zener diode.
In the case where the integrated intelligent switch device is composed of a plurality of transistors, a diode is provided at at least one position between the input terminal and the power supply terminal, between the output terminal and the power supply terminal, and between the power supply terminal and the ground. Preferably, the diode and the transistor satisfy at least one of the above relationships.
In order for the diode and the transistor to satisfy the above relationship, the resistivity of the semiconductor substrate may be set to 0.3 to 10 Ωcm. In addition, a semiconductor layer is preferably provided on the back surface of the semiconductor substrate. For example, the resistivity of the back semiconductor layer may be set to 0.1 Ωcm or less.
Further, in order to set the breakdown voltage of the diode to a desired value, the junction depth and the impurity of the well forming the diode are determined by the conditions under which punch-through or reach-through occurs between the diode and the semiconductor layer on the back surface of the semiconductor substrate. It is determined by the relationship between the concentration and the resistivity and thickness of the semiconductor substrate.

According to the present invention, it is possible to obtain a semiconductor device having a sufficiently small area and a high ESD resistance and a high surge resistance without affecting the operation of the normal MOSFET at all and without impairing the absorption capability of ESD, surge and the like. Therefore, the reduction of the ESD resistance and the surge noise resistance due to the fine integration of the semiconductor device is suppressed, and the high ESD resistance and the high surge resistance are realized by using a lower-cost semiconductor substrate without causing a significant increase in the chip area. It is possible to realize a lower-cost integrated power IC, an integrated communication IC, and the like having noise immunity.

In a semiconductor device according to an embodiment of the present invention, a lateral MOSFET and a Zener diode as a vertical surge absorbing element are formed on the same semiconductor substrate without forming a special element isolation structure, and a drain of the lateral MOSFET is formed. An electrode or a source electrode and a surface electrode of the vertical Zener diode are electrically connected by metal electrode wiring.
FIG. 1 is a diagram showing IV characteristics of a lateral MOSFET 20 as a transistor and a Zener diode 30 as a surge absorbing element.
First, the resistance (RB _(MOS) ) of the lateral MOSFET 20 at the time of the breakdown operation is the gradient (di / dv) at the time of the breakdown operation, and the resistance (RB _(ZD) ) of the vertical Zener diode 30 at the time of the breakdown operation. Satisfies the relationship of equation (1),
(Equation 1)
(RB _(ZD) ) <(RB _(MOS) ) (1)
At the same time, the relationship between the secondary breakdown current (I _{SB (MOS)} ) of the lateral MOSFET 20 and the secondary breakdown current (I _{SB (ZD)} ) of the vertical Zener diode 30 is satisfied (condition (2)). 1).
(Equation 2)
(I _{SB (ZD)} )> (I _{SB (MOS)} ) (2)
By simultaneously satisfying the relations of the above equations (1) and (2), protection of the lateral MOSFET from surge can be achieved.

Further, in addition to the relations of the above equations (1) and (2), (3) is set between the breakdown voltage (VB _(MOS) ) of the lateral MOSFET 20 and the breakdown voltage (VB _(ZD) ) of the vertical Zener diode. ) Is satisfied (condition 2).
(Equation 3)
( _{VB (ZD)} ) < _{(VB (MOS)} ) (3)
By simultaneously satisfying the relationships of the above equations (1) to (3), protection of the lateral MOSFET from surge can be achieved.
Alternatively, in addition to the relations of the above equations (1) and (2), the secondary breakdown voltage ( _{VSB (MOS)} ) of the lateral MOSFET 20 and the secondary breakdown voltage ( _{VSB (ZD)} ) of the vertical Zener diode may be changed. It is assumed that the relationship of equation (4) is satisfied between them (condition 3).
(Equation 4)
( _{VSB (ZD)} ) <( _{VSB (MOS)} ) (4)
By simultaneously satisfying the relationships of the above equations (1), (2) and (4), protection of the lateral MOSFET from surge can be achieved.

It is also assumed that the above expressions (1) to (4) are simultaneously satisfied (condition 4). This makes it possible to protect the lateral MOSFET from surges.
Further, in addition to the relations of the above equations (1) and (2), a surge current (I _surge) flowing through the vertical Zener diode 30 at a desired ESD and surge noise immunity is obtained, and the secondary breakdown of the vertical Zener diode 30 is obtained. It is assumed that the relationship of the expression (5) is satisfied with the current (I _{SB (ZD)} ) (condition 5).
(Equation 5)
(I _surge ) <(I _{SB (ZD)} ) (5)
By simultaneously satisfying the relations of the above equations (1), (2) and (5), it is possible to prevent the vertical Zener diode from being destroyed by the surge and to protect the horizontal MOSFET from the surge.

Here, the surge current (I _surge ) is, for example, a current that flows when a surge voltage of 25 kv is assumed under the test conditions of 150 pF and 150 Ω, and a current of about 100 A instantaneously flows through a path F in FIG. Flows. The measurement conditions are arbitrarily set according to the specifications of the element, and the surge voltage is also arbitrarily set according to the characteristics of the element.
In order to satisfy the above relationship between the vertical Zener diode 30 and the horizontal MOSFET 20, the resistivity of the semiconductor substrate on which both elements are formed may be 0.3 to 10 Ωcm. In addition, a semiconductor layer is preferably provided on the back surface of the semiconductor substrate. For example, the resistivity of the back semiconductor layer may be set to 0.1 Ωcm or less.
Further, in order to set the breakdown voltage (VB ( _ZD) ) of the vertical Zener diode to a desired value, punch-through is performed between the well region where the vertical Zener diode 30 is formed and the semiconductor layer on the back surface of the semiconductor substrate. Alternatively, the junction depth and the impurity concentration of the well layer and the resistivity and the thickness of the semiconductor substrate may be determined on condition that the reach-through occurs.

For example, in the configuration of FIG. 3, an impurity is ion-implanted at 2.7 × 10 ¹⁴ cm ⁻² on the low-concentration n layer 12 of 0.95 Ωcm to form the p-well 31.
It is preferable that all of the above conditions 1 to 5 are satisfied, but protection of the MOSFET can be achieved by satisfying at least one of the conditions. Therefore, when designing the concentration and layout of each region so that each element constituting the integrated type intelligent switch device can obtain necessary characteristics, the above conditions 1 to 5 can be satisfied without sacrificing the characteristics of each element. What is necessary is just to select the condition which is easy to adopt from among.
〔Example〕
Next, an embodiment will be described with reference to FIG. FIG. 2 is a diagram showing an embodiment of the present invention. Reference numeral 1 denotes an IC composed of a plurality of MOSFETs 2 and includes an input terminal 3, an output terminal 4, and a power supply terminal 5.

When a surge voltage is applied to the IC 1, a surge current flows through paths indicated by arrows A to F. In order to protect the IC 1, that is, the MOSFET 2 constituting the IC 1, from such a surge voltage, a zener diode 6 is provided between the input terminal 3 and the power supply terminal 5, between the output terminal 4 and the power supply terminal 5, and between the power supply terminal 5 and the ground. I have.
At this time, it is assumed that at least one of the above-mentioned (condition 1) to (condition 5) is satisfied between the Zener diode 6 and the MOSFET 2.
When the above relationship is satisfied, the operation waveforms of the Zener diode 6 and the MOSFET 2 have the IV characteristics shown in FIG. When a surge such as ESD is applied, a voltage of V _surge is applied to the Zener diode 6 and the MOSFET 2, and a current of I _surge flows through the Zener diode 6. At this time, if the above condition is satisfied, the surge voltage V _surge applied to the MOSFET 2 does not exceed the secondary breakdown voltage V _{SB (MOS)} of the MOSFET 2 and the MOSFET 2 is surely protected from being destroyed by surges such as ESD. Can be protected.

With this configuration, the size of the surge absorbing element can be optimized, and the chip size of the integrated intelligent switch device can be reduced.
In FIG. 2, a Zener diode is disposed in each path. However, when a mode in which a surge voltage is applied can be specified, a surge absorbing element may be disposed at least between its terminals, and a surge absorbing element may be connected to another part. The arrangement can be omitted. By omitting the arrangement of the surge absorbing element, the chip size can be further reduced.
In the above embodiments and examples, the horizontal MOSFET and the vertical Zener diode have been described as examples of the surge absorbing element. However, the present invention is not limited to this, and an element satisfying the above conditions 1 to 5 is adopted. be able to.

It is a figure which shows a lateral MOSFET and Zener diode IV characteristic. FIG. 2 is a cross-sectional view illustrating a configuration of an example of the present invention. It is sectional drawing which shows the structure of the conventional integrated type intelligent switch device. It is a characteristic view which shows the experimental result of ESD with respect to an element area about a horizontal MOSFET, a vertical MOSFET, a vertical Zener diode of 60V rating, and a horizontal MOSFET provided with high ESD tolerance.

Explanation of reference numerals

1 IC
2 MOSFET
Reference Signs List 3 input terminal 4 output terminal 5 power supply terminal 6 Zener diode 11 high concentration n layer (semiconductor substrate)
12 Low concentration n-layer (semiconductor substrate)
13 Back electrode (cathode electrode)
20 Surge absorbing element (vertical diode)
21, 31 p well 22, 24 n-type high concentration layer 23 n base 25 drain electrode 26 gate electrode 27 source electrode 32 p-type high concentration layer 33 anode electrode 35, 36 wiring

Claims (6)

In a semiconductor device formed on the same substrate and having a transistor and a surge absorbing element connected in parallel,
A semiconductor device, wherein the resistance of the surge absorbing element during breakdown operation is smaller than the resistance of the transistor during breakdown operation, and the secondary breakdown current of the surge absorbing element is larger than the secondary breakdown current of the transistor. .   2. The semiconductor device according to claim 1, wherein a breakdown voltage of said surge absorbing element is smaller than a breakdown voltage of said transistor.   3. The semiconductor device according to claim 1, wherein a secondary breakdown voltage of the surge absorbing element is smaller than a secondary breakdown voltage of the transistor. 4.   2. The semiconductor device according to claim 1, wherein a secondary breakdown current of the surge absorbing element is larger than a surge current flowing through the surge absorbing element.   2. The semiconductor device according to claim 1, wherein said transistor is a lateral MOSFET, and said diode is a Zener diode.   In a semiconductor device including a plurality of transistors, a surge absorbing element is provided in at least one portion between an input terminal and a power terminal, between an output terminal and a power terminal, and between a power terminal and a ground of the semiconductor device. 5. The semiconductor device according to claim 1, wherein the transistor satisfies at least one of the above-described relationships.

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