JP2004327658A

JP2004327658A - Semiconductor memory device and its manufacturing method

Info

Publication number: JP2004327658A
Application number: JP2003119365A
Authority: JP
Inventors: Katsumi Mori; 克己森
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2003-04-24
Filing date: 2003-04-24
Publication date: 2004-11-18

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device wherein a cross point-type FeRAM includes a ferroelectric capacitor which is less likely to have damages, and which can use interconnections made of a low-melting point material and has little deterioration in characteristics; and also to provide a method of manufacturing the same. <P>SOLUTION: On an insulation film 11, a first electrode interconnection 12 is so formed as to be extended in a prescribed direction X. On the first electrode interconnection 12, a protection film 13 is formed. On an interlayer insulation film 14, a second electrode interconnection 20 is so formed as to be extended in a prescribed direction Y crossing the extended direction of the first electrode interconnection 12. In an intersection between the first electrode interconnection 12 and the second electrode interconnection 20, an opening 15 is formed. Inside the opening 15, a first electrode film 16 electrically connected at least with the first electrode interconnection 12, a second electrode film 18 electrically connected to the second electrode interconnection 20 via an embedded conductive member 19, and a ferroelectric film 17 between the first and second electrode films 16 and 18 are formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、特にクロスポイント型のＦｅＲＡＭ（ＦｅｒｒｏｅｌｅｃｔｒｉｃＲａｎｄｏｍＡｃｃｅｓｓＭｅｍｏｒｙ）セルを有する半導体記憶装置及びその製造方法に関する。
【０００２】
【従来の技術】
ＦｅＲＡＭ、いわゆる強誘電体メモリは高速性、低消費電力、高集積性、耐書き換え特性に優れた不揮発性メモリの一つである。強誘電体メモリは強誘電体膜のヒステリシス特性、すなわち高速分極反転とその残留分極を利用する高速書き換えが可能である。特にクロスポイント型のＦｅＲＡＭは、下部電極と上部電極が強誘電体膜を介して交差させた構造のメモリセルがマトリクス状に配列される構成を有し、高集積性に優れている。
【０００３】
図９は、従来のクロスポイント型のＦｅＲＡＭにおける一部のメモリセル部を示す断面図である。半導体基板上の所定層に下部電極１０１が形成されている。下部電極１０１上の所定領域には強誘電体膜１０２及び上部電極１０３を配している。これらの構成上に層間絶縁膜１０４が形成されている。層間絶縁膜１０４上の所定の開孔部１０５は上部電極１０３に到達し、開孔部１０５には上部配線１０６が埋め込まれている。上部配線１０６は下部電極１０１と交差する方向に伸長して形成されている。メモリ部は、下部電極１０１上に形成された、強誘電体膜１０２及び上部電極１０３の強誘電体キャパシタを有するメモリセルが複数配列される構成となっている。
【０００４】
クロスポイント型のＦｅＲＡＭにおいては、下部電極１０１の副ビット線電位と上部電極１０３に繋がる上部配線１０６のワード線電位の関係を制御して、それぞれ強誘電体膜１０２を有する強誘電体キャパシタを所定の印加電界方向に分極させる。選択されたメモリセルは、強誘電体キャパシタの分極状態に応じた副ビット線電位となり、図示しない選択トランジスタ及びビット線に伝達される。このようなクロスポイント型のＦｅＲＡＭは例えば特許文献１に開示されている。
【０００５】
【特許文献１】
特開平９−１１６１０７（第５−１０頁）
【０００６】
【発明が解決しようとする課題】
上記メモリセル構造に関し、一般に上部電極１０３及び下部電極１０１はＰｔまたはＰｔを含む貴金属の積層で形成されている。これは、強誘電体膜１０２の結晶化、特性を安定化させるリカバリー酸化のための高温アニールに対する電極材料としての酸素耐性が必要とされるからである。Ｐｔ等貴金属をエッチングする際には化学反応エッチングを用いることができず、不活性原子などで物理的にプラズマエッチングするトリミング加工をとる。強誘電体膜１０２は下部電極１０１と共に加工される。その際、強誘電体膜１０２にプラズマや応力によるダメージが入り易い。すなわち、プロセス中に強誘電体膜１０２にダメージが入ることにより、データ保持特性を劣化させる恐れがある。酸素雰囲気中での高温熱処理（リカバリー酸化）によりダメージ回復は可能であるが、Ａｌ等の低融点材料を用いた配線工程以降ではこの熱処理を行うことはできない。
【０００７】
本発明は上記のような事情を考慮してなされたもので、クロスポイント型のＦｅＲＡＭにおいてダメージの入り難い強誘電体キャパシタを有し、低融点材料、また精密加工しやすい材料の配線の使用が可能な特性劣化の少ない半導体記憶装置及びその製造方法を提供しようとするものである。
【０００８】
【課題を解決するための手段】
本発明に係る半導体記憶装置は、半導体基板上の所定層に形成された第１電極配線と、前記第１電極配線を覆う絶縁性の保護膜と、前記保護膜上の層間絶縁膜と、前記層間絶縁膜上において前記第１電極配線と交差するように設けられた第２電極配線と、前記第１電極配線と前記第２電極配線の交差領域に設けられた開孔内に少なくとも前記第１電極配線と電気的に接続される第１電極膜、前記第２電極配線と電気的に接続される第２電極膜、及び前記第１、第２電極膜間の強誘電体膜を含んで構成されたメモリセルキャパシタと、を具備したことを特徴とする。
【０００９】
また、本発明に係る半導体記憶装置は、半導体基板上の所定層に形成された第１電極配線と、前記第１電極配線の所定領域上に形成された第１電極膜と、前記第１電極配線及び前記第１電極膜を覆う絶縁性の保護膜と、前記保護膜上の層間絶縁膜と、前記層間絶縁膜上において少なくとも前記第１電極膜と重なり前記第１電極配線と交差するように設けられた第２電極配線と、前記第１電極配線と前記第２電極配線の交差領域に設けられた開孔内に少なくとも前記第１電極膜上の強誘電体膜、及び前記強誘電体膜上の第２電極膜を含んで構成されたメモリセルキャパシタと、を具備したことを特徴とする。
【００１０】
上記それぞれ本発明に係る半導体記憶装置によれば、メモリセルキャパシタは、第１電極配線と第２電極配線の交差領域に設けられた開孔内に構成されており、開孔に依存した形状が得られる。強誘電体膜にダメージが入り難く、特性劣化が抑えられる。
【００１１】
なお、上記それぞれ本発明に係る半導体記憶装置において、好ましくは次のような特徴を有する。
前記保護膜は少なくとも前記強誘電体膜の側面を覆っていることを特徴とする。ダメージ抑制に寄与する。
前記第２電極配線は前記開孔内への埋め込み金属を介して前記第２電極膜と接続されていることを特徴とする。配線形態の一つである。
前記第２電極配線は前記開孔内に埋め込まれる形態を含んで前記第２電極膜と接続されていることを特徴とする。配線形態の一つである。
前記第１電極配線はアルミニウムを主成分とする金属材料で構成されることを特徴とする。また、前記第２電極配線はアルミニウムを主成分とする金属材料で構成されることを特徴とする。ダメージが低減される強誘電体膜が構成されるので、アルミニウムに支障がない程度の温度の熱処理でダメージ回復が可能である。これにより、アルミニウムを主成分とする金属材料の利用が期待できる。
【００１２】
本発明に係る半導体記憶装置の製造方法は、半導体基板上の所定層に第１電極配線を形成する工程と、前記第１電極配線を絶縁性の保護膜で覆う工程と、前記保護膜上に層間絶縁膜を形成する工程と、前記層間絶縁膜上の所定領域において前記第１電極配線表面に到達する開孔部を形成する工程と、前記開孔部内に前記第１電極配線と接続される第１電極膜を形成する工程と、前記開孔部内の前記第１電極膜上に強誘電体膜を形成する工程と、前記開孔部内の前記強誘電体膜上に第２電極膜を形成する工程と、前記開孔部内の前記第２電極膜に電気的に接続され、かつ前記層間絶縁膜上において前記第１電極配線と交差するように第２電極配線を形成する工程と、を具備したことを特徴とする。
【００１３】
また、本発明に係る半導体記憶装置の製造方法は、半導体基板上の所定層に第１電極配線を形成する工程と、前記第１電極配線の所定領域上に第１電極膜を形成する工程と、前記第１電極配線及び第１電極膜を絶縁性の保護膜で覆う工程と、前記保護膜上に層間絶縁膜を形成する工程と、前記層間絶縁膜上の所定領域において前記第１電極膜表面に到達する開孔部を形成する工程と、前記開孔部内に前記第１電極膜上に強誘電体膜を形成する工程と、前記開孔部内の前記強誘電体膜上に第２電極膜を形成する工程と、前記開孔部内の前記第２電極膜に電気的に接続され、かつ前記層間絶縁膜上において前記第１電極配線と交差するように第２電極配線を形成する工程と、を具備したことを特徴とする。
【００１４】
上記それぞれ本発明に係る半導体記憶装置の製造方法によれば、開孔部に合わせて第１電極膜が形成され、強誘電体膜、第２電極膜が形成される。強誘電体膜にダメージが入り難く、特性劣化が抑えられる。第１電極配線、第２電極配線を構成する材料の選択度が広がる。
【００１５】
なお、上記それぞれ本発明に係る半導体記憶装置の製造方法において、好ましくは次のような特徴を有する。
前記保護膜は少なくとも前記強誘電体膜の側面を覆う厚さが得られるように形成することを特徴とする。ダメージ抑制に寄与する。
前記第２電極配線は前記開孔部内へ金属を埋め込む工程が前提となっていることを特徴とする。埋め込み易い金属を選ぶことができる。
前記強誘電体膜はインクジェット法を用いて前記開孔部内に必要量注入する工程を含んで形成されることを特徴とする。強誘電体膜におけるより均一な膜厚の制御が期待できる。
【００１６】
【発明の実施の形態】
図１は、本発明の第１実施形態に係る半導体記憶装置の要部構成であり、クロスポイント型のＦｅＲＡＭにおける一つのメモリセル部を示す断面図である。半導体基板上に平坦化された絶縁膜１１が設けられている。絶縁膜１１上に所定方向Ｘに伸長するように第１電極配線１２が設けられている。第１電極配線１２は、Ｓｉ半導体に使われる一般的な配線材料で構成される。例えばＡｌ合金のような低融点材料でもよい。また、Ｗ（タングステン）のような高融点材料も考えられる。第１電極配線１２上に保護膜１３が形成されている。保護膜１３は、少なくとも水素バリア性に富む膜、例えばＳｉＮ膜（シリコン窒化膜）やＴａＮ膜（タンタル窒化膜）等で構成される。保護膜１３上に層間絶縁膜１４が形成されている。層間絶縁膜１４上において第１電極配線１２の伸長方向と交差する所定方向Ｙに伸長するように第２電極配線２０が設けられている。第２電極配線２０は、Ｓｉ半導体に使われる一般的な配線材料で構成される。例えばＡｌ合金のような低融点材料でもよい。また、Ｗのような高融点材料も考えられる。
【００１７】
第１電極配線１２と第２電極配線２０の交差領域に開孔部１５が設けられている。開孔部１５内に少なくとも第１電極配線１２と電気的に接続される第１電極膜１６、第２電極配線２０に埋め込み導電部材１９を介して電気的に接続される第２電極膜１８、及び第１、第２電極膜１６，１８間の強誘電体膜１７が設けられている。強誘電体膜１７の側面は水素バリアとしての保護膜１３で覆われる。第１、第２電極膜１６，１８はＰｔを含む貴金属膜である。強誘電体膜１７は、例えば、ＰＺＴ（Ｐｂ（Ｚｒ，Ｔｉ）Ｏ_３）系の化合物、層状構造を有するＢｉ系化合物（ＳＢＴ（ＳｒＢｉ_２Ｔａ_２Ｏ_９）等）などから選択して採用する。第１、第２電極膜１６，１８、その間の強誘電体膜１７によりメモリセルキャパシタＭＣ１が構成されている。メモリセルキャパシタＭＣ１は、図示しないが第１電極配線１２と第２電極配線２０の各交差領域に複数設けられ、マトリクス状のメモリ部を構成する。
【００１８】
上記第１実施形態の構成によれば、メモリセルキャパシタＭＣ１は、第１電極配線１２と第２電極配線２０の交差領域に設けられた開孔部１５内に埋め込まれるように構成されている。つまり、開孔部１５に依存した形状が得られる。強誘電体膜１７はエッチング環境に晒されずダメージが入り難く、メモリセルの特性劣化が抑えられる。以下、製法の一例を説明する。
【００１９】
図２、図３は、図１の構成を実現するための製造工程の要部を示す断面図である。図１と同様の箇所には同一の符号を付す。
図２に示すように、半導体基板上の所定層に設けられる平坦化された下地の絶縁膜１１を形成する。絶縁膜１１は素子分離絶縁膜、またはＳｉＮ膜等バリア機能を備えた絶縁膜でもよい。次に、絶縁膜１１上に第１電極配線１２をパターニング形成する。第１電極配線１２はＡｌ合金を中心としたＳｉ半導体に使われる一般的な配線材料とする。後述する強誘電体膜１７の結晶化温度の低温化ができない場合、第１電極配線１２はＷ等の高融点材料を用いることも考えられる。第１電極配線１２はダマシン技術を用いた埋め込み配線構造でもよい。この第１電極配線１２上に水素バリア性に富む保護膜１３を形成する。保護膜１３は後述する強誘電体膜１７の側面を覆う厚さは確保する。次に、保護膜１３上にＳｉＯ_２膜やＢＰＳＧ（ボロン・リン・シリケートガラス）膜等の層間絶縁膜１４を形成する。層間絶縁膜１４上の所定領域において異方性エッチング技術を用いて第１電極配線１２表面に到達する開孔部１５を形成する。異方性エッチング前のフォトリソグラフィ工程でハードマスクを形成してもよい。
【００２０】
次に、図３に示すように、開孔部１５内に第１電極配線１２と接続される第１電極膜１６を形成する。第１電極膜１６は例えばＰｔを含む貴金属膜であり、スパッタ法により形成する。例えば、低圧スパッタ法やプラズマバイアススパッタ法といった開孔部１５内壁側面には付着されないスパッタ技術を用いる。次に、第１電極膜１６上に強誘電体膜１７を形成する。強誘電体膜１７は、例えば、ＰＺＴ系、ＳＢＴ系化合物などから選択して採用する。強誘電体膜１７はスパッタ法を利用する。その他に、液体（ゾル）状の原料をインクジェット法により塗布する方法も考えられる。インクジェット法を利用する場合、開孔部１５に必要量注入する制御によって均一な強誘電体膜１７の成膜が可能である。また、インクジェット法を利用する場合、強誘電体膜１７の仮焼成、結晶化の熱処理を経る必要がある。第１電極配線１２にＡｌ合金を使用するなら４００℃よりも低温の熱処理で仮焼成、結晶化が実現できるような強誘電体膜物質、あるいは減圧アニール等の低温の熱処理が必要となる。次に、強誘電体膜１７上に第２電極膜１８を形成する。第２電極膜１８は例えばＰｔを含む貴金属膜であり、スパッタ法により形成する。
【００２１】
次に、開孔部１５内の第２電極膜１８にＷを用いた埋め込み導電部材１９を形成し平坦化する。すなわち、図示しないバリア膜被覆後、開孔部１５を十分に埋めるＷをＣＶＤ法等で堆積する。その後、ＣＭＰ（化学的機械的研磨）技術を用いて層間絶縁膜１４上の不要なＷ及びＰｔ等を除去しつつ平坦化する。
次に、埋め込み導電部材１９に接続される第２電極配線２０をパターニング形成する。第２電極配線２０は例えばＡｌ合金で構成される。これにより、前記図１の構成が実現される。すなわち、第２電極配線２０は第１電極配線１２の伸長方向Ｘと交差するようにＹ方向に伸長される。第１、第２電極膜１６，１８、その間の強誘電体膜１７により構成されるメモリセルキャパシタＭＣ１は、図示しないが第１電極配線１２と第２電極配線２０の各交差領域に複数設けられ、マトリクス状のメモリ部を構成する。
【００２２】
このような製造方法によれば、メモリセルキャパシタＭＣ１は、第１電極配線１２と第２電極配線２０の交差領域に設けられた開孔部１５の形状に合わせて形成されるようになる。つまり、第１、第２電極膜１６，１８、その間の強誘電体膜１７に対する加工にはプラズマエッチングが使われないため、プラズマや応力によるダメージが入り難い。従って、強誘電体膜１７に対するリカバリー酸化の熱処理も４００℃よりも低い温度で短時間に達成可能となる。これにより、特に第１電極配線１２にはＡｌ等の低融点材料を用いることも期待でき、微細加工が容易になる。なお、各々示す主要な金属材料の下地には密着材料やバリア膜の被覆が必要なこともあるが省略した。
【００２３】
図４は、上記第１実施形態の変形例を示す構成の断面図である。図１と同様の箇所には同一の符号を付している。図１に比べて第２電極配線の構成が異なっている。第２電極配線２５として、Ｗによるデュアルダマシン構造を採用している。製造方法は、例えば図２の構成の段階で、配線溝２４を予め形成しておき、開孔部１５を形成する。その後、図示しないバリア膜被覆後、開孔部１５及び配線溝２４を埋めるＷをＣＶＤ法により形成する。次に、ＣＭＰ技術を用いて層間絶縁膜１４上の不要なＷ及びＰｔ等を除去しつつ平坦化して図４のような構成を得る。
【００２４】
図５は、本発明の第２実施形態に係る半導体記憶装置の要部構成であり、クロスポイント型のＦｅＲＡＭにおける一つのメモリセル部を示す断面図である。図１と同様の箇所には同一の符号を付している。図１の構成に比べて第１電極膜の配置が開孔部１５形成以前にあるということが異なっている点である。その他の構成は前記第１実施形態と同様である。すなわち、絶縁膜１１上に所定方向Ｘに伸長するように第１電極配線１２が設けられ、その所定領域上に第１電極膜１６ｆが形成されている。第１電極配線１２は、Ｓｉ半導体に使われる一般的な配線材料で構成される。例えばＡｌ合金のような低融点材料でもよい。また、Ｗ（タングステン）のような高融点材料も考えられる。また、第１電極配線１２はダマシン技術を用いた埋め込み配線構造でもよい。第１電極膜１６ｆは、Ｐｔを含む貴金属膜である。この第１電極膜１６ｆは、その他の配置形態として第１電極配線１２上全体に形成されてもよい（図示せず）。第１電極配線１２及び第１電極膜１６ｆの一部上に保護膜１３が形成されている。保護膜１３は、少なくとも水素バリア性に富む膜、例えばＳｉＮ膜やＴａＮ膜等で構成される。保護膜１３上に層間絶縁膜１４が形成されている。層間絶縁膜１４上において少なくとも第１電極膜１６ｆと重なり第１電極配線１２の伸長方向と交差する所定方向Ｙに伸長するように第２電極配線２０が設けられている。第２電極配線２０は、Ｓｉ半導体に使われる一般的な配線材料で構成される。例えばＡｌ合金のような低融点材料でもよい。また、Ｗのような高融点材料も考えられる。
【００２５】
第１電極配線１２と第２電極配線２０の交差領域に開孔部１５が設けられている。開孔部１５内に少なくとも第１電極膜１６ｆ上の強誘電体膜１７、及び強誘電体膜１７上の第２電極膜１８が設けられている。第２電極膜１８はＰｔを含む貴金属膜で埋め込み導電部材１９を介して第２電極配線２０に電気的に接続されている。強誘電体膜１７の側面は水素バリアとしての保護膜１３で覆われる。強誘電体膜１７は、例えば、ＰＺＴ（Ｐｂ（Ｚｒ，Ｔｉ）Ｏ_３）系の化合物、層状構造を有するＢｉ系化合物（ＳＢＴ（ＳｒＢｉ_２Ｔａ_２Ｏ_９）等）などから選択して採用する。第１、第２電極膜１６ｆ，１８、その間の強誘電体膜１７によりメモリセルキャパシタＭＣ２が構成されている。メモリセルキャパシタＭＣ２は、図示しないが第１電極配線１２と第２電極配線２０の各交差領域に複数設けられ、マトリクス状のメモリ部を構成する。
【００２６】
上記第２実施形態の構成によれば、メモリセルキャパシタＭＣ２は、第１電極配線１２と第２電極配線２０の交差領域に設けられた開孔部１５内に埋め込まれる形で形状が決まるように構成されている。強誘電体膜１７はエッチング環境に晒されずダメージが入り難く、メモリセルの特性劣化が抑えられる。以下、製法の一例を説明する。
【００２７】
図６、図７は、図５の構成を実現するための製造工程の要部を示す断面図である。図５と同様の箇所には同一の符号を付す。
図６に示すように、半導体基板上の所定層に設けられる平坦化された下地の絶縁膜１１を形成する。絶縁膜１１は素子分離絶縁膜、またはＳｉＮ膜等バリア機能を備えた絶縁膜でもよい。次に、絶縁膜１１上に第１電極配線１２をパターニング形成する。第１電極配線１２はＡｌ合金を中心としたＳｉ半導体に使われる一般的な配線材料とする。後述する強誘電体膜１７の結晶化温度の低温化ができない場合、第１電極配線１２はＷ等の高融点材料を用いることも考えられる。この第１電極配線１２上の所定領域に第１電極膜１６ｆを形成する。
第１電極膜１６ｆの形成は、例えばフォトリソグラフィ工程を経てマスクを形成し、露出している第１電極配線１２表面にＰｔを含む貴金属膜をスパッタ被覆する。その後、マスクを除去する。次に、水素バリア性に富む保護膜１３を形成する。保護膜１３は後述する強誘電体膜１７の側面を覆う厚さは確保する。次に、保護膜１３上にＳｉＯ_２膜やＢＰＳＧ膜等の層間絶縁膜１４を形成する。層間絶縁膜１４上の所定領域において異方性エッチング技術を用いて第１電極膜１６ｆ表面領域に到達する開孔部１５を形成する。異方性エッチング前のフォトリソグラフィ工程でハードマスクを形成してもよい。
【００２８】
次に、図７に示すように、開孔部１５内において第１電極膜１６ｆ上に強誘電体膜１７を形成する。強誘電体膜１７は、例えば、ＰＺＴ系、ＳＢＴ系化合物などから選択して採用する。強誘電体膜１７はスパッタ法を利用する。その他に、液体（ゾル）状の原料をインクジェット法により塗布する方法も考えられる。インクジェット法を利用する場合、開孔部１５に必要量注入する制御によって均一な強誘電体膜１７の成膜が可能である。また、インクジェット法を利用する場合、強誘電体膜１７の仮焼成、結晶化の熱処理を経る必要がある。第１電極配線１２にＡｌ合金を使用するなら４００℃よりも低温の熱処理で仮焼成、結晶化が実現できるような強誘電体膜物質、あるいは減圧アニール等の低温の熱処理が必要となる。次に、強誘電体膜１７上に第２電極膜１８を形成する。第２電極膜１８は例えばＰｔを含む貴金属膜であり、スパッタ法により形成する。
【００２９】
次に、開孔部１５内の第２電極膜１８にＷを用いた埋め込み導電部材１９を形成し平坦化する。すなわち、図示しないバリア膜被覆後、開孔部１５を十分に埋めるＷをＣＶＤ法等で堆積する。その後、ＣＭＰ技術を用いて層間絶縁膜１４上の不要なＷ及びＰｔ等を除去しつつ平坦化する。
次に、埋め込み導電部材１９に接続される第２電極配線２０をパターニング形成する。第２電極配線２０は例えばＡｌ合金で構成される。これにより、前記図１の構成が実現される。第２電極配線２０は第１電極配線１２の伸長方向Ｘと交差するようにＹ方向に伸長される。第１、第２電極膜１６ｆ，１８、その間の強誘電体膜１７により構成されるメモリセルキャパシタＭＣ２は、図示しないが第１電極配線１２と第２電極配線２０の各交差領域に複数設けられ、マトリクス状のメモリ部を構成する。
【００３０】
このような製造方法によれば、メモリセルキャパシタＭＣ２は、第１電極配線１２と第２電極配線２０の交差領域に設けられた開孔部１５の形状に合わせて形成されるようになる。つまり、第１、第２電極膜１６ｆ，１８、その間の強誘電体膜１７に対する加工にはプラズマエッチングが使われないため、プラズマや応力によるダメージが入り難い。従って、強誘電体膜１７に対するリカバリー酸化の熱処理も４００℃よりも低い温度で短時間に達成可能となる。これにより、特に第１電極配線１２にはＡｌ等の低融点材料を用いることも期待でき、微細加工が容易になる。なお、各々示す主要な金属材料の下地には密着材料やバリア膜の被覆が必要なこともあるが省略した。
【００３１】
図８は、上記第２実施形態の変形例を示す構成の断面図である。図５と同様の箇所には同一の符号を付している。図５に比べて第２電極配線の構成が異なっている。第２電極配線２８として、Ｗによるデュアルダマシン構造を採用している。製造方法は、例えば図６の構成の段階で、配線溝２７を予め形成しておき、開孔部１５を形成する。その後、図示しないバリア膜被覆後、開孔部１５及び配線溝２７を埋めるＷをＣＶＤ法により形成する。次に、ＣＭＰ技術を用いて層間絶縁膜１４上の不要なＷ及びＰｔ等を除去しつつ平坦化して図８のような構成を得る。
【００３２】
以上説明したように、本発明によれば、メモリセルキャパシタの構成は、エッチング加工を用いない埋め込み形態をとり、応力、ダメージの入り難い、かつ加工性に優れた構成を実現することができる。電極配線にＡｌ合金のような低融点材料、また精密加工しやすい材料を用いることが期待できると共に、メモリ部のセル配列ピッチの縮小化に寄与する。この結果、クロスポイント型のＦｅＲＡＭにおいてダメージの入り難い強誘電体キャパシタを有し、低融点材料や精密加工の容易な配線材料が利用でき、より微細で特性劣化の少ない高信頼性の半導体記憶装置及びその製造方法を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１実施形態に係る半導体装置の要部構成であり、クロスポイント型のＦｅＲＡＭにおける一部のメモリ部を示す断面図。
【図２】図１の構成を実現するための途中工程を示す第１断面図。
【図３】図２に続く第２断面図。
【図４】第１実施形態の変形例を示す構成の断面図。
【図５】本発明の第２実施形態に係る半導体装置の要部構成であり、クロスポイント型のＦｅＲＡＭにおける一部のメモリ部を示す断面図。
【図６】図５の構成を実現するための途中工程を示す第１断面図。
【図７】図６に続く第２断面図。
【図８】第２実施形態の変形例を示す構成の断面図。
【図９】従来のクロスポイント型のＦｅＲＡＭにおける一部のメモリセル部を示す断面図。
【符号の説明】
１１…絶縁膜、１２…第１電極配線、１３…保護膜、１４，１０４…層間絶縁膜、１５，１０５…開孔部、１６，１６ｆ…第１電極膜、１７，１０２…強誘電体膜、１８…第２電極膜、１９…埋め込み導電部材、２０，２５，２８…第２電極配線、２４，２７…配線溝、１０１…下部電極、１０３…上部電極、１０６…上部配線。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention particularly relates to a semiconductor memory device having a cross-point type FeRAM (Ferroelectric Random Access Memory) cell and a method of manufacturing the same.
[0002]
[Prior art]
An FeRAM, a so-called ferroelectric memory, is one of the non-volatile memories having high speed, low power consumption, high integration, and excellent rewriting resistance. The ferroelectric memory can perform high-speed rewriting using the hysteresis characteristic of the ferroelectric film, that is, high-speed polarization inversion and its remanent polarization. In particular, the cross-point type FeRAM has a configuration in which memory cells having a structure in which a lower electrode and an upper electrode intersect via a ferroelectric film are arranged in a matrix, and is excellent in high integration.
[0003]
FIG. 9 is a cross-sectional view showing a part of a memory cell part in a conventional cross-point type FeRAM. A lower electrode 101 is formed on a predetermined layer on a semiconductor substrate. A ferroelectric film 102 and an upper electrode 103 are arranged in a predetermined region on the lower electrode 101. On these structures, an interlayer insulating film 104 is formed. A predetermined opening 105 on interlayer insulating film 104 reaches upper electrode 103, and upper wiring 106 is embedded in opening 105. The upper wiring 106 is formed to extend in a direction crossing the lower electrode 101. The memory section has a configuration in which a plurality of memory cells each having a ferroelectric capacitor formed of a ferroelectric film 102 and an upper electrode 103 formed on a lower electrode 101 are arranged.
[0004]
In the cross-point type FeRAM, the relationship between the sub-bit line potential of the lower electrode 101 and the word line potential of the upper wiring 106 connected to the upper electrode 103 is controlled, and the ferroelectric capacitors each having the ferroelectric film 102 are fixed. In the direction of the applied electric field. The selected memory cell has a sub-bit line potential corresponding to the polarization state of the ferroelectric capacitor, and is transmitted to a not-shown selection transistor and a bit line. Such a cross-point type FeRAM is disclosed in Patent Document 1, for example.
[0005]
[Patent Document 1]
JP-A-9-116107 (pages 5 to 10)
[0006]
[Problems to be solved by the invention]
Regarding the memory cell structure, generally, the upper electrode 103 and the lower electrode 101 are formed of Pt or a lamination of a noble metal containing Pt. This is because crystallization of the ferroelectric film 102 and oxygen resistance as an electrode material for high-temperature annealing for recovery oxidation for stabilizing characteristics are required. When etching a noble metal such as Pt, a chemical reaction etching cannot be used, and a trimming process of physically etching with inert atoms or the like is performed. The ferroelectric film 102 is processed together with the lower electrode 101. At this time, the ferroelectric film 102 is easily damaged by plasma or stress. That is, there is a possibility that the data retention characteristics may be degraded due to damage to the ferroelectric film 102 during the process. Damage can be recovered by high-temperature heat treatment (recovery oxidation) in an oxygen atmosphere, but this heat treatment cannot be performed after the wiring step using a low melting point material such as Al.
[0007]
The present invention has been made in view of the above circumstances, and has a ferroelectric capacitor that is unlikely to be damaged in a cross-point type FeRAM, and the use of wiring of a low-melting-point material and a material that is easy to perform precision processing is possible. An object of the present invention is to provide a semiconductor memory device with less possible deterioration in characteristics and a method for manufacturing the same.
[0008]
[Means for Solving the Problems]
The semiconductor memory device according to the present invention includes: a first electrode wiring formed in a predetermined layer on a semiconductor substrate; an insulating protective film covering the first electrode wiring; an interlayer insulating film on the protective film; A second electrode wiring provided on the interlayer insulating film so as to intersect with the first electrode wiring, and at least the first electrode wiring provided in an opening provided in an intersection region between the first electrode wiring and the second electrode wiring. Including a first electrode film electrically connected to the electrode wiring, a second electrode film electrically connected to the second electrode wiring, and a ferroelectric film between the first and second electrode films And a memory cell capacitor.
[0009]
In addition, the semiconductor memory device according to the present invention includes: a first electrode wiring formed on a predetermined layer on a semiconductor substrate; a first electrode film formed on a predetermined region of the first electrode wiring; An insulating protective film covering a wiring and the first electrode film, an interlayer insulating film on the protective film, and at least overlapping the first electrode film on the interlayer insulating film so as to cross the first electrode wiring. A second electrode wiring provided, a ferroelectric film on at least the first electrode film in an opening provided in an intersection region of the first electrode wiring and the second electrode wiring, and the ferroelectric film And a memory cell capacitor including the above second electrode film.
[0010]
According to each of the above semiconductor memory devices according to the present invention, the memory cell capacitor is formed in the opening provided in the intersection region of the first electrode wiring and the second electrode wiring, and the shape depending on the opening is can get. The ferroelectric film is hardly damaged, and characteristic deterioration is suppressed.
[0011]
The semiconductor memory device according to the present invention preferably has the following features.
The protection film covers at least a side surface of the ferroelectric film. Contributes to damage suppression.
The second electrode wiring is connected to the second electrode film via a metal buried in the opening. This is one of the wiring forms.
The second electrode wiring is connected to the second electrode film including a form embedded in the opening. This is one of the wiring forms.
The first electrode wiring is made of a metal material containing aluminum as a main component. The second electrode wiring is made of a metal material containing aluminum as a main component. Since the ferroelectric film whose damage is reduced is formed, damage can be recovered by heat treatment at a temperature at which aluminum is not hindered. Thus, use of a metal material containing aluminum as a main component can be expected.
[0012]
A method for manufacturing a semiconductor memory device according to the present invention includes the steps of: forming a first electrode wiring on a predetermined layer on a semiconductor substrate; covering the first electrode wiring with an insulating protective film; Forming an interlayer insulating film, forming an opening reaching the surface of the first electrode wiring in a predetermined region on the interlayer insulating film, and connecting to the first electrode wiring in the opening. Forming a first electrode film, forming a ferroelectric film on the first electrode film in the opening, and forming a second electrode film on the ferroelectric film in the opening And forming a second electrode wiring on the interlayer insulating film to be electrically connected to the second electrode film in the opening and intersecting the first electrode wiring on the interlayer insulating film. It is characterized by having done.
[0013]
Also, a method of manufacturing a semiconductor memory device according to the present invention includes a step of forming a first electrode wiring on a predetermined layer on a semiconductor substrate, and a step of forming a first electrode film on a predetermined region of the first electrode wiring. Covering the first electrode wiring and the first electrode film with an insulating protective film, forming an interlayer insulating film on the protective film, and forming the first electrode film in a predetermined region on the interlayer insulating film. Forming a hole reaching the surface, forming a ferroelectric film on the first electrode film in the hole, and forming a second electrode on the ferroelectric film in the hole. Forming a film; and forming a second electrode wiring electrically connected to the second electrode film in the opening and intersecting the first electrode wiring on the interlayer insulating film. , Are provided.
[0014]
According to the method of manufacturing a semiconductor memory device according to the present invention, the first electrode film is formed in accordance with the opening, and the ferroelectric film and the second electrode film are formed. The ferroelectric film is hardly damaged, and characteristic deterioration is suppressed. The selectivity of the material forming the first electrode wiring and the second electrode wiring is widened.
[0015]
Each of the above-described methods for manufacturing a semiconductor memory device according to the present invention preferably has the following features.
The protective film is formed so as to have a thickness that covers at least a side surface of the ferroelectric film. Contributes to damage suppression.
The second electrode wiring is premised on a step of embedding a metal in the opening. A metal that can be easily embedded can be selected.
The ferroelectric film is formed including a step of injecting a required amount into the opening using an inkjet method. More uniform film thickness control of the ferroelectric film can be expected.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a cross-sectional view showing a main configuration of a semiconductor memory device according to a first embodiment of the present invention, showing one memory cell unit in a cross-point type FeRAM. A planarized insulating film 11 is provided on a semiconductor substrate. The first electrode wiring 12 is provided on the insulating film 11 so as to extend in the predetermined direction X. The first electrode wiring 12 is made of a general wiring material used for a Si semiconductor. For example, a low melting point material such as an Al alloy may be used. Further, a high melting point material such as W (tungsten) is also conceivable. A protective film 13 is formed on the first electrode wiring 12. The protective film 13 is formed of a film having at least a high hydrogen barrier property, for example, a SiN film (silicon nitride film), a TaN film (tantalum nitride film), or the like. On the protective film 13, an interlayer insulating film 14 is formed. The second electrode wiring 20 is provided on the interlayer insulating film 14 so as to extend in a predetermined direction Y intersecting with the extending direction of the first electrode wiring 12. The second electrode wiring 20 is made of a general wiring material used for a Si semiconductor. For example, a low melting point material such as an Al alloy may be used. Further, a high melting point material such as W is also conceivable.
[0017]
An opening 15 is provided in an intersection area between the first electrode wiring 12 and the second electrode wiring 20. A first electrode film 16 electrically connected to at least the first electrode wiring 12 in the opening 15, a second electrode film 18 electrically connected to the second electrode wiring 20 via the embedded conductive member 19, Further, a ferroelectric film 17 is provided between the first and second electrode films 16 and 18. Side surfaces of the ferroelectric film 17 are covered with a protective film 13 as a hydrogen barrier. The first and second electrode films 16 and 18 are noble metal films containing Pt. The ferroelectric film 17 is selected from, for example, a PZT (Pb (Zr, Ti) O ₃ ) -based compound, a Bi-based compound having a layered structure (SBT (SrBi ₂ Ta ₂ O ₉ )), and the like. . The first and second electrode films 16 and 18 and the ferroelectric film 17 therebetween constitute a memory cell capacitor MC1. Although not shown, a plurality of memory cell capacitors MC1 are provided in each intersection region of the first electrode wiring 12 and the second electrode wiring 20, and constitute a matrix memory unit.
[0018]
According to the configuration of the first embodiment, the memory cell capacitor MC1 is configured to be buried in the opening 15 provided in the intersection area between the first electrode wiring 12 and the second electrode wiring 20. That is, a shape depending on the opening 15 is obtained. The ferroelectric film 17 is not exposed to the etching environment, is hardly damaged, and suppresses deterioration of characteristics of the memory cell. Hereinafter, an example of the manufacturing method will be described.
[0019]
2 and 3 are cross-sectional views showing the main parts of a manufacturing process for realizing the configuration of FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals.
As shown in FIG. 2, a planarized base insulating film 11 provided on a predetermined layer on a semiconductor substrate is formed. The insulating film 11 may be an element isolation insulating film or an insulating film having a barrier function such as a SiN film. Next, the first electrode wiring 12 is formed on the insulating film 11 by patterning. The first electrode wiring 12 is a general wiring material used for a Si semiconductor centering on an Al alloy. If the crystallization temperature of the ferroelectric film 17 described later cannot be lowered, it is conceivable to use a high melting point material such as W for the first electrode wiring 12. The first electrode wiring 12 may have an embedded wiring structure using damascene technology. A protective film 13 rich in hydrogen barrier properties is formed on the first electrode wiring 12. The protective film 13 has a sufficient thickness to cover a side surface of a ferroelectric film 17 described later. Next, an interlayer insulating film 14 such as a SiO ₂ film or a BPSG (boron phosphorus silicate glass) film is formed on the protective film 13. An opening portion 15 reaching the surface of the first electrode wiring 12 is formed in a predetermined region on the interlayer insulating film 14 using an anisotropic etching technique. A hard mask may be formed in a photolithography step before anisotropic etching.
[0020]
Next, as shown in FIG. 3, a first electrode film 16 connected to the first electrode wiring 12 is formed in the opening 15. The first electrode film 16 is, for example, a noble metal film containing Pt, and is formed by a sputtering method. For example, a sputtering technique, such as a low-pressure sputtering method or a plasma bias sputtering method, that is not attached to the inner wall side surface of the opening 15 is used. Next, a ferroelectric film 17 is formed on the first electrode film 16. The ferroelectric film 17 is selected from, for example, a PZT-based compound or an SBT-based compound. The ferroelectric film 17 uses a sputtering method. In addition, a method of applying a liquid (sol) -like raw material by an inkjet method is also conceivable. When the ink jet method is used, a uniform ferroelectric film 17 can be formed by controlling injection of a required amount into the opening 15. When the ink jet method is used, the ferroelectric film 17 needs to undergo a preliminary baking and a heat treatment for crystallization. If an Al alloy is used for the first electrode wiring 12, a low temperature heat treatment such as a ferroelectric film material capable of realizing calcination and crystallization by heat treatment at a temperature lower than 400 ° C., or low pressure annealing is required. Next, a second electrode film 18 is formed on the ferroelectric film 17. The second electrode film 18 is a noble metal film containing, for example, Pt, and is formed by a sputtering method.
[0021]
Next, a buried conductive member 19 using W is formed in the second electrode film 18 in the opening 15 and flattened. That is, after coating a barrier film (not shown), W that sufficiently fills the opening 15 is deposited by a CVD method or the like. Thereafter, flattening is performed while removing unnecessary W, Pt, and the like on the interlayer insulating film 14 using a CMP (chemical mechanical polishing) technique.
Next, the second electrode wiring 20 connected to the embedded conductive member 19 is formed by patterning. The second electrode wiring 20 is made of, for example, an Al alloy. Thereby, the configuration of FIG. 1 is realized. That is, the second electrode wiring 20 extends in the Y direction so as to intersect with the extending direction X of the first electrode wiring 12. Although not shown, a plurality of memory cell capacitors MC1 composed of the first and second electrode films 16, 18 and the ferroelectric film 17 therebetween are provided in each intersection region between the first electrode wiring 12 and the second electrode wiring 20. , A matrix memory unit.
[0022]
According to such a manufacturing method, the memory cell capacitor MC1 is formed according to the shape of the opening 15 provided in the intersection region between the first electrode wiring 12 and the second electrode wiring 20. That is, since plasma etching is not used for processing the first and second electrode films 16 and 18 and the ferroelectric film 17 therebetween, damage due to plasma or stress is unlikely to occur. Therefore, the heat treatment for recovery oxidation of the ferroelectric film 17 can be achieved at a temperature lower than 400 ° C. in a short time. Accordingly, it is expected that a low melting point material such as Al can be used particularly for the first electrode wiring 12, which facilitates fine processing. It should be noted that the base material of each of the main metal materials shown here may need to be coated with an adhesion material or a barrier film, but is omitted.
[0023]
FIG. 4 is a sectional view of a configuration showing a modification of the first embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals. The configuration of the second electrode wiring is different from that of FIG. As the second electrode wiring 25, a dual damascene structure using W is adopted. In the manufacturing method, for example, at the stage of the configuration in FIG. 2, the wiring groove 24 is formed in advance, and the opening 15 is formed. Thereafter, after coating a barrier film (not shown), W filling the openings 15 and the wiring grooves 24 is formed by a CVD method. Next, the structure as shown in FIG. 4 is obtained by flattening while removing unnecessary W, Pt and the like on the interlayer insulating film 14 using the CMP technique.
[0024]
FIG. 5 is a cross-sectional view showing a main configuration of a semiconductor memory device according to a second embodiment of the present invention, showing one memory cell unit in a cross-point type FeRAM. The same parts as those in FIG. 1 are denoted by the same reference numerals. The difference is that the arrangement of the first electrode film is before the formation of the opening 15 as compared with the configuration of FIG. Other configurations are the same as those of the first embodiment. That is, the first electrode wiring 12 is provided on the insulating film 11 so as to extend in the predetermined direction X, and the first electrode film 16f is formed on the predetermined region. The first electrode wiring 12 is made of a general wiring material used for a Si semiconductor. For example, a low melting point material such as an Al alloy may be used. Further, a high melting point material such as W (tungsten) is also conceivable. Further, the first electrode wiring 12 may have a buried wiring structure using damascene technology. The first electrode film 16f is a noble metal film containing Pt. The first electrode film 16f may be formed over the entire first electrode wiring 12 as another arrangement (not shown). A protective film 13 is formed on a part of the first electrode wiring 12 and the first electrode film 16f. The protective film 13 is made of at least a film having a high hydrogen barrier property, for example, a SiN film or a TaN film. On the protective film 13, an interlayer insulating film 14 is formed. The second electrode wiring 20 is provided on the interlayer insulating film 14 so as to overlap at least with the first electrode film 16f and extend in a predetermined direction Y intersecting with the extending direction of the first electrode wiring 12. The second electrode wiring 20 is made of a general wiring material used for a Si semiconductor. For example, a low melting point material such as an Al alloy may be used. Further, a high melting point material such as W is also conceivable.
[0025]
An opening 15 is provided in an intersection area between the first electrode wiring 12 and the second electrode wiring 20. In the opening 15, at least a ferroelectric film 17 on the first electrode film 16f and a second electrode film 18 on the ferroelectric film 17 are provided. The second electrode film 18 is a noble metal film containing Pt and is electrically connected to the second electrode wiring 20 via the embedded conductive member 19. Side surfaces of the ferroelectric film 17 are covered with a protective film 13 as a hydrogen barrier. The ferroelectric film 17 is selected from, for example, a PZT (Pb (Zr, Ti) O ₃ ) -based compound, a Bi-based compound having a layered structure (SBT (SrBi ₂ Ta ₂ O ₉ )), and the like. . The first and second electrode films 16f, 18 and the ferroelectric film 17 therebetween constitute a memory cell capacitor MC2. Although not shown, a plurality of memory cell capacitors MC2 are provided in each intersection region of the first electrode wiring 12 and the second electrode wiring 20, and constitute a matrix-shaped memory portion.
[0026]
According to the configuration of the second embodiment, the shape of the memory cell capacitor MC2 is determined such that the memory cell capacitor MC2 is embedded in the opening 15 provided in the intersection area between the first electrode wiring 12 and the second electrode wiring 20. It is configured. The ferroelectric film 17 is not exposed to the etching environment, is hardly damaged, and suppresses deterioration of characteristics of the memory cell. Hereinafter, an example of the manufacturing method will be described.
[0027]
6 and 7 are cross-sectional views showing the main parts of a manufacturing process for realizing the configuration of FIG. The same parts as those in FIG. 5 are denoted by the same reference numerals.
As shown in FIG. 6, a planarized base insulating film 11 provided on a predetermined layer on a semiconductor substrate is formed. The insulating film 11 may be an element isolation insulating film or an insulating film having a barrier function such as a SiN film. Next, the first electrode wiring 12 is formed on the insulating film 11 by patterning. The first electrode wiring 12 is a general wiring material used for a Si semiconductor centering on an Al alloy. If the crystallization temperature of the ferroelectric film 17 described later cannot be lowered, it is conceivable to use a high melting point material such as W for the first electrode wiring 12. A first electrode film 16f is formed in a predetermined region on the first electrode wiring 12.
For forming the first electrode film 16f, for example, a mask is formed through a photolithography process, and the exposed surface of the first electrode wiring 12 is coated with a noble metal film containing Pt by sputtering. After that, the mask is removed. Next, a protective film 13 rich in hydrogen barrier properties is formed. The protective film 13 has a sufficient thickness to cover a side surface of a ferroelectric film 17 described later. Next, an interlayer insulating film 14 such as a SiO ₂ film or a BPSG film is formed on the protective film 13. An opening 15 is formed in a predetermined region on the interlayer insulating film 14 to reach a surface region of the first electrode film 16f by using an anisotropic etching technique. A hard mask may be formed in a photolithography step before anisotropic etching.
[0028]
Next, as shown in FIG. 7, a ferroelectric film 17 is formed on the first electrode film 16f in the opening 15. The ferroelectric film 17 is selected from, for example, a PZT-based compound or an SBT-based compound. The ferroelectric film 17 uses a sputtering method. In addition, a method of applying a liquid (sol) -like raw material by an inkjet method is also conceivable. When the ink jet method is used, a uniform ferroelectric film 17 can be formed by controlling injection of a required amount into the opening 15. When the ink jet method is used, the ferroelectric film 17 needs to undergo a preliminary baking and a heat treatment for crystallization. If an Al alloy is used for the first electrode wiring 12, a low temperature heat treatment such as a ferroelectric film material capable of realizing calcination and crystallization by heat treatment at a temperature lower than 400 ° C., or low pressure annealing is required. Next, a second electrode film 18 is formed on the ferroelectric film 17. The second electrode film 18 is a noble metal film containing, for example, Pt, and is formed by a sputtering method.
[0029]
Next, a buried conductive member 19 using W is formed in the second electrode film 18 in the opening 15 and flattened. That is, after coating a barrier film (not shown), W that sufficiently fills the opening 15 is deposited by a CVD method or the like. After that, flattening is performed while removing unnecessary W, Pt, and the like on the interlayer insulating film 14 using the CMP technique.
Next, the second electrode wiring 20 connected to the embedded conductive member 19 is formed by patterning. The second electrode wiring 20 is made of, for example, an Al alloy. Thereby, the configuration of FIG. 1 is realized. The second electrode wiring 20 extends in the Y direction so as to intersect with the extending direction X of the first electrode wiring 12. Although not shown, a plurality of memory cell capacitors MC2 constituted by the first and second electrode films 16f and 18 and the ferroelectric film 17 therebetween are provided in each intersection region between the first electrode wiring 12 and the second electrode wiring 20. , A matrix memory unit.
[0030]
According to such a manufacturing method, the memory cell capacitor MC2 is formed according to the shape of the opening 15 provided in the intersection region between the first electrode wiring 12 and the second electrode wiring 20. That is, since plasma etching is not used for processing the first and second electrode films 16f and 18 and the ferroelectric film 17 therebetween, damage due to plasma or stress is less likely to occur. Therefore, the heat treatment for recovery oxidation of the ferroelectric film 17 can be achieved at a temperature lower than 400 ° C. in a short time. Accordingly, it is expected that a low melting point material such as Al can be used particularly for the first electrode wiring 12, which facilitates fine processing. It should be noted that the base material of each of the main metal materials shown here may need to be coated with an adhesion material or a barrier film, but is omitted.
[0031]
FIG. 8 is a cross-sectional view of a configuration showing a modification of the second embodiment. The same parts as those in FIG. 5 are denoted by the same reference numerals. The configuration of the second electrode wiring is different from that of FIG. As the second electrode wiring 28, a dual damascene structure using W is adopted. In the manufacturing method, for example, at the stage of the configuration in FIG. 6, the wiring groove 27 is formed in advance, and the opening 15 is formed. Thereafter, after coating a barrier film (not shown), W filling the opening 15 and the wiring groove 27 is formed by a CVD method. Next, the structure as shown in FIG. 8 is obtained by flattening while removing unnecessary W and Pt on the interlayer insulating film 14 using the CMP technique.
[0032]
As described above, according to the present invention, the configuration of the memory cell capacitor has a buried form that does not use an etching process, and can realize a configuration that is hardly subjected to stress and damage and has excellent workability. It is expected that a material having a low melting point such as an Al alloy or a material that is easy to perform precision processing can be used for the electrode wiring, and contributes to a reduction in the cell arrangement pitch of the memory unit. As a result, a highly reliable semiconductor memory device having a ferroelectric capacitor that is unlikely to be damaged in a cross-point type FeRAM, a low-melting-point material and a wiring material that can be easily processed with precision can be used, And a method for producing the same.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a main part configuration of a semiconductor device according to a first embodiment of the present invention, showing a part of a memory portion in a cross-point type FeRAM.
FIG. 2 is a first sectional view showing an intermediate step for realizing the configuration of FIG. 1;
FIG. 3 is a second sectional view following FIG. 2;
FIG. 4 is a sectional view of a configuration showing a modified example of the first embodiment.
FIG. 5 is a cross-sectional view showing a main part of a semiconductor device according to a second embodiment of the present invention, showing a part of a memory part in a cross-point type FeRAM;
FIG. 6 is a first sectional view showing an intermediate step for realizing the configuration of FIG. 5;
FIG. 7 is a second sectional view following FIG. 6;
FIG. 8 is a sectional view of a configuration showing a modification of the second embodiment.
FIG. 9 is a cross-sectional view showing a part of a memory cell part in a conventional cross-point type FeRAM.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Insulating film, 12 ... First electrode wiring, 13 ... Protective film, 14, 104 ... Interlayer insulating film, 15, 105 ... Opening, 16, 16f ... First electrode film, 17, 102 ... Ferroelectric film , 18: second electrode film, 19: embedded conductive member, 20, 25, 28: second electrode wiring, 24, 27: wiring groove, 101: lower electrode, 103: upper electrode, 106: upper wiring.

Claims

A first electrode wiring formed on a predetermined layer on the semiconductor substrate;
An insulating protective film covering the first electrode wiring;
An interlayer insulating film on the protective film,
A second electrode wiring provided on the interlayer insulating film so as to intersect with the first electrode wiring;
A first electrode film electrically connected to at least the first electrode wiring in an opening provided in an intersection region of the first electrode wiring and the second electrode wiring, and electrically connected to the second electrode wiring; A second electrode film, and a memory cell capacitor including a ferroelectric film between the first and second electrode films;
A semiconductor memory device comprising:

A first electrode wiring formed on a predetermined layer on the semiconductor substrate;
A first electrode film formed on a predetermined region of the first electrode wiring,
An insulating protective film covering the first electrode wiring and the first electrode film;
An interlayer insulating film on the protective film,
A second electrode wiring provided on the interlayer insulating film so as to overlap at least the first electrode film and intersect with the first electrode wiring;
At least a ferroelectric film on the first electrode film and a second electrode film on the ferroelectric film are included in an opening provided in an intersection region of the first electrode wiring and the second electrode wiring. A configured memory cell capacitor;
A semiconductor memory device comprising:

3. The semiconductor memory device according to claim 1, wherein said protective film covers at least a side surface of said ferroelectric film.

The semiconductor memory device according to claim 1, wherein the second electrode wiring is connected to the second electrode film via a metal embedded in the opening.

4. The semiconductor memory device according to claim 1, wherein the second electrode wiring is connected to the second electrode film including a form embedded in the opening. 5.

6. The semiconductor memory device according to claim 1, wherein said first electrode wiring is made of a metal material containing aluminum as a main component.

7. The semiconductor memory device according to claim 1, wherein said second electrode wiring is made of a metal material containing aluminum as a main component.

Forming a first electrode wiring on a predetermined layer on the semiconductor substrate;
Covering the first electrode wiring with an insulating protective film;
Forming an interlayer insulating film on the protective film;
Forming an opening reaching the surface of the first electrode wiring in a predetermined region on the interlayer insulating film;
Forming a first electrode film connected to the first electrode wiring in the opening;
Forming a ferroelectric film on the first electrode film in the opening;
Forming a second electrode film on the ferroelectric film in the opening;
Forming a second electrode wiring electrically connected to the second electrode film in the opening and crossing the first electrode wiring on the interlayer insulating film;
A method for manufacturing a semiconductor memory device, comprising:

Forming a first electrode wiring on a predetermined layer on the semiconductor substrate;
Forming a first electrode film on a predetermined region of the first electrode wiring;
Covering the first electrode wiring and the first electrode film with an insulating protective film;
Forming an interlayer insulating film on the protective film;
Forming an opening reaching the surface of the first electrode film in a predetermined region on the interlayer insulating film;
Forming a ferroelectric film on the first electrode film in the opening;
Forming a second electrode film on the ferroelectric film in the opening;
Forming a second electrode wiring electrically connected to the second electrode film in the opening and crossing the first electrode wiring on the interlayer insulating film;
A method for manufacturing a semiconductor memory device, comprising:

10. The method of manufacturing a semiconductor memory device according to claim 8, wherein said protective film is formed so as to have a thickness covering at least a side surface of said ferroelectric film.

11. The method according to claim 8, wherein the second electrode wiring is premised on a step of burying a metal in the opening.

11. The method according to claim 8, wherein the ferroelectric film includes a step of injecting a required amount into the opening using an inkjet method. .