JP2004317455A - Inspection auxiliary device and inspection method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an influence of dullness and strain of a signal in an input for an inspection device to conduct a quick function test, when executing an inspection for a semiconductor device, using the inspection device. <P>SOLUTION: This inspection auxiliary device consists of a frequency dividing circuit 20 for frequency-dividing a clock signal supplied from the inspection device or the semiconductor device to generate a frequency-divided clock signal, a comparison circuit 50 for comparing a series of values in an output signal output from at least one terminal of the semiconductor device synchronized with the lock signal respectively with a series of expected values supplied from the inspection device, and comparison result signal generating circuits 51-56 for generating a comparison result signal expressing collectively a plurality of comparison results in the comparison circuit, synchronized with the frequency-divided clock signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inspection auxiliary device used together with an LSI tester when inspecting a semiconductor device, and further relates to an inspection method for inspecting a semiconductor device using such an inspection auxiliary device together with an LSI tester.
[0002]
[Prior art]
In the manufacture of a semiconductor device, a wafer on which a large number of circuits are formed is cut into individual chips, and the chip is manufactured by performing a packaging process. Generally, a wafer test (wafer sort) for determining whether each chip is a non-defective product is performed at a wafer stage, and a package test (final test) is performed on the semiconductor device after the packaging process is performed. Done.
[0003]
Conventionally, in a wafer test or a package test, an LSI tester has been directly connected to a semiconductor device to be inspected. However, the input circuit of the LSI tester has a large input capacitance, and the cable used to connect the semiconductor device and the LSI tester also has a large stray capacitance. As a result, the signal input from the semiconductor device to be tested to the LSI tester becomes dull or distorted, making it difficult to perform a high-speed function test.
[0004]
By the way, Patent Document 1 discloses an auxiliary device for a semiconductor test apparatus that can obtain a highly accurate measurement result even in a low-precision and inexpensive semiconductor test apparatus. The auxiliary device latches a test signal of the semiconductor test device, and outputs the test signal to the semiconductor device and outputs a reference signal with a first timing signal delayed by a predetermined time from the test signal as a trigger. First latch means, programmable delay means for delaying a reference signal output from the first latch means by a pre-programmed time to generate a second timing signal, and latching an output result of the semiconductor device And a second latch means for outputting an output result of the semiconductor device to the semiconductor test apparatus by using a second timing signal generated by the programmable delay means as a trigger.
[0005]
By using the auxiliary device disclosed in Patent Document 1, the measurement start time is made to coincide with the operation start time of the semiconductor device irrespective of the skew time between pins of the semiconductor test device, and regardless of the judgment time accuracy of the semiconductor test device. The operation time of the semiconductor device can be measured. However, even if this auxiliary device is used, it is still difficult to perform a high-speed function test because the frequency of the input signal of the semiconductor test device does not become lower than the frequency of the output signal of the semiconductor device.
[0006]
Patent Document 2 discloses that a test signal is supplied to a semiconductor component under test for each reference frequency, and the resulting output signal of the semiconductor component under test is compared with an expected value to test the quality of the semiconductor component. An emulator for use in a semiconductor test apparatus is disclosed. This emulator enables a semiconductor test device to perform a test program creation and an operation check thereof when testing a semiconductor component in a semiconductor test device without occupying the semiconductor test device as actual hardware. It is not intended to perform a high-speed function test on actual semiconductor components.
[0007]
[Patent Document 1]
JP-A-1-287485 (Page 1, FIG. 1)
[Patent Document 2]
JP-A-10-320229 (page 1, FIG. 1)
[0008]
[Problems to be solved by the invention]
Therefore, in view of the above, the present invention can perform a high-speed function test by reducing the effects of signal dullness and distortion at the input of the inspection device when inspecting the semiconductor device using the inspection device. It is an object of the present invention to provide an inspection auxiliary device that can be used and an inspection method for inspecting a semiconductor device using such an inspection auxiliary device together with an LSI tester.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor device inspection assisting device according to the present invention includes a frequency dividing circuit that divides a clock signal supplied from an inspecting device or a semiconductor device to generate a frequency-divided clock signal; A comparison circuit that compares a series of values in an output signal output from at least one terminal of the semiconductor device with a series of expected values supplied from the inspection apparatus in synchronization with the divided clock signal; A comparison result signal generation circuit for generating a comparison result signal representing a plurality of comparison results in the comparison circuit.
[0010]
Here, the comparison result signal generation circuit has the first value when the series of values in the output signal output from at least one terminal of the semiconductor device are respectively equal to the series of expected values supplied from the inspection device. The comparison result signal may be generated, and in other cases, the comparison result signal having the second value may be generated.
[0011]
In addition, a method for inspecting a semiconductor device according to the present invention is a method for inspecting a semiconductor device using an inspection device and an inspection auxiliary device, wherein the semiconductor device is synchronized with a clock signal supplied from the inspection device or the semiconductor device. (A) comparing a series of values in an output signal output from at least one of the terminals with a series of expected values supplied from the inspection device in the inspection auxiliary device; (B) generating a comparison result signal representing the plurality of comparison results in step (a) in synchronism with the frequency-divided clock signal generated by the frequency division; and comparing the comparison signal generated in step (b). (C) outputting a result signal from the inspection auxiliary device to the inspection device.
[0012]
According to the present invention, in the inspection auxiliary device, a comparison result signal representing a comparison result between a series of values in an output signal output from at least one terminal of the semiconductor device and a series of expected values supplied from the inspection device. Is generated, the effect of signal dullness and distortion at the input of the inspection apparatus can be reduced, and a high-speed function test can be performed.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components are denoted by the same reference numerals, and description thereof will be omitted.
FIG. 1 is a diagram illustrating a semiconductor device to be inspected and a measurement system including an inspection auxiliary device according to an embodiment of the present invention. As shown in FIG. 1, the LSI tester 3 includes a test signal generation circuit 31 for generating a test signal, a clock signal generation circuit 32 for generating a clock signal used as a strobe signal, and a reset signal generation circuit for generating a reset signal. 33.
[0014]
A test signal is supplied from an LSI tester 3 to a semiconductor device 1 such as an IC or an LSI to be inspected. Further, a clock signal and a reset signal are supplied from the LSI tester 3 to the inspection auxiliary device 2. When a function test is performed based on a clock signal generated in the semiconductor device 1, the clock signal generated in the semiconductor device 1 is supplied to the inspection auxiliary device 2 and the LSI tester 3.
[0015]
Further, the LSI tester 3 includes an expected value signal generating circuit 34 that generates an expected value signal representing an expected value in an output signal output from at least one terminal of the semiconductor device 1 and an inspection assisting device 2 that assists a function test. And an inspection circuit 35 for inspecting the output comparison result signal.
[0016]
An output signal output from at least one terminal of the semiconductor device 1 is supplied to the inspection auxiliary device 2. On the other hand, an expected value signal output from the LSI tester 3 corresponding to this is also supplied to the inspection auxiliary device 2. The inspection auxiliary device 2 converts a series of values (in this embodiment, 4-bit serial data) contained in the output signal of the semiconductor device 1 into a series of expected values (this In this embodiment, the comparison result is 4-bit serial data), and a comparison result signal having a value collectively indicating the comparison result is generated.
[0017]
The LSI tester 3 performs a function test of the semiconductor device 1 based on the comparison result signal output from the inspection auxiliary device 2. Note that a changeover switch 4 is provided between the inspection auxiliary device 2 and the LSI tester 3, and when a characteristic test other than a function test (functional test) is performed, the output signal of the semiconductor device 1 is output to the LSI tester. It is directly input to the tester 3.
[0018]
FIG. 2 is a diagram illustrating a configuration example of the inspection auxiliary device according to the embodiment of the present invention. The inspection auxiliary device is configured by an IC or a discrete circuit. As shown in FIG. 2, the inspection assisting device 2 outputs the clock signal from the LSI tester 3 or the clock signal dividing circuit 20 for dividing the frequency of the clock signal CK supplied from the semiconductor device 1 and a plurality of terminals of the semiconductor device 1. The plurality of output signals SIG (1), SIG (2),... Are compared with a plurality of expected value signals EXP (1), EXP (2),. , Which output a plurality of comparison result signals COMP (1), COMP (2),..., Respectively, and near input terminals and output terminals of the inspection auxiliary device 2. , And a plurality of buffer circuits B1, B2,...
[0019]
The clock signal dividing circuit 20 divides the frequency of the clock signal CK and generates four divided clock signals CK1 to CK4 having different phases in order to give timing for performing a comparison operation on 4-bit serial data. Each of the serial data comparison circuits 21, 22,... Synchronizes a plurality of values of serial data in an output signal of the semiconductor device 1 with a plurality of expected values in an expected value signal in synchronization with the divided clock signals CK1 to CK4. And sequentially compared.
[0020]
FIG. 3 is a diagram showing in detail one system of serial data comparison circuit in the inspection auxiliary device shown in FIG. The serial data comparison circuit 21 supplies an exclusive NOR (XNOR) circuit 50 for comparing the output signal SIG (1) of the semiconductor device with the expected value signal EXP (1), and an output signal of the XNOR circuit 50 to a data input terminal. Flip-flops 51-54.
[0021]
The XNOR circuit 50 outputs a high-level output signal when the output signal SIG (1) of the semiconductor device matches the expected value signal EXP (1), and otherwise outputs a low-level output signal. Output.
[0022]
The clock signal input terminals of the flip-flops 51 to 54 are supplied with four frequency-divided clock signals CK1 to CK4 having different phases generated in the clock signal frequency dividing circuit 20. At the rising edge of the divided clock signal, the output signal of XNOR circuit 50 is held.
[0023]
Further, the serial data comparison circuit 21 includes an AND circuit 55 for calculating the logical product of the output signals of the flip-flops 51 to 54 and a flip-flop 56 for latching the output signal of the AND circuit 55 at the rising edge of the divided clock signal CK1. Have.
[0024]
FIG. 4 is a timing chart for explaining the operation of the one-system serial data comparison circuit shown in FIG. When the reset signal becomes low level and the reset state is released, the output signal SIG (1) including the serial data S11, S12,... Is supplied from the semiconductor device to be inspected, and the LSI tester An expected value signal EXP (1) including serial data E11, E12,... Is supplied.
[0025]
Flip-flop 51 holds the output signal of XNOR circuit 50 at the rising edge of frequency-divided clock signal CK1, and flip-flop 52 holds the output signal of XNOR circuit 50 at the rising edge of frequency-divided clock signal CK2. 53 holds the output signal of XNOR circuit 50 at the rising edge of divided clock signal CK3, and flip-flop 54 holds the output signal of XNOR circuit 50 at the rising edge of divided clock signal CK4.
[0026]
The AND circuit 55 calculates the logical product of the output signals of the flip-flops 51 to 54. The flip-flop 56 generates the comparison result signal COMP (1) by holding the output signal of the AND circuit 55 at the next rising edge of the divided clock signal CK1, and supplies the signal to the LSI tester.
[0027]
In this manner, the serial data comparison circuit 21 can combine the comparison results of the 4-bit serial data output from the semiconductor device to be inspected into 1-bit data. As a result, a comparison result signal having a quarter of the frequency of the output signal of the semiconductor device can be supplied to the LSI tester, thereby reducing the effects of signal dullness and distortion at the input of the LSI tester. Thus, a high-speed function test can be performed.
[0028]
In the present embodiment, the comparison results for the 4-bit serial data output from the semiconductor device to be inspected are collectively obtained. However, the comparison results for the 8-bit or other bit-number serial data are collected. You may ask for it. Further, a plurality of different bit numbers, for example, 4 bits and 8 bits may be switched, and the comparison result of the serial data of any bit number may be obtained collectively.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor device to be inspected and a measurement system including an inspection auxiliary device.
FIG. 2 is a diagram showing a configuration example of an inspection auxiliary device according to an embodiment of the present invention.
FIG. 3 is a diagram showing in detail a serial data comparison circuit of one system in FIG. 2;
FIG. 4 is a diagram for explaining the operation of the serial data comparison circuit shown in FIG. 3;
[Explanation of symbols]
Reference Signs List 1 semiconductor device to be inspected, 2 inspection auxiliary device, 3 LSI tester, 4 changeover switch, 20 clock signal divider circuit, 21, 22,... Serial data comparison circuit, B1, B2,. Test signal generation circuit, 32 clock signal generation circuit, 33 reset signal generation circuit, 34 expected value signal generation circuit, 35 inspection circuit, 50 XNOR circuit, 51 to 54 flip-flop, 55 AND circuit, 56 flip-flop

Claims (3)

An inspection auxiliary device for a semiconductor device,
A frequency divider that divides a clock signal supplied from an inspection device or a semiconductor device to generate a divided clock signal;
A comparison circuit that compares a series of values in an output signal output from at least one terminal of the semiconductor device in synchronization with the clock signal with a series of expected values supplied from the inspection device;
A comparison result signal generation circuit that generates a comparison result signal collectively representing a plurality of comparison results in the comparison circuit in synchronization with the frequency-divided clock signal;
An inspection auxiliary device comprising: The comparison result signal generation circuit has a first value when a series of values in an output signal output from at least one terminal of the semiconductor device are each equal to a series of expected values supplied from the inspection device. The inspection assistant device according to claim 1, wherein the comparison result signal is generated, and otherwise, the comparison result signal having the second value is generated. A method for inspecting a semiconductor device using an inspection device and an inspection auxiliary device,
A series of values in an output signal output from at least one terminal of the semiconductor device in synchronism with a clock signal supplied from the inspection device or the semiconductor device are used by an inspection auxiliary device to generate a series of expected values supplied from the inspection device. (A) comparing each with a value;
A step (b) of synchronizing with the frequency-divided clock signal generated by dividing the clock signal to generate a comparison result signal collectively representing a plurality of comparison results in step (a); ,
(C) outputting the comparison result signal generated in step (b) from the inspection auxiliary device to the inspection device;
An inspection method comprising:

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