JP2004312719A - Delay correction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems: delay time changes between immediately after inputting a signal and after repeatedly inputting the signal for certain times in a conventional delay circuit; duty in multiplication output changes in a two-multiplication circuit using the conventional delay circuit; and malfunction, or the like, occurs in an internal circuit using the multiplication output as input in a low power consumption circuit for frequently turning on/off the multiplication circuit. <P>SOLUTION: A delay correction circuit comprises first and second switching means; a delay circuit; and a control circuit composed of a pulse generation circuit and a switch change-over circuit. In the delay correction circuit, the output of the delay circuit is inputted to the pulse generation circuit, and the output of the pulse generation circuit is connected to the switch change-over circuit. By the switch change-over circuit, the opening and closing of the first and second switch means are controlled. This configuration allows delay time to be fixed. THe delay correction circuit is used for the two-multiplication circuit, thus obtaining the two-multiplication circuit that synchronizes with a source oscillation signal and has a duty that does not change. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a configuration of a delay circuit, and more particularly, to a configuration of a delay circuit for making a delay time constant and an electronic circuit using the delay circuit.

Delay circuits are widely used in general electronic circuits. A doubler circuit is an example of a circuit using a delay circuit. The doubling circuit is a circuit that can input a source vibration signal and output the signal at a double speed (double frequency), and is used for a one-chip microcomputer, a clock circuit for a CPU, and the like. .
By the way, to double the source vibration signal, there is a method of doubling the system clock signal itself used by all operating circuits. However, this method has a problem that not only a specific circuit cannot be operated at higher speed, but also that power consumption increases due to doubling of a system clock signal. Therefore, it is widely used to double a clock signal supplied to a specific circuit by using a doubler instead of doubling the system clock signal itself (for example, see Patent Document 1). .

  In an electronic circuit (for example, a small portable device or a watch) that strongly requires low power consumption, the power source signal may be frequently turned ON / OFF in order to stop wasteful power consumption. That is, the input and stop of the source vibration signal are frequently repeated according to the purpose.

In the ON / OFF of the frequent source oscillation signal as described above, in the doubler circuit using the conventional technique shown in Patent Document 1, the delay time immediately after ON and the delay time after some operation are different. There was a problem that would.
This difference in the delay time causes a temporary change in the duty of the multiplied signal in the doubler circuit using the conventional technique disclosed in Patent Document 1, which may cause malfunction of the internal circuit using this signal, There were problems such as malfunctioning of the circuit.

  This will be described in detail with reference to the drawings. FIGS. 9A to 9C are diagrams showing a doubler circuit using the conventional technique shown in Patent Document 1. FIG. FIG. 9A is a circuit diagram showing a configuration of a doubler circuit. FIG. 9B is a circuit diagram showing a configuration of a general delay circuit used in the related art shown in Patent Document 1. FIG. 9C is a diagram schematically showing a potential change of the input / output terminal of the doubler circuit.

In FIG. 9A, 102 is a source signal circuit, 103 is an internal circuit, 900 is a doubler circuit, 901 is a delay circuit, 902 is a two-input exclusive OR (exclusive OR) circuit, 903 is an input terminal, and 904 is an input terminal. Output terminal.
The doubling circuit 900 includes a delay circuit 901 that receives a signal from the source signal circuit 102 and a two-input exclusive-OR circuit that receives a signal from the source signal circuit 102 and a signal delayed by the delay circuit 901. 902.
The doubling circuit 900 receives the signal before multiplication from the source signal circuit 102 as an input and outputs a multiplied signal to the internal circuit 103. The output of the two-input exclusive OR circuit 902 is used as the output of the doubling circuit 900. It is input to the internal circuit 103.

Next, the operation of the doubler 900 will be described. The two-input exclusive OR circuit 902 outputs a high VDD potential when the potentials of the input signals are different, and outputs a low VSS potential otherwise.
When the delay time of the delay circuit 901 is set to approximately １ ／ of the output cycle of the source signal circuit 102, the output of the two-input exclusive OR circuit 902 becomes a double signal with a duty of approximately 50%.

Next, the delay circuit 901 will be described with reference to FIG. 905, an inverter circuit; 906, a resistor; 907, a capacitor; 107, a low-potential power supply line for supplying a VSS potential; The delay circuit 901 is a generally well-known delay circuit, and includes an input terminal 903, an output terminal 904, an inverter circuit 905, a resistor 906, and a capacitor 907. Note that the resistor 906 and the capacitor 907 are delay elements using the current limiting characteristics of the resistor 906 and the charge / discharge characteristics of the capacitor 907.
The circuit operates at a potential between a power supply line (VDD power supply line) 106 for supplying a VDD potential (not shown) and a power supply line (VSS power supply line) 107 for supplying a low VSS potential.
The input terminal 903 is connected to the input of the inverter circuit 905, the output of the inverter circuit 905 is connected to one terminal of the resistor 906, and the other terminal of the resistor 906 is connected to one terminal of the capacitor 907 and the output terminal 904. Connected. The other terminal of the capacitor 907 is connected to the VSS power supply line 107. Note that the other terminal of the capacitor 907 does not necessarily have to be connected to the VSS power supply line 107, and may be connected to the VDD power supply line 106.

Next, the operation of the delay circuit 901 will be described with reference to FIG. FIG. 9C is a diagram schematically showing a potential change of the doubling circuit 900 shown in FIG. 9A.
In the figure, the first stage shows the potential of the input terminal 903, the second stage shows the potential of the output terminal 904, and the third stage shows the output potential of the doubler 900. The vertical axis in the figure represents the VDD potential and the VSS potential, and the height is different between the first stage, the third stage, and the second stage, but this is for making the waveform easy to see. is there.
When a signal starts to be input from the power source signal circuit 102 and the potential of the input terminal 903 changes from the VSS potential to the VDD potential, the potential of the output terminal 904 rises from the VSS potential in accordance with the time constant of the resistor 906 and the capacitor 907. I do. When the signal from the power source signal circuit 102 is inverted and the potential of the input terminal 903 changes from the VDD potential to the VSS potential, the potential of the output terminal 904 similarly becomes the VDD potential along the time constant of the resistor 906 and the capacitor 907. Descend from.
The potential of the output terminal 904 repeatedly rises and falls according to the inversion of the signal from the power source signal circuit 102. The two-input exclusive-OR circuit 902 outputs the VDD potential when the potential of the input signal is different, and outputs the VSS potential otherwise. Therefore, the output of the doubling circuit 900 outputs the signal of the input terminal 903 at twice the frequency. Signal.

JP-A-2002-064367 (page 2, FIG. 5)

However, the doubling circuit using the conventional technique disclosed in Patent Document 1 has a problem that a delay time immediately after the delay circuit is turned on and a delay time after the delay circuit is slightly operated are different.
explain in detail. Immediately after the signal from the power source signal circuit 102 is input, the potential of the output terminal 904 starts to rise from the VSS potential, but in the second cycle (T2), it is slightly closer to the VDD potential than the VSS potential. Has started to rise from a high potential.

  The same applies to the drop in the potential of the output terminal 904. The second cycle (T2), the third cycle (T3), and the fall start potential are changed from the 1/2 VDD potential compared to immediately after the signal input from the source signal circuit 102. It has risen to the VDD potential. Note that the Ｖ VDD potential indicates a half of the power supply potential.

The two-input exclusive OR circuit 902 which receives the output signal of the output terminal 904 as an input generally changes the logic of the output when the input signal crosses the 1/2 VDD potential. Output terminal 9
The cycle of the signal 04 gradually changes and falls within a constant value as shown by T1, T2, T3... Shown in FIG. As shown in FIG. 9C, the period variation is greatest immediately after the start of signal input from the source signal circuit 102.

  In order to make the duty of the multiplied output signal close to 50%, it is necessary to set the delay time to about 1/4 of the cycle of the source signal, and as described with reference to FIG. The delay time immediately after ON and the delay time after some operation are different from each other, and in the doubling circuit shown in FIG. 9A, the variation of the duty of the multiplied output signal is inevitable.

  As described with reference to FIGS. 9A to 9C, in the doubling circuit using the conventional technique disclosed in Patent Document 1, the duty of the multiplied output changes, and the doubling circuit is frequently turned ON / OFF. In a low power consumption circuit that is turned off, a problem such as a malfunction occurs in an internal circuit that receives a multiplied output.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide a delay correction circuit capable of stably operating a doubler circuit even in an electronic circuit requiring low power consumption.

  In order to achieve the above object, the present invention employs the following configuration.

  A delay circuit for delaying the source signal, first switch means provided between the output of the delay circuit and the high-potential power supply line, and second switch means provided between the output of the delay circuit and the low-potential power supply line And a control circuit for controlling the opening and closing of the first switch means and the second switch means.

  The control circuit includes a pulse generation circuit that generates a pulse when the source signal is switched, and a switch switching circuit that controls opening and closing of the first switch means and the second switch means.

  The pulse generation circuit includes a resistor, a capacitor, an inverter circuit, and a logic synthesis circuit.

  The switch switching circuit includes an inverter circuit, an OR circuit, and an AND circuit.

The first switch is a P-channel MOS transistor, the second switch is an N-channel MOS transistor,
The control circuit outputs a signal for alternately turning on the P-channel MOS transistor and the N-channel MOS transistor based on the output signal of the delay circuit, and connects the output terminal of the delay circuit to a high potential power line and a low potential power line. And are connected alternately.

The delay correction circuit according to the present invention is characterized in that the delay time immediately after the operation of the delay circuit is started and the delay time after the operation of the delay circuit are somewhat equal, and the delay time can be synchronized with the output signal from the source signal circuit. Have.
If the delay correction circuit of the present invention is applied to a doubling circuit, it is possible to prevent a change in the duty of the multiplied output and a malfunction of the internal circuit due to the problem, which has been a problem in the doubling circuit using the conventional delay circuit. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating a delay correction circuit 100 according to the present invention, FIG. 2 is a diagram illustrating a configuration of a control circuit 101, FIG. 3 is a diagram illustrating a configuration of a pulse generation circuit 200, and FIG. 3 is a diagram illustrating a configuration of a switch switching circuit 201. FIG. FIG. 5 is a timing chart illustrating the operation of the delay correction circuit 100. FIG. 6 is a diagram for explaining a doubling circuit using the delay correction circuit 100 of the present invention.

[Description of delay correction circuit: FIG. 1]
FIG. 1 shows a delay correction circuit 100 according to the present invention. 101 is a control circuit, 104 is a P-channel MOS transistor (PMOSFET) as a first switch, 105 is an N-channel MOS transistor (NMOSFET) as a second switch, and 106 supplies a high VDD potential. A power supply line (VDD power supply line) 107 is a power supply line (VSS power supply line) for supplying a low VSS potential. 300 and 400 are input terminals of the control circuit 101, and 402 and 403 are output terminals of the control circuit 101. Reference numeral 903 denotes an input terminal of the delay circuit 901, and 904 denotes an output terminal of the delay circuit 901. In addition, 102 is a source oscillation signal circuit, and 103 is an internal circuit.

The delay correction circuit 100 of the present invention includes a delay circuit 901, a PMOSFET 104 as a first switch, an NMOSFET 105 as a second switch, a control circuit 101 for opening and closing the PMOSFET 104 and the NMOSFET 105, and a VDD power supply line. 106 and a VSS power supply line 107.
The delay circuit 901 has an input terminal 903 and an output terminal 904, and the circuit configuration will be described later. The control circuit 101 has an input terminal 300, an input terminal 400, an output terminal 402, and an output terminal 403, and the circuit configuration will be described later.

The output of the source signal circuit 102 is connected to the input terminal 903 of the delay circuit 901 and to the input terminal 400 of the control circuit 101. The output terminal 904 of the delay circuit 901 is connected to the input of the internal circuit 103 and the control circuit. 101 is connected to the input terminal 300.
The PMOSFET 104 is connected between the output terminal 904 of the delay circuit 901 and the VDD power supply line 106. The PMOSFET 104 has a source connected to the VDD power supply line 106 and a drain connected to the output terminal 904 of the delay circuit 901.
The NMOSFET 105 is connected between the output terminal 904 of the delay circuit 901 and the VSS power supply line 107. The NMOSFET 105 has a source connected to the VSS power supply line 107 and a drain connected to the output terminal 904 of the delay circuit 901.
The output terminal 402 of the control circuit 101 is connected to the gate of the PMOSFET 104, and the output terminal 403 of the control circuit 101 is connected to the gate of the NMOSFET 105.
With such a configuration, the delay correction circuit 100 delays the signal input from the source signal circuit 102 and outputs the signal to the internal circuit 103.

[Explanation of the delay circuit 901: FIG. 9B]
As the delay circuit 901, a delay circuit that is generally widely used can be used. For example, as shown in FIG. 9B, a signal is delayed by an inverter circuit 905, a resistor 906, and a capacitor 907.
In the following description, the delay circuit 901 will be described with reference to the circuit shown in FIG.

[Description of Control Circuit 101: FIG. 2]
Next, the configuration of the control circuit 101 constituting the delay correction circuit 100 will be described with reference to FIG. The control circuit 101 includes a pulse generation circuit 200 that generates a pulse when the source signal is switched, and a switch switching circuit 201 that controls opening and closing of the PMOSFET 104 and the NMOSFET 105.
The pulse generation circuit 200 has an input terminal 300 and an output terminal 301. The switch switching circuit 201 has input terminals 400 and 401 and output terminals 402 and 403.
The output terminal 301 of the pulse generation circuit 200 is connected to the input terminal 401 of the switch switching circuit 201.

[Description of Pulse Generating Circuit 200: FIG. 3]
The configuration of the pulse generation circuit 200 forming the control circuit 101 will be described with reference to FIG. The pulse generation circuit 200 is a circuit for inputting a pulse-like output signal to the switch switching circuit 201 in accordance with the switching of the source vibration signal. For example, the pulse generation circuit 200 has the following configuration.

The pulse generation circuit 200 has an input terminal 300, an output terminal 301, a resistor 304, a capacitor 305, an inverter circuit 302, and a two-input exclusive NOR circuit 303 which is a logic synthesis circuit.
The input terminal 300 is connected to one terminal of the resistor 304 and the input of the inverter circuit 302. The other terminal of the resistor 304 is connected to one input of a two-input exclusive NOR circuit 303 and a capacitor 305 is connected to the VSS power supply line 107. The output of the inverter circuit 302 is connected to the other input of the two-input exclusive NOR circuit 303, and the output of the two-input exclusive NOR circuit 303 is connected to the output terminal 301.

In the pulse generation circuit 200, the signal input from the input terminal 300 is divided into two signals, each of which is input to the two-input exclusive NOR circuit 303. One signal input to the two-input exclusive NOR circuit 303 is a signal delayed by a time constant generated by the resistor 304 and the capacitor 305, and the other signal is obtained by inverting a signal input from the input terminal 300 by the inverter circuit 302. Signal.
Only when these two signals are at the VDD potential or the VSS potential at the same time, a signal of the VDD potential is output to the output terminal 301. Otherwise, a signal of the VSS potential is output.
That is, the pulse generation circuit 200 generates an output signal from the output terminal 301 in synchronization with the rise and fall of the input signal applied to the input terminal 300.
This output signal is a pulse-like output signal obtained by the input signal from the input terminal 300 and the time constant of the resistor 304 and the capacitor 305, and controls opening and closing of the PMOSFET 104 and the NMOSFET 105 by a switch switching circuit 201 described later. Signal for

[Description of Switch Switching Circuit 201: FIG. 4]
Next, the configuration of the switch switching circuit 201 included in the control circuit 101 will be described with reference to FIG. The switch switching circuit 201 is a circuit that outputs a signal for controlling the opening and closing of the PMOSFET 104 and the NMOSFET 105 from the output terminals 402 and 403, and has the following configuration as an example.

The switch switching circuit 201 has input terminals 400 and 401, output terminals 402 and 403, an inverter circuit 404, a two-input OR circuit 405, and a two-input AND circuit 406.
The input terminal 400 is connected to one input of a two-input OR circuit 405 and to one input of a two-input AND circuit 406. The input terminal 401 is connected to the input of the inverter circuit 404 and to the other input of the two-input AND circuit 406. The output of the inverter circuit 404 is connected to the other input of the two-input OR circuit 405. The output of the two-input OR circuit 405 is connected to the output terminal 402, and the output of the two-input AND circuit 406 is connected to the output terminal 403.

The signal input from the input terminal 400 is divided into two signals, which are the first input of the two-input OR circuit 405 and the first input of the two-input AND circuit 406. The signal input from the input terminal 401 is divided into two signals, which are the input of the inverter circuit 404 and the second input of the two-input AND circuit 406.
The output of the inverter circuit 404 is obtained by inverting the signal input from the input terminal 401 and is output as the second input of the two-input OR circuit 405.
The two-input OR circuit 405 outputs a signal of the VDD potential to the output terminal 402 only when one of the signal of the first input and the signal of the second input of the two-input OR circuit 405 is the VDD potential. . Otherwise, it outputs a signal of the VSS potential.
The two-input AND circuit 406 outputs the signal of the VDD potential to the output terminal 403 only when the signal of the first input and the signal of the second input of the two-input AND circuit 406 are simultaneously the VDD potential. Otherwise, it outputs a signal of the VSS potential.
That is, the switch switching circuit 201 generates a signal from the output terminal 402 in synchronization with the rise of the input signal applied to the input terminal 300 shown in FIG. 2, and synchronizes with the fall of the input signal applied to the input terminal 300. Output terminal 403 to generate an output signal. As shown in FIG. 1, the operation of the PMOSFET 104 is controlled by a signal from the output terminal 402, and the operation of the NMOSFET 105 is controlled by a signal from the output terminal 403.

[Operation description: FIGS. 1 to 5]
Next, the operation of the delay correction circuit 100 of the present invention will be described with reference to FIGS. FIG. 5 is a timing chart for explaining the operation of the delay circuit 101. The state of the potential of the input terminal 903 of the delay circuit 901 is shown at the first stage in the figure. The second row shows the state of the potential of the output terminal 402 of the control circuit 101, and the third row shows the state of the potential of the output terminal 403. The fourth stage shows the state of the potential of the output terminal 904 of the delay circuit 901 (that is, the potential of the input terminal 300 of the control circuit 101).
The vertical axis in the figure represents the VDD potential and the VSS potential, and their heights are different in the first to third and fourth stage timing charts. Things.

  When a signal from the source signal circuit 102 shown in FIG. 1 is applied to the input terminal 903, the potential of the input terminal 903 starts to change. When this potential changes from the VDD potential to the VSS potential, the potential of the output terminal 904 changes according to the delay time created by the resistor 906 and the capacitor 907 of the delay circuit 901, and exceeds 1/2 of the VDD potential and the VSS potential. At this point, the input of the next-stage control circuit 101 is changed.

The control circuit 101 outputs signals from the output terminal 402 and the output terminal 403 in synchronization with the output of the delay circuit 901 as described with reference to FIGS. 2, 3, and 4. That is, the potential of the output terminal 904 changes from the VSS potential to the VDD potential, and a signal is output from the output terminal 402 when the potential exceeds 1/2 of the VDD potential and the VSS potential.
As shown in FIG. 5, the potential of the output terminal 402 indicates a signal synchronized with the signal of the output terminal 904, which is the output of the delay circuit 901 obtained from the pulse generation circuit 200.
When the output terminal 402 outputs the VSS potential, the PMOSFET 104 is turned on to forcibly raise the potential of the output terminal 904 to the VDD potential.

When the potential of the input terminal 903 changes from the VSS potential to the VDD potential, and the potential of the output terminal 904 drops from the VDD potential and exceeds 1/2 of the VDD potential and the VSS potential, the input of the control circuit 101 in the next stage is input. Then, the pulse generation circuit 200 outputs a signal from the output terminal 403 in synchronization with a signal at the output terminal 904, which is the output of the delay circuit 901.
When the output terminal 403 outputs the VDD potential, the NMOSFET 105 is turned on to forcibly reduce the potential of the output terminal 904 to the VSS potential.

  That is, the potential of the output terminal 904 repeats the same operation every time the potential of the input terminal 903 changes between the VDD potential and the VSS potential. In any case, the potential rises or falls at the potential between the VSS potential and the VDD potential. In either case, the potential changes at the delay time formed by the resistor 906 and the capacitor 907 of the same delay circuit 901. Therefore, the potential of the output terminal 904 is always constant as in the period T1 shown in FIG. 903 is synchronized with the potential change.

  As described above, in the present invention, the delay time immediately after the delay circuit 901 is turned on is equal to the delay time after the delay circuit 901 is slightly operated, and the delay time can be synchronized with the input signal from the source signal circuit 102. Malfunction of the internal circuit can be prevented.

[Description of Doubler Circuit Utilizing the Present Invention: FIG. 6]
When a doubling circuit is created using the delay correction circuit 100 of the present invention, a change in the duty of the multiplied output and a malfunction of the internal circuit 103 due to the problem, which are problems in the doubling circuit using the conventional delay circuit, are caused. Does not occur. This will be described with reference to FIG.

  FIG. 6 is a doubler circuit using the delay correction circuit 100 of the present invention. This doubler circuit includes a delay correction circuit 100 and a two-input exclusive NOR circuit 601, and doubles the signal of the source signal circuit 102 and inputs the signal to the internal circuit 103.

  The source oscillation signal circuit 102 is connected to an input terminal 903 (not shown in FIG. 6) of the delay circuit 901 included in the delay correction circuit 100 and to one input of a two-input exclusive NOR circuit 601. An output terminal 904 (not shown in FIG. 6) of the delay circuit 901 constituting the delay correction circuit 100 is connected to the other input of the two-input exclusive NOR circuit 601. The output of the two-input exclusive NOR circuit 601 is connected to the internal circuit 103.

  As described above in the description of the operation of the delay correction circuit 100, the output of the delay correction circuit 100 is synchronized with the output of the source signal circuit 102, and after the delay correction circuit 100 operates even immediately after being turned on. However, since the delay time is the same, the output of the two-input exclusive NOR circuit 601 is synchronized with the signal from the source signal circuit 102 and the duty does not change. Therefore, the problem of the prior art can be solved by configuring the doubler circuit using the delay correction circuit 100 of the present invention.

[Description of Different Doubler Circuits: FIGS. 7 and 8]
Next, a doubling circuit different from FIG. 6 using the delay correction circuit 100 according to the present invention will be described with reference to FIGS. FIG. 7 is a diagram for explaining the doubler circuit, and FIG. 8 is a timing chart showing the operation of the doubler circuit shown in FIG.

In the doubling circuit shown in FIG. 7, the same components as those already described are denoted by the same reference numerals, and detailed description will be omitted.
As shown in FIG. 7, the doubling circuit includes a delay circuit 901, two switch means of a PMOSFET 104 as a first switch means and an NMOSFET 105 as a second switch means, a resistor 707, a capacitor 709, and an inverter 701. And a pulse generation circuit 220 including a two-input AND circuit 702 as a logic synthesis circuit, a switch switching circuit 201, and a two-input exclusive OR circuit 703.
The VDD power supply line 106 is a power supply line for supplying a high potential VDD potential, and the VSS power supply line 107 is a power supply line for supplying a low potential VSS potential. VDD power line 106 and V
The SS power supply line 107 supplies a potential to each circuit.

The output of the source signal circuit 102 is connected to the input terminal of the delay circuit 901 and the input terminal 400 of the switch switching circuit 201. An output terminal of the inverter circuit 905 constituting the delay circuit 901 is connected to one input terminal of the two-input exclusive OR circuit 703.
The PMOSFET 104 and the NMOSFET 105 are provided between the VDD power supply line 106 and the VSS power supply line 107 from the connection point between the output terminal of the delay circuit 901 and the other input terminal of the two-input exclusive OR circuit 703, respectively.
The NMOSFET 105 has a source connected to the VSS power supply line 107 and a drain connected to the output terminal of the delay circuit 901. The PMOSFET 104 has a source connected to the VDD power supply line 106 and a drain connected to the output terminal of the delay circuit 901.
The output of the two-input exclusive OR circuit 703 is connected to the input terminal of the pulse generation circuit 220 and to the internal circuit 103.
An output terminal of the pulse generation circuit 220 is connected to an input terminal 401 of the switch switching circuit 201.
The output terminal 402 of the switch switching circuit 201 is connected to the gate of the PMOSFET 104, and the output terminal 403 is connected to the gate of the NMOSFET 105.
The pulse generation circuit 220 has a resistor 707, a capacitor 709, an inverter 701, and a two-input AND circuit 702. The input terminal of the pulse generation circuit 220 is connected to the input terminal of the inverter circuit 701 and one terminal of the resistor 707. The output of the inverter circuit 701 is connected to one input terminal of a two-input AND circuit 702. The other terminal of the resistor 707 is connected to the other input terminal of the two-input AND circuit 702, and a capacitor 709 is provided between this connection point and the VSS power supply line 107.

Next, the operation of the doubling circuit of FIG. 7 will be described with reference to FIGS. FIG. 8 is a timing chart for explaining the operation of the doubling circuit of FIG.
The first stage in the figure shows the state of the potential of the output terminal of the source signal circuit 102, and the second stage shows the potential of the input of the internal circuit 103 obtained from the output of the two-input exclusive-OR circuit 703, that is, a doubling of this. The state of the output potential of the circuit is shown, the state of the potential of the output terminal of the two-input AND circuit 702 is shown in the third stage, and the state of the output terminal 402 output of the switch switching circuit 201 is shown in the fourth stage. The eye shows the state of the potential of the output terminal 403 of the switch switching circuit 201, and the sixth part shows the state of the other input terminal of the two-input exclusive OR circuit 703, that is, the state of the output potential of the delay circuit 901. In the figure, the vertical axis represents the VDD potential and the VSS potential. The heights of the first to fifth and sixth stages are different, but this is for making the waveforms easier to see.

  When a signal output from the source signal circuit 102 shown in FIG. 7 is applied to an input terminal of the inverter circuit 905 of the delay circuit 901, the potential of the output terminal of the inverter circuit 905 starts to change. When the potential of the input terminal of the inverter circuit 905 changes from the VDD potential to the VSS potential, the potential of the output terminal of the inverter circuit 905 becomes VDD potential which is an inverted signal of the potential of the input terminal of the inverter circuit 905, and the two inputs are output. A signal input to one input terminal of the exclusive OR circuit 703 and a signal delayed by a time constant generated by the resistor 906 and the capacitor 907 are input to the other input terminal of the two-input exclusive OR circuit 703.

As for the signal output from the output terminal of the two-input exclusive OR circuit 703, the signal inverted by the inverter circuit 701 of the pulse generation circuit 220 is input to one input terminal of the two-input AND circuit 702 and the resistor 707 is output. A signal delayed by a time constant generated by the capacitor 709 and the capacitor 709 is input to the other input terminal of the two-input AND circuit 702.
The output terminal of the two-input AND circuit 702 outputs a signal of the VDD potential only when two input signals are simultaneously at the VDD potential, and outputs a signal of the VSS potential otherwise.
That is, the output of the 2-input AND circuit 702 generates an output signal from the output terminal of the 2-input AND circuit 702 in synchronization with the fall of the output signal of the 2-input exclusive OR circuit 703. By selecting the period of the output signal and the values of the resistor 707 and the capacitor 709, a pulse-like output signal as shown in the third row of FIG. 8 is obtained.

  When the output signal of the two-input AND circuit 702 is input to the input terminal 401 of the switch switching circuit 201, as described above, the output signal of the output terminal 402 of the switch switching circuit 201 becomes as shown in the fourth stage in FIG. A signal is generated in synchronization with the rising edge of the input signal of the other input of the two-input exclusive OR circuit 703, and the output signal of the output terminal 403 of the switch switching circuit 201 has two inputs as shown in the fifth stage of FIG. A signal is generated in synchronization with the fall of the input signal of the other input of the exclusive OR circuit 703.

When a signal from the source signal circuit 102 shown in FIG. 7 is applied to the input terminal of the inverter circuit 905, the potential of the output terminal of the inverter circuit 905 starts to change. When the potential of the input terminal of the inverter circuit 905 changes from the VDD potential to the VSS potential, as the potential of the output terminal of the inverter circuit 905, a VDD potential which is an inverted signal of the potential of the input terminal of the inverter circuit 905 is output. A signal input to one input terminal of the exclusive OR circuit 703 and a signal delayed by a time constant generated by the resistor 906 and the capacitor 907 are input to the other input terminal of the two-input exclusive OR circuit 703. The time when the other input of the two-input exclusive OR circuit 703 changes from the VSS potential to the VDD potential according to the delay time created by the resistor 906 and the capacitor 907, and exceeds 1/2 of the VSS potential and the VDD potential. Then, the output of the two-input exclusive OR circuit 703 changes from the VDD potential to the VSS potential.
That is, the output signal of the output terminal 402 of the switch switching circuit 201 becomes VSS potential, the PMOSFET 104 is turned on, and the potential of the other input of the two-input exclusive OR circuit 703 is forcibly set to VDD as shown in the sixth stage of FIG. Raise to potential.

When the potential of the input terminal of the inverter circuit 905 changes from the VSS potential to the VDD potential, the potential of the output terminal of the inverter circuit 905 becomes the VSS potential which is an inverted signal of the potential of the input terminal of the inverter circuit 905. The signal is input to one input terminal of the input exclusive OR circuit 703, and the other input of the two input exclusive OR circuit 703 changes from the VDD potential to the VSS potential according to the delay time created by the resistor 906 and the capacitor 907. At this point, the output of the two-input exclusive-OR circuit 703 changes from the VDD potential to the VSS potential when the potential exceeds 1/2 of the VDD potential and the VSS potential.
That is, the output signal of the output terminal 403 of the switch switching circuit 201 becomes the VDD potential, the NMOSFET 105 is turned on, and the potential of the other input of the two-input exclusive OR circuit 703 is forcibly set as shown in the sixth stage of FIG. Pull down to VSS potential.

  The same operation is repeated every time the potential of the output of the power source signal circuit 102 changes between the VDD potential and the VSS potential. In any case, the potential of the other input of the two-input exclusive OR circuit 703 is changed to the VSS potential or the VDD potential. The potential of the other input of the two-input exclusive-OR circuit 703 always rises or falls at a potential between the potentials and changes in the delay time formed by the same resistor 906 and capacitor 907 in both cases. It is constant as in the period T1 shown in the lower row, and is synchronized with the potential change of the output of the source signal circuit 102.

As described above, even in the doubling circuit different from FIG. 6 using the delay correction circuit 100 of the present invention, the signal of the other input of the two-input exclusive OR circuit 703 immediately after the doubling circuit of FIG. And the delay time after some operation is equal, and can be synchronized with the output signal from the source signal circuit 102, and the input of the internal circuit 103 obtained from the output of the two-input exclusive OR circuit 703 The signal is synchronized with the signal from the source signal circuit 102 and the duty does not change as shown in the second stage of FIG.

  A delay correction circuit of the present invention corrects a signal delayed by a delay circuit by using a first switch unit, a second switch unit, and a control circuit including a pulse generation circuit and a switch switching circuit, and delays the signal. Time can always be constant. Therefore, when this delay correction circuit is used for a doubler circuit, it is possible to obtain a doubler circuit which is synchronized with the source signal and whose duty does not change. Therefore, the present invention can be applied to a circuit for a small portable device or a timepiece that strongly requires low power consumption by frequently turning on / off a source vibration signal.

FIG. 3 is a diagram illustrating a configuration of a delay correction circuit according to the present invention. FIG. 3 is a diagram illustrating a configuration of a control circuit 101 of the delay correction circuit according to the present invention. FIG. 3 is a diagram illustrating a configuration of a pulse generation circuit 200 of the delay correction circuit of the present invention. FIG. 3 is a diagram illustrating a configuration of a switch switching circuit 201 of the delay correction circuit according to the present invention. 5 is a timing chart illustrating an operation of the delay correction circuit according to the present invention. FIG. 2 is a diagram illustrating a configuration of a doubler circuit according to a first embodiment using the delay correction circuit of the present invention. FIG. 9 is a diagram illustrating a configuration of a doubler circuit according to a second embodiment using the delay correction circuit of the present invention. 9 is a timing chart illustrating the operation of the doubler circuit according to the second embodiment using the delay correction circuit of the present invention. FIG. 6 is a diagram illustrating a conventional technique.

Explanation of reference numerals

REFERENCE SIGNS LIST 100 delay correction circuit 101 control circuit 102 power source signal circuit 103 internal circuit 104 first switch means 105 second switch means 106 high-potential power supply line 107 low-potential power supply line 200 pulse generation circuit 201 switch switching circuit 220 pulse generation circuit 300 Input terminal 301 Output terminal 302 Inverter circuit 303 Two-input exclusive NOR circuit 304 Resistance 305 Capacitance 400 Input terminal 401 Input terminal 402 Output terminal 403 Output terminal 404 Inverter circuit 405 Two-input OR circuit 406 Two-input AND circuit 601 Two-input exclusive NOR circuit 701 Inverter circuit 702 Two-input AND circuit 703 Two-input exclusive OR circuit 707 Resistance 709 Capacity 901 Delay circuit 902 Two-input exclusive OR circuit 90 3 input terminal 904 output terminal 905 inverter circuit 906 resistance 907 capacitance

Claims (5)

  A delay circuit for delaying the source oscillation signal, first switch means provided between the output of the delay circuit and the high-potential power supply line, and second switch provided between the output of the delay circuit and the low-potential power supply line A delay correction circuit comprising: switch means; and a control circuit that controls opening and closing of the first switch means and the second switch means.   The control circuit includes a pulse generation circuit that generates a pulse when the source signal is switched, and a switch switching circuit that controls opening and closing of the first switch unit and the second switch unit. The delay correction circuit according to claim 1.   3. The delay correction circuit according to claim 1, wherein the pulse generation circuit includes a resistor, a capacitor, an inverter circuit, and a logic synthesis circuit.   The delay correction circuit according to claim 1, wherein the switch switching circuit includes an inverter circuit, an OR circuit, and an AND circuit. The first switch means is a P-channel MOS transistor, the second switch means is an N-channel MOS transistor,
The control circuit outputs a signal for alternately turning on the P-channel MOS transistor and the N-channel MOS transistor based on an output signal of the delay circuit, and connects an output terminal of the delay circuit to a high potential power supply line. 2. The delay correction circuit according to claim 1, wherein the delay correction circuit and the low potential power supply line are connected alternately.

Images