JP2004312372A - Ofdm receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the FFET window timing offset between a known pattern and a data symbol, which is caused by the deviation between synchronizing timings of the head and the trail of a packet signal. <P>SOLUTION: A signal S3 has an offset removed in a frequency offset compensation part 105 on the basis of a carrier frequency offset calculated by a frequency offset detection part 104, and a signal S4 is outputted. FFT processing is performed for the signal S4 in an FFT part 107 on the basis of an FFET window timing detected by an FFT window timing detection part 106, and a frequency base signal S5 is outputted by conversion from a time base signal to the frequency bade signal. A clock offset is calculated in a clock offset detection part 110 on the basis of the carrier frequency offset calculated by the frequency offset detection part 104, and a phase difference between a data symbol and a symbol in the leading part of the packet signal is calculated in a phase difference detection part 11 on the basis of the clock offset and the time interval between the symbol in the leading part of the packet signal and the data symbol, which is outputted from a system control part 109. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【００２４】
ここで、ｆ_{ｃａｒｒｉｅｒｏｆｆｓｅｔ}は、送受信装置間におけるキャリア周波数オフセット、ｆ_ＴｘＬＯは送信装置のローカルの発振器の周波数、ｆ_ＲｘＬＯは、受信装置のローカルの発振器の周波数を表す。
【００２５】
以下に示す式（２）は、送受信装置間における基準発振器の周波数オフセットを示している。
【００２６】
【数２】

【００２７】
ここで、ｆ_{ＴＣＸＯｏｆｆｓｅｔ}は送受信装置間における基準発振周波数オフセット、ｆ_{ＴｘＴＣＸＯ}は送信装置の基準発振器の周波数、ｆ_{ＲｘＴＣＸＯ}は受信装置の基準発振器の周波数を表す。ローカルの発振器は、電圧制御発振器の出力周波数をＮ分割した周波数と基準発振器の周波数とを比較し、比較した結果を元に電圧制御発振器の電圧を制御して周波数を制御しているため、以下に示す式（３）のように送受信装置間におけるキャリア周波数オフセットと送信装置のローカルの発振器の周波数の比と送受信装置間における基準発振周波数オフセットと送信装置の基準発振器の周波数との比は等しい。
【００２８】
【数３】

【００２９】
以上のように、検出した送受信装置間におけるキャリア周波数オフセットを元に、送受信装置間における基準発振周波数オフセットを検出することができる。
【００３０】
次に、クロックオフセットと基準発振周波数オフセットの関係を説明する。
以下に示す式（４）は、送受信装置間におけるクロックオフセットを示している。
【００３１】
【数４】

【００３２】
ここで、ｆ_{ｃｌｋｏｆｆｓｅｔ}は送受信装置間におけるクロックオフセット、ｆ_{Ｔｘｃｌｋ}は、送信装置のＢＢ部を制御するクロック周波数、ｆ_{Ｒｘｃｌｋ}は受信装置のＢＢ部を制御するクロック周波数を表す。ＢＢ部を制御するクロック周波数は基準発振器により生成されるため、以下の式（５）に示されるように、送受信装置間におけるクロックオフセットと送信装置のＢＢ部を制御するクロック周波数の比と送受信装置間における基準発振周波数オフセットと送信装置の基準発振器の周波数の比とは等しいと表せる。
【００３３】
【数５】

【００３４】
以上のように、検出した送受信装置間における基準発振周波数オフセットを元に、送受信装置間におけるクロックオフセットを検出することができる。上記式（３）、式（５）より、キャリア周波数オフセットとクロックオフセットの関係は以下に示す式（６）のように表せる。
【００３５】
【数６】

【００３６】
上記の式（６）を用いて、クロックオフセット検出部１１０では周波数オフセット検出部１０４より出力されるキャリア周波数オフセットを元に、ローカルの発振器１００の発振周波数に応じたクロックオフセットを算出する。
【００３７】
次に、ＦＦＴウィンドウタイミングオフセットとクロックオフセットとの関係について説明する。本実施の形態によるＯＦＤＭ通信システムでは、パケット信号先頭部のシンボルより検出した同期情報を元に、後続のデータシンボルに対して１シンボル毎に固定のタイミング間隔をあけてＦＦＴウィンドウタイミングを設定しているため、ＦＦＴウィンドウタイミングオフセットは同期情報を検出したパケット信号先頭部のシンボルからの時間間隔に比例して増加する。ＢＢ部はクロックにより制御されているため、以下に示す式（７）のように、ＦＦＴ部においてＦＦＴ処理を行うデータシンボルのパケット信号先頭部のシンボルからの時間間隔とＦＦＴウィンドウタイミングオフセットとの比と、送受信装置間におけるクロックオフセットと送信装置のＢＢ部を制御するクロック周波数の比とは等しいと表せる。
【００３８】
【数７】

【００３９】
ここで、ΔｔはＦＦＴウィンドウタイミングオフセット、ＴはＦＦＴ部においてＦＦＴ処理を行うデータシンボルのパケット信号先頭部のシンボルからの時間間隔を表す。以上のように、検出した送受信装置間におけるクロックオフセットを元に、送受信装置間におけるＦＦＴウィンドウタイミングオフセットをデータシンボル毎に検出することができる。上記式（７）を用いて、位相差検出部１１１では、クロックオフセット検出部１１０より出力されるクロックオフセットとシステム制御部１０９より出力されるパケット信号先頭部のシンボルとデータシンボルの時間間隔とに基づき、ＦＦＴウィンドウタイミングオフセットを算出する。
【００４０】
次に、パケット信号先頭部のシンボルとデータシンボルの位相差とＦＦＴタイミングオフセットの関係を説明する。ＦＦＴ部に入力されるパケット信号先頭部のシンボルの時間波形を以下に示す式（８）によると、ＦＦＴ部においてΔｔのＦＦＴウィンドウタイミングオフセットが生じるデータシンボルの時間波形は以下の式（９）で示すことができる。
【００４１】
【数８】

【００４２】
【数９】

【００４３】
ここで、ａ_ｋはＩ相の信号点配置、ｂｋはＱ相の信号点配置、Ｎはサブキャリア数、ｆ_ｋはサブキャリア周波数、ｔは時間を表す。
【００４４】
図１５（Ａ）、（Ｂ）に、パケット信号先頭部のシンボルとデータシンボルのサブキャリア毎の位相差を表す説明図を示す。なお、１例としてＱＰＳＫ（Ｑｕａｄｒａｔｕｒｅ Ｐｈａｓｅ Ｓｈｉｆｔ Ｋｅｙｉｎｇ）の信号点配置を用いる。ここで、白点はＦＦＴウィンドウタイミングオフセットがない場合の信号点配置であり、黒点はＦＦＴウィンドウタイミングオフセットがある場合の信号点配置である。また、図１５（Ａ）のｋ→ｌｏｗは周波数が低いサブキャリア、図１５（Ｂ）のｋ→ｈｉｇｈは周波数が高いサブキャリアを示している。
【００４５】
ＦＦＴウィンドウタイミングオフセットが生じる場合、ＦＦＴウィンドウタイミングオフセットがない場合のデータシンボルと位相差θ_ｋが生じる。この位相差θ_ｋはパケット信号先頭部のシンボルとの初期位相のずれを示している。サブキャリア毎の位相差θ_ｋは上記式（９）を展開した下記式（１０）より、下記式（１１）と表せる。
【００４６】
【数１０】

【００４７】
【数１１】

【００４８】
上記式（１１）が示しているように、サブキャリア周波数が高くなるにつれて位相差が大きくなる。上記式（７）、式（１１）を用いて、位相差検出部１１１では算出したＦＦＴウィンドウタイミングオフセットを元に、サブキャリア周波数に応じた位相差を算出する。位相差補正部１１２では、位相差検出部１１１より出力される位相差を元に、ＦＦＴ処理後のデータシンボルのサブキャリア毎の位相回転量を算出する。以下に示す式（１２）は、上記式（１０）を展開した式である。尚、θ_ｋ＝２πｆ_ｋΔｔを用いる。下記式（１３）に、下記式（１２）をｃｏｓ（２πｆ_ｋｔ）とｓｉｎ（２πｆ_ｋｔ）でまとめた式を示す。
【００４９】
【数１２】

【００５０】
【数１３】

【００５１】
下記式（１４）、（１５）に、上記式（１３）の時間波形をＦＦＴ処理した周波数波形のＩ相、Ｑ相を示す。上記式（１３）に示すｃｏｓ（２πｆ_ｋｔ）とｓｉｎ（２πｆ_ｋｔ）の係数がＦＦＴ処理を行った後、Ｉ相、Ｑ相のデータとしてそれぞれ出力される。
【００５２】
【数１４】

【００５３】
【数１５】

【００５４】
下記式（１６）に回転行列を示す。
【数１６】

【００５５】
ＦＦＴ処理後のデータは、上記式（１４）、式（１５）に示すように位相がθ_ｋ回転している。位相差補正部１１２では下記式（１７）に示すように上記式（１４）、（１５）を要素とする行列と位相がθ_ｋである上記式（１６）の回転行列を計算することにより位相回転を除去する。
【００５６】
【数１７】

【００５７】
下記式（１８）、（１９）に、上記式（１７）の計算を行った後のＩ相、Ｑ相を示す。
【００５８】
【数１８】

【００５９】
【数１９】

【００６０】
位相差補正部１１２では、上記式（１７）の計算をすることによりＦＦＴ処理後のデータシンボルのサブキャリア毎の位相回転を除去し、上記式（１８）、（１９）のデータを出力する。
【００６１】
尚、通常、ローカルの発振器１００の発振周波数はシステム帯域内において複数の値が設定されているが、異なる発振周波数間の周波数差があまり大きくない場合、上記式（６）において送信装置の基準発振器の発振周波数を固定の値とすることにより回路を簡略化し、演算量を削減することができる。
【００６２】
また、本実施の形態おいてはクロックオフセット検出部１１０では、上記式（６）の計算、位相差検出部１１１では上記式（７）、（１１）の計算、位相差補正部１１２では位相差検出部１１１より出力される位相差を元に位相回転を行っているが、上記式（６）、（７）を上記式（１１）に代入した式を構成とした回路とすることもできるし、周波数オフセット検出部１０４より出力される周波数オフセットが入力されるとすぐに位相回転を行う構成とした回路とすることもできる。つまり、クロックオフセット検出部１１０、位相差検出部１１１、位相差補正部１１２を各々組み合わせて一つの回路構成とすることもできる。
【００６３】
次に、本発明の第１の実施の形態によるＯＦＤＭ通信システムの受信装置の回路構成について説明する。図２に、本実施の形態による受信装置の回路構成例を示す。図２において、図１と同一構成部分には同一符号を付している。上記受信装置の各ブロックにおける動作の説明に沿って説明を行う。周波数オフセット検出部１０４より出力される信号は、上記動作説明における周波数オフセットｆ_{ｃａｒｒｉｅｒｏｆｆｓｅｔ}Ｃ１である。クロックオフセット検出部１１０では、上記式（６）の左辺の分母項であるローカルの発振器の周波数ｆ_ＴＸＬＯの逆数をＲＯＭ１に記憶しており、使用するローカルの発振器の周波数に応じた値をＲＯＭ１より出力し、乗算器２において周波数オフセットＣ１と乗算する。
【００６４】
図３に、ＲＯＭ１に記憶する値の例を示す。図３（Ａ）は、ＲＯＭ１において記憶する値の概略例である。ＲＯＭ１では、１／ｆ_ＴｘＬｏの値を記憶している。入力されるアドレスがｆ_{ＴｘＬｏ１}であれば、ＲＯＭ１は、１／ｆ_{ＴｘＬｏ１}を出力する。図３の（Ｂ）は、ＲＯＭ１において記憶する値の具体例であり、例えば「ＡＲＩＢＳＴＤ−Ｔ７０」において述べられている使用周波数に対応した値である。通信時に使用する周波数が５．１７０×１０^９Ｈｚであれば、ＲＯＭ１にアドレス１を入力し、ＲＯＭ１は１／５．１７０×１０^９を出力する。乗算器２の出力として、上記式（６）の右辺項であるクロックオフセット比ｆ_{ｃｌｋｏｆｆｓｅｔ}／ｆ_{ＴｘｃｌｋＣ２}が出力され、位相差検出部１１１（図２）に入力される。位相差検出部１１１では、先ず上記式（７）の左辺の分子項であるＦＦＴウィンドウタイミングオフセットΔｔを算出する。
【００６５】
システム制御部１０９からデータシンボルのパケット信号先頭部の既知パターンからの時間間隔ｔを出力する。乗算器３において、クロックオフセット比Ｃ２と時間間隔を乗算し、ＦＦＴウィンドウタイミングオフセットＣ３を出力する。
次に、上記式（１１）の左辺の項である位相差θ_ｋを算出する。ＲＯＭ４（図２）には上記式（１１）の右辺項の一部である２πｆ_ｋを記憶しており、乗算器５において、ＦＦＴウィンドウタイミングオフセットＣ３とサブキャリア毎の２πｆ_ｋを乗算し、位相差Ｃ４をサブキャリア数個出力し位相差補正部１１２に入力する。
【００６６】
図４は、ＲＯＭ４に記憶する値の一例を示す図である。図４（Ａ）は、ＲＯＭ４において記憶される値の例である。ＲＯＭ４では、２πｆ_ｋの値を記憶している。入力されるアドレスがｆ_１であれば、ＲＯＭ４は２πｆ_１を出力する。図４（Ｂ）は、ＲＯＭ４において記憶する値の具体例であり、例えば「ＡＲＩＢ ＳＴＤ−Ｔ７０」において述べられているサブキャリア配置に対応した値である。ここでは、ＯＦＤＭ使用周波数帯域が２０ＭＨｚ、５２個の情報サブキャリア数、１２個のヌルサブキャリア数の場合について示す。最もサブキャリア周波数が低いサブキャリアの位相差Ｃ４を出力する場合は、ＲＯＭ４にアドレス１を入力し、ＲＯＭ４は２π×３１２．５×１０^３×（−２６）を出力して、乗算器５においてＦＦＴウィンドウタイミングオフセットＣ３と乗算して出力する。最もサブキャリア周波数が高いサブキャリアの位相差Ｃ４を出力する場合は、ＲＯＭ４にアドレス５２を入力し、ＲＯＭ４は２π×３１２．５×１０^３×２６を出力して、乗算器５においてＦＦＴウィンドウタイミングオフセットＣ３と乗算して出力する。
【００６７】
位相差補正部１１２では、回転行列と周波数軸信号を行列演算することにより周波数軸信号の位相回転を除去する。ＲＯＭ７には、位相に応じた上記式（１７）の要素ｃｏｓθを記憶しており、ＲＯＭ８には位相に応じた上記式（１７）の要素ｓｉｎθを記憶している。コントローラ６は、位相差Ｃ４から位相回転を行う際に用いるｃｏｓθ、ｓｉｎθを判定し、対応したアドレスをＲＯＭ７、ＲＯＭ８に対して出力する。ＲＯＭ７、ＲＯＭ８ではコントローラ６から入力されるアドレスに応じたｃｏｓθ、ｓｉｎθを出力する。
【００６８】
図５は、ＲＯＭ７、ＲＯＭ８に記憶する値の例を示す図である。ＲＯＭ７では、ｃｏｓθの値を記憶している。ＲＯＭ８では、ｓｉｎθの値を記憶している。入力されるアドレスがθ１であれば、ＲＯＭ７はｃｏｓθ１を出力し、ＲＯＭ８はｓｉｎθ１を出力する。図６（Ａ）、（Ｂ）に、それぞれＲＯＭ７、ＲＯＭ８に記憶する値の具体例を示す説明図を示す。ここでは、例えば、ＲＯＭ７、ＲＯＭ８において、位相差検出部１１１からの出力である信号の位相差が１°、４°、７°の値に対応したｃｏｓθ、ｓｉｎθを記憶している場合について示している。
【００６９】
ＲＯＭ７では、アドレス１にｃｏｓ１°、アドレス２にｃｏｓ４°、アドレス３にｃｏｓ７°の値を記憶している。ＲＯＭ８では、アドレス１にｓｉｎ１°、アドレス２にｓｉｎ４°、アドレス３にｓｉｎ７°の値を記憶している。位相差検出部１１１からの出力である信号の位相差が７°であった場合、位相差補正部１１２のコントローラ６はアドレス３をＲＯＭ７、およびＲＯＭ８に出力する。
アドレス３が入力されたＲＯＭ７は０．９９９８１０９６３を出力し、ＲＯＭ８は０．０１９４４３２１９を出力する。
【００７０】
乗算器１０には上記式（１７）の回転行列の１行１列目のｃｏｓθが入力され、乗算器１１には上記式（１７）の回転行列の２行１列目のｓｉｎθが入力され、乗算器１２には上記式（１７）の回転行列の２行２列目のｃｏｓθが入力され、乗算器１３にはＲＯＭ８の出力を符号反転部９において符号反転した上記式（１７）の回転行列の１行２列目の−ｓｉｎθが入力される。また、乗算器１０、１２には周波数軸信号のＩ相Ｓ５．１、乗算器１１、１３には周波数軸信号のＱ相Ｓ５．２が入力され、ＲＯＭ７、８からの入力と乗算する。加算器１４において、上記式（１８）に示すように乗算器１０、１３の出力を加算し、位相回転を除去した周波数軸信号Ｉ相Ｓ７．１を出力する。加算器１５において上記式（１９）に示すように乗算器１１、１２の出力を加算し、位相回転を除去した周波数軸信号Ｑ相Ｓ７．２を出力する。そして、位相差補正部１１２において位相回転を除去した周波数軸信号を復調部に入力する。
【００７１】
本発明の第１の実施の形態によるＯＦＤＭ受信装置の位相差補正部１１２の動作手順について説明する。１ＯＦＤＭシンボル間で生じるＦＦＴウィンドウタイミングオフセットは相当に小さい値なので、パケット長が短い場合には影響が余りなく、パケット長が長い場合に受信誤り率特性の劣化を生じる。また、図２のＲＯＭ７、ＲＯＭ８において位相差θ_ｋに対応したｃｏｓ（θ_ｋ）、およびｓｉｎ（θ_ｋ）を無限に記憶しておくことはできない。そのため、複数の任意の値をＲＯＭ７、ＲＯＭ８に記憶しておき、算出した位相差が予め任意に設定した値に達した場合から位相差補正部１１２において位相回転の除去を行うとともに、設定する値を次の値に更新し、算出した位相差が更新した値に達した場合に、現ステップの位相差判定で設定した位相差と前ステップの位相差判定で設定した位相差の差分に対応した位相を用いて位相回転の除去値を行い、次ステップの位相差判定に進む。以降、パケットの受信を終了するまで、上記手順を行う。
【００７２】
図７は、本発明の第１の実施の形態による位相差補正部１１２の動作の一例を示すフローチャート図である。図７では、位相差判定の回数が２回であり、位相差判定は位相差が一番大きい最も周波数の高いサブキャリアにおいて行う場合を例に示す。位相差補正部１１２に位相差検出部１１１からの出力が入力されると、ステップＳ１において、位相差検出部１１１からの出力の中で最も周波数の高いサブキャリアの位相差θ_ｍａｘが正か負かを判定する。ステップＳ１において判定結果がＹＥＳの場合ステップＳ２Ｌに進み、判定結果がＮＯの場合ステップＳ２Ｓに進む。ステップＳ２Ｌに進んだ場合、位相差θ_ｍａｘが予め任意に設定した位相差θ_ｓ１に達したか否かの位相差判定を行う。
【００７３】
ステップＳ２Ｌにおいて、判定結果がＹＥＳの場合ステップＳ３Ｌに進み、判定結果がＮＯの場合は信号を出力する。ステップＳ３Ｌに進んだ場合、最も周波数の高いサブキャリアの位相差判定に用いた位相θ_ｓ１に対応した各サブキャリアの位相回転量を用いて位相回転の除去を行い、ステップＳ４Ｌに進む。ステップＳ４Ｌにおいて予め任意に設定した位相差θ_ｓ２に達したか否かの位相差判定を行う。ステップＳ４Ｌにおいて、判定結果がＹＥＳの場合、ステップＳ５Ｌに進み、判定結果がＮＯの場合、信号を出力する。ステップＳ５Ｌに進んだ場合、ステップＳ５Ｌにおいて設定した位相差θ_ｓ２とステップＳ３Ｌにおいて設定した位相差θ_ｓ１の差分（θ_ｓ２―θ_ｓ１）に対応した各サブキャリアの位相回転量を用いて位相回転の除去を行い、信号を出力する。ステップＳ２Ｓに進んだ場合、位相差θ_ｍａｘが予め任意に設定した位相差θ_ｓ３に達したか否かの位相差判定を行う。ステップＳ２Ｓにおいて判定結果がＹＥＳの場合ステップＳ３Ｓに進み、判定結果がＮＯの場合、信号を出力する。ステップＳ３Ｓに進んだ場合、最も周波数の高いサブキャリアの位相差判定に用いた位相θ_ｓ３に対応した各サブキャリアの位相回転量を用いて位相回転の除去を行い、ステップＳ４Ｓに進む。ステップＳ４Ｓにおいて予め任意に設定した位相差θ_ｓ４に達したか否かの位相差判定を行う。ステップＳ４Ｓにおいて判定結果がＹＥＳの場合、ステップＳ５Ｓに進み、判定結果がＮＯの場合、信号を出力する。
【００７４】
ステップＳ５Ｓに進んだ場合、ステップＳ５Ｓにおいて設定した位相差θ_ｓ４とステップＳ３Ｓにおいて設定した位相差θ_ｓ４の差分（θ_ｓ４―θ_ｓ３）に対応した各サブキャリアの位相回転量を用いて位相回転の除去を行い、信号を出力する。
【００７５】
尚、位相差補正部１１２において位相差検出部１１１の出力である位相差が予め任意に設定した位相差以上か否かを判定する際に、１つのサブキャリアにおいて判定を行うのではなく、複数のサブキャリアにおいて判定を行うこともできる。この場合、複数のサブキャリアにおける判定の平均値、最大値、或いは、最小値、或いは、最大値と最小値の中間値に基づいて判定を行うこともできる。
【００７６】
また、サブキャリア周波数が低いサブキャリアにおいてはＦＦＴウィンドウタイミングオフセットによって生じる位相差が小さいため、位相回転の除去動作を省略することもできる。さらに、位相差補正部１１２において位相差によって動作を制御するのではなく、図１の各ブロックにおいて出力される周波数オフセット、クロックオフセット、ＦＦＴウィンドウタイミングオフセットによって動作を制御することもできる。
【００７７】
次に、本発明の第２の実施の形態によるＯＦＤＭ受信機について説明する。図２におけるＲＯＭ７、ＲＯＭ８において、複数の位相差θ_ｋに対応したｃｏｓ（θ_ｋ）、およびｓｉｎ（θ_ｋ）を記憶しておくことは回路規模増大に繋がる。本発明の第２の実施の形態によるＯＦＤＭ受信装置の位相差補正部１１２の動作手順について説明する。本発明の第２の実施の形態によるＯＦＤＭ受信装置は、算出した位相差が所定の値以上の場合、予め任意に設定した位相をパラメータとした位相回転の除去を行い、位相回転の除去後の信号の位相差が所定の値以下になった場合に出力を行うことにより、ＲＯＭ７、ＲＯＭ８のｃｏｓ（θ_ｋ）、およびｓｉｎ（θ_ｋ）を１組のサブキャリア数分だけ記憶するものにし、回路規模を低減することを特徴としている。
【００７８】
図８は、本発明の第２の実施の形態による位相差補正部１１２の動作の一例を示すフローチャート図である。図８では、位相差判定は位相差が一番大きい最も周波数の高いサブキャリアにおいて行う場合について示す。位相差検出部１１１からの出力が位相差補正部１１２に入力されると、ステップＳ１１において、位相差検出部１１１からの出力の中で最も周波数の高いサブキャリアの位相差θ_ｍａｘが正か負かを判定する。ステップＳ１１において、判定結果がＹＥＳの場合ステップＳ１２Ｌに進み、判定結果がＮＯの場合ステップＳ１２Ｓに進む。ステップＳ１２Ｌに進んだ場合、位相差θ_ｍａｘが予め任意に設定した位相差θ_１に達したか否かの位相差判定を行う。ステップＳ１２Ｌにおいて、判定結果がＹＥＳの場合はステップＳ１３Ｌに進み、判定結果がＮＯの場合は信号を出力する。ステップＳ１３Ｌに進んだ場合、最も周波数の高いサブキャリアの位相差判定に用いた位相θ_１に対応した各サブキャリアの位相回転量を用いて位相回転の除去を行い、ステップＳ１４Ｌに進む。ステップＳ１４ＬにおいてステップＳ１２Ｌにおいて判定を行った位相差θ_ｍａｘからθ_１を減算し、減算した値を位相差θ_ｍａｘとして更新し、ステップＳ１２Ｌに戻る。以降、ステップＳ１２Ｌにおいて判定結果がＮＯとなるまで上記ステップを繰り返し、出力する。
【００７９】
図８において、ｖは上記ステップの繰り返し回数である。ステップＳ１２Ｓに進んだ場合、位相差θ_ｍａｘが予め任意に設定した位相差θ_ｍに達したか否かの位相差判定を行う。ステップＳ１２Ｓにおいて判定結果がＹＥＳの場合、ステップＳ１３Ｓに進み、判定結果がＮＯの場合は信号を出力する。ステップＳ１３Ｓに進んだ場合、最も周波数の高いサブキャリアの位相差判定に用いた位相θ_ｍに対応した各サブキャリアの位相回転量を用いて位相回転の除去を行い、ステップＳ１４Ｓに進む。ステップＳ１４ＳにおいてステップＳ１２Ｓにおいて判定を行った位相差θ_ｍａｘにθ_ｍを加算し、加算した値を位相差θ_ｍａｘとして更新し、ステップＳ１２Ｓに戻る。以降、ステップＳ１２Ｓにおいて判定結果がＮＯとなるまで上記ステップを繰り返し、出力する。図８において、ｗは上記ステップの繰り返し回数である。
【００８０】
本発明の第３の実施の形態によるＯＦＤＭ受信装置について説明する。図９に、本発明の第３の実施の形態によるＯＦＤＭ通信システムにおける受信装置の概略構成を示す要部ブロック図を示す。また、図１と同一構成部分については同一符号を付している。図９において、符号１１３はＦＦＴウィンドウタイミングオフセット検出部であり、ＦＦＴウィンドウタイミング検出部１０６に関しては本発明の第１の実施の形態によるものと機能が異なる。本実施の形態によるＯＦＤＭ通信システムの動作の概略を説明する。
【００８１】
アンテナで受信した高周波信号Ｓ１は乗算器１０１に入力されて、基準発振器１００００により周波数生成されるローカルの発振器出力と乗算及びダウンコンバートされてベースバンド信号Ｓ２が出力される。ベースバンド信号Ｓ２は基準発振器１００００によりＯＦＤＭ信号生成が行われるＢＢ（Ｂａｓｅ Ｂａｎｄ）部１００１のＡ／Ｄ変換器１０２に入力されて、アナログ信号からディジタル信号に変換されてベースバンド信号Ｓ３が出力される。相関検出部１０３において受信パケット信号先頭部の同一波形間の相関値を算出する。この相関値を元に周波数オフセット検出部１０４においてキャリア周波数オフセットが算出され、ＦＦＴウィンドウタイミング検出部１０６においてＦＦＴウィンドウタイミングが検出される。周波数オフセット検出部１０４において算出されたキャリア周波数オフセットを元に、周波数オフセット補正部１０５においてベースバンド信号Ｓ３に対してキャリア周波数オフセットの除去を行い、ベースバンド信号Ｓ４を出力する。周波数オフセット検出部１０４において算出されたキャリア周波数オフセットを元に、クロックオフセット検出部１１０においてクロックオフセットを算出する。クロックオフセット検出部１１０において算出されたクロックオフセットとシステム制御部１０９より出力されるパケット信号先頭部のシンボルとデータシンボルの時間間隔を元に、ＦＦＴウィンドウタイミングオフセット検出部１１３においてパケット信号先頭部のシンボルとデータシンボルとのＦＦＴウィンドウタイミングオフセットを算出する。
【００８２】
ＦＦＴウィンドウタイミングオフセット検出部１１３において算出されたＦＦＴウィンドウタイミングオフセットを元に、ＦＦＴウィンドウタイミング検出部１０６においてＦＦＴウィンドウタイミングの補正を行う。ＦＦＴウィンドウタイミング検出部１０６において検出及び補正されたＦＦＴウィンドウタイミングを元に、ＦＦＴ部１０７においてベースバンド信号Ｓ４に対してＦＦＴ処理を行い、時間軸信号から周波数軸信号に変換して周波数軸信号Ｓ５を出力する。周波数軸信号Ｓ５は復調回路１０８に入力されて復調信号Ｓ６が出力される。復調信号Ｓ６はシステム制御部１０９に入力される。以下、本発明の受信装置の各ブロックにおける動作の説明を行う。
【００８３】
パケット信号先頭部のシンボルとデータシンボルはＦＦＴウィンドウタイミングオフセットによりＦＦＴ部１０７に入力される時間波形が上記式（８）、（９）のようになる。ＦＦＴウィンドウタイミングオフセット検出部１１３において上記式（７）のようにＦＦＴウィンドウタイミングオフセットΔｔを検出する。
ＦＦＴウィンドウタイミング検出部１０６においてＦＦＴウィンドウタイミングをΔｔだけずらしてＦＦＴ部７に補正したＦＦＴウィンドウタイミングを出力する。ＦＦＴ部７では補正されたＦＦＴウィンドウタイミングを用いてデータシンボルに対してＦＦＴウィンドウを設定する。従来、上記式（９）のような時間波形に対してＦＦＴ処理を行っていたものを上記式（８）のような時間波形となるＦＦＴウィンドウタイミングでＦＦＴ処理を行うことによりパケット信号先頭部のシンボルとデータシンボルの位相差を除去する。
【００８４】
本発明の第３の実施形態のＯＦＤＭ通信システムの受信装置の回路構成について説明する。図１０に本発明の第３の実施形態の受信装置のブロックの回路構成の１例を示す。また、図９および図２と同一構成部分には同一符号を付している。上記本発明の第１の実施形態の受信装置の各ブロックにおける動作の説明を参照しながら説明を行う。
【００８５】
周波数オフセット検出部１０４より出力される信号は、上記動作説明における周波数オフセットｆ_{ｃａｒｒｉｅｒｏｆｆｓｅｔ}Ｃ１である。クロックオフセット検出部１１０では、上記式（６）の左辺の分母項であるローカルの発振器の周波数 の逆数をＲＯＭ１に記憶しており、使用するローカルの発振器の周波数に応じた値をＲＯＭ１より出力し、乗算器２において周波数オフセットＣ１と乗算する。乗算器２の出力として上記式（６）の右辺項であるクロックオフセット比ｆ_{ｃｌｋｏｆｆｓｅｔ}／ｆ_{Ｔｘｃｌｋ}Ｃ２が出力され、ＦＦＴウィンドウタイミングオフセット検出部１１３に入力される。ＦＦＴウィンドウタイミングオフセット検出部１１３では、上記式（７）の左辺の分子項であるＦＦＴウィンドウタイミングオフセットΔｔを算出する。システム制御部１０９からデータシンボルのパケット信号先頭部の既知パターンからの時間間隔ｔを出力する。乗算器３においてクロックオフセット比Ｃ２と時間間隔を乗算し、ＦＦＴウィンドウタイミングオフセットＣ３を出力し、ＦＦＴウィンドウタイミング検出部１０６に入力する。ＦＦＴウィンドウタイミング検出部１０６では、ＦＦＴウィンドウタイミングオフセット検出部１１３の出力であるＦＦＴウィンドウタイミングオフセットＣ３を元に、ＦＦＴウィンドウタイミングの補正を行う。
【００８６】
以上、本発の各実施の形態によるＯＦＤＭ受信装置によれば、ＦＦＴウィンドウタイミングオフセットによる受信信号の誤り率の劣化を低減することができ、良好な通信品質を維持しつつ、一度に送受信可能なパケット長を増大することができる。また、従来の周波数オフセット検出回路を拡張し、ＦＦＴタイミングオフセットの補正を行う回路構成とすることにより、大幅な回路変更及び回路規模増大を避けることができる。
【００８７】
以上、実施の形態に沿って本発明を説明したが、本発明はこれらに制限されるものではない。その他、種々の変更、改良、組み合わせが可能なことは当業者に自明であろう。例えば、ひとつの基準発振器を元に、ローカル発振器の周波数生成とＯＦＤＭ信号の生成とを行う技術中には、必ずしも基準発振器が１個のみの場合に限定されるわけではなく、実際には基準クロックの同期がとれていれば、２以上の発振器を用いている技術も含まれる。
【００８８】
【発明の効果】
本発明によれば、ＦＦＴウィンドウタイミングオフセットによる受信信号の誤り率の劣化を低減することができ、良好な通信品質を維持しつつ、一度に送受信可能なパケット長を増大することができる。また、従来の周波数オフセット検出回路を拡張し、ＦＦＴタイミングオフセットの補正を行う回路構成とすることにより、大幅な回路変更及び回路規模増大を避けることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態のＯＦＤＭ通信システムの受信装置の概略構成を示す要部ブロック図である。
【図２】本発明の第１の実施形態の受信装置のブロックの回路構成例を示す図である。
【図３】本発明の受信装置の位相差補正部のＲＯＭ１に記憶する値の１例を示す説明図である。
【図４】本発明の受信装置の位相差補正部のＲＯＭ４に記憶する値の１例を示す説明図である。
【図５】本発明の受信装置の位相差補正部のＲＯＭ７、ＲＯＭ８に記憶する値の概略例を示す説明図である。
【図６】本発明の受信装置の位相差補正部のＲＯＭ７、ＲＯＭ８に記憶する値の具体例を示す説明図である。
【図７】本発明の第１の実施形態の位相差補正部の動作を示すフローチャートである。
【図８】本発明の第２の実施形態の位相差補正部の動作を示すフローチャートである。
【図９】本発明の第３の実施形態のＯＦＤＭ通信システムの受信装置の概略構成を示す要部ブロック図である。
【図１０】本発明の第３の実施形態の受信装置のブロックの回路構成の１例を示す図である。
【図１１】従来のＯＦＤＭ通信システムのパケットフォーマットの一例を示す模式図である。
【図１２】受信信号の伝搬路変動補償を示す動作説明図である。
【図１３】パケット内のデータシンボル位置とＦＦＴウィンドウタイミングのオフセットとデータシンボルの位相差の関係を示した説明図である。
【図１４】本発明の想定するシステムの基準発振器の動作の概略を示す要部ブロック図である。
【図１５】パケット信号先頭部のシンボルとデータシンボルのＦＦＴ処理により検出される位相を表す説明図である。
【図１６】従来のＯＦＤＭ通信システムの受信装置の概略構成を示す要部ブロック図である。
【符号の説明】
Ｓ１：高周波信号
Ｓ２：アナログベースバンド信号
Ｓ３：デジタルベースバンド信号
Ｓ４：周波数オフセット除去ベースバンド信号
Ｓ５：周波数軸ベースバンド信号
Ｓ５．１：周波数軸ベースバンド信号Ｉ相
Ｓ５．２：周波数軸ベースバンド信号Ｑ相
Ｓ６：復調信号
Ｓ７：位相差除去後周波数軸信号
Ｓ７．１：位相差除去後周波数軸信号Ｉ相
Ｓ７．２：位相差除去後周波数軸信号Ｑ相
Ｃ１：周波数オフセット
Ｃ２：クロックオフセット比
Ｃ３：ＦＦＴウィンドウタイミングオフセット
Ｃ４：位相差
１、４、７、８：ＲＯＭ
２、３、５、１０、１１、１２、１３：乗算器
６：コントローラ
９：符号反転部
１４、１５：加算器
１００：ローカルの発振器
１０１：乗算器
１０２：Ａ／Ｄ変換器
１０３：相関検出部
１０４：周波数オフセット検出部
１０５：周波数オフセット補正部
１０６：ＦＦＴウィンドウタイミング検出部
１０７：ＦＦＴ部
１０８：復調部
１０９：システム制御部
１１０：クロックオフセット検出部
１１１：位相差検出部
１１２：位相差補正部
１１３：ＦＦＴウィンドウタイミングオフセット検出部
１０００：ＲＦ部
１００１：ＢＢ部[0001]
[Field of the Invention]
The present invention relates to a wireless communication device of a wireless communication system such as a mobile phone and a wireless LAN, and more particularly to a receiving apparatus and an FFT window timing offset correction method of a wireless packet communication system using an OFDM (Orthogonal Frequency Division Multiplexing) transmission method.
[0002]
[Prior art]
The OFDM transmission method is a method of transmitting information using a plurality of orthogonally related carriers. Based on the input information signal, modulation such as QPSK (Quadrature Phase Shift Keying) and QAM (Quadrature Amplitude Modulation) is performed for each subcarrier. Further, an OFDM signal is generated for the modulated output using an IFFT (Inverse Fast Fourier Transform) circuit. In the OFDM transmission type receiving apparatus, it is necessary to remove the influence of the carrier frequency offset, and it is necessary to perform synchronization such as detection of FFT window timing. Packet transmission is a method of transmitting data by dividing data into short packet signals, and it is necessary to establish synchronization for each packet signal. Normally, synchronization is established from the symbol at the head of the packet signal in terms of transmission efficiency, and synchronization with subsequent data symbols is established based on synchronization information detected from the symbol at the head of the packet signal.
[0003]
FIG. 16 is a block diagram illustrating a main part of a schematic configuration of a receiving device in a conventional OFDM communication system. In FIG. 16, S1 is a high-frequency signal input from the antenna, 100 is a local oscillator, 101 is a multiplier that multiplies the local oscillator 100 and the high-frequency signal S1 and outputs a baseband signal S2, and S2 is a local oscillator. A baseband signal down-converted by the oscillator 100, a reference numeral 102 denotes an A / D converter for converting an analog signal to a digital signal, a reference numeral S3 denotes a baseband signal converted from an analog signal to a digital signal by the A / D converter 102, 103 is a correlation detector, 104 is a frequency offset detector, 105 is a frequency offset corrector that corrects the carrier frequency offset calculated by the frequency offset detector 104, 106 is an FFT window timing detector, and S4 is a frequency offset corrector. Carrier circumference by 105 A baseband signal from which a number offset has been removed, 107 is an FFT unit for converting a time axis signal to a frequency axis signal, S5 is a frequency axis signal converted from a time axis signal to a frequency axis signal by the FFT unit 107, and 108 is a demodulation unit. , S6 are demodulated signals demodulated by the demodulation unit 108, and 109 is a system control unit.
[0004]
FIG. 11 is a schematic diagram illustrating a configuration example of a packet format of an OFDM communication system (for example, see Non-Patent Document 1).
[0005]
In FIG. 11, GI (Guard Interval) represents a guard interval, KP (Known Pattern) represents a known pattern (for example, a pilot symbol), and D (Data) represents data. In this packet format, known symbols used for frequency offset detection, FFT window timing detection, and the like are repeatedly arranged at the head of the packet signal, and two symbols are arranged, followed by data symbols for information transmission. The outline of the operation of the conventional OFDM communication system will be described based on the above configuration example. As shown in FIG. 16, the high-frequency signal S1 received by the antenna is input to the multiplier 101, multiplied and down-converted by the output of the local oscillator 100, and the baseband signal S2 is output.
[0006]
The baseband signal S2 is input to the A / D converter 102, and is converted from an analog signal to a digital signal and output. In general, a deviation occurs between the oscillator frequency of the transmitting device and the oscillator frequency of the receiving device, and therefore, a carrier frequency offset occurs in the baseband signal S3. Further, since the arrival timing of the received signal is unknown, the receiving apparatus needs to detect the FFT window timing. Since the same waveform is repeatedly included in two symbols at the head of the received packet signal as shown in FIG. 11, the correlation detecting section 103 calculates a correlation value between the same waveforms. Based on this correlation value, the carrier frequency offset is calculated in frequency offset detecting section 104, and the FFT window timing is detected in FFT window timing detecting section 106.
[0007]
Based on the carrier frequency offset calculated by frequency offset detecting section 104, frequency offset correcting section 105 removes the carrier frequency offset from baseband signal S3 and outputs baseband signal S4. Based on the FFT window timing detected by the FFT window timing detection unit 106, the FFT unit 107 performs FFT processing on the baseband signal S4, converts the time axis signal into a frequency axis signal, and outputs a frequency axis signal S5. I do. The frequency axis signal S5 is input to the demodulation unit 108, and the demodulation signal S6 is output. Demodulated signal S6 is input to system control section 109.
[0008]
As described with reference to FIG. 11, in the conventional OFDM communication system, the detection of the carrier frequency offset and the signal synchronization are performed by using the synchronization symbol at the head of the packet signal. Synchronization has been established based on the detected synchronization information from the symbol at the head of the packet signal.
[0009]
FIG. 12 shows signal point arrangement d1 of data symbols before propagation path fluctuation compensation and signal point arrangement of data symbols after propagation path fluctuation compensation in which propagation path fluctuation compensation is performed based on propagation path fluctuation information estimated from the synchronization symbol. Indicates d2. Note that d3 is a signal point arrangement of data symbols after propagation path compensation in an ideal state without an FFT window timing offset, and a difference between signal point arrangements of d2 and d3 represents an error (error).
[0010]
[Non-patent document 1]
"Study on Synchronous System of OFDM Modulation System for High-Speed Wireless LAN" IEICE Technical Report RCS-97-210.
[0011]
[Problems to be solved by the invention]
However, according to the above-described synchronization establishment method, the synchronization timing is shifted between the beginning and the end of the packet signal due to the offset of the reference oscillator represented by the carrier frequency offset, and the FFT window timing offset of the known pattern and the data symbol occurs. . The FFT window timing offset causes a phase difference between the known pattern after the FFT processing and the data symbol, and causes a problem that a signal point arrangement deviates from an ideal state.
[0012]
This FFT window timing offset increases as the data symbol starts from the symbol at the beginning of the packet signal and continues to the data symbol as shown in FIG. As a result, the phase difference of the signal after the FFT processing and the error after the compensation for the propagation path fluctuation are increased as the data symbol becomes subsequent to the packet, and the error rate of the signal is deteriorated. Therefore, when the packet length is long, the deterioration of the error rate due to the FFT window timing offset cannot be ignored in the data symbol after the packet.
[0013]
An object of the present invention is to provide a receiving apparatus capable of reducing an FFT window timing offset in an OFDM communication system.
[0014]
[Means for Solving the Problems]
The present invention provides a packet data receiver in which an RF signal generation and a reference clock generation in a transmission device and a reception device are each performed by one reference oscillator, and a means for calculating an offset of the reference oscillator from a frequency offset, Means for calculating a clock offset from the calculated offset, and means for calculating an FFT window timing offset from the calculated clock offset. Based on the detected shift of the reference oscillator, a frequency axis signal which is an output of the FFT unit is provided. It is characterized in that the phase difference is corrected or the setting and adjustment of the FFT window timing are performed.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
The technique according to the present invention focuses on the fact that the cause of the FFT window timing offset is caused by the offset of the reference oscillator in the transmission / reception period as in the case of the carrier frequency offset, and detects the offset of the reference oscillator. To adjust the FFT window timing offset.
[0016]
Hereinafter, an FFT timing offset correction technique and a wireless communication device according to an embodiment of the present invention will be described with reference to the drawings.
[0017]
First, a receiving device of an OFDM communication system according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration example of a receiving device in an OFDM communication system according to a first embodiment of the present invention. 1, the same components as those in FIG. 16 are denoted by the same reference numerals. As shown in FIG. 1, reference numeral 10000 denotes a reference oscillator, 110 denotes a clock offset detector, 111 denotes a phase difference detector, 112 denotes a phase difference corrector, and S7 denotes a frequency axis from which the phase difference has been removed by the phase difference corrector 112. Signal. An outline of the operation of the OFDM communication system according to the present embodiment will be described.
[0018]
The OFDM communication system according to the present embodiment is premised on a system in which frequency generation of a local oscillator and OFDM signal generation are performed by one reference oscillator. The high-frequency signal S1 received by the antenna is input to the multiplier 101, multiplied by the output of the local oscillator 100 generated by the reference oscillator 10000, down-converted, and output as the baseband signal S2. The baseband signal S2 is input to an A / D converter 102 in a BB (Base Band) unit 1001 in which an OFDM signal is generated by a reference oscillator 10000, and is converted from an analog signal to a digital signal to output a baseband signal S3. Is done. Correlation detection section 103 calculates a correlation value between the same waveforms at the beginning of the received packet signal. Based on the correlation value, the carrier frequency offset is calculated in frequency offset detecting section 104, and the FFT window timing is detected in FFT window timing detecting section 106.
[0019]
Based on the carrier frequency offset calculated in frequency offset detection section 104, frequency offset correction section 105 removes the carrier frequency offset from baseband signal S3, and outputs baseband signal S4.
Based on the FFT window timing detected by the FFT window timing detection unit 106, the FFT unit 107 performs FFT processing on the baseband signal S4, converts a time axis signal into a frequency axis signal, and outputs a frequency axis signal S5. . The clock offset detector 110 calculates a clock offset based on the carrier frequency offset calculated by the frequency offset detector 104. Based on the clock offset calculated by clock offset detecting section 110 and the time interval between the symbol of the packet signal head output from system control section 109 and the data symbol, phase difference detecting section 111 detects the packet signal head of the data symbol. Calculate the phase difference with the symbol.
[0020]
Based on the phase difference between the data symbol calculated by the phase difference detection unit 111 and the symbol at the head of the packet signal, the phase difference correction unit 112 removes the phase difference from the frequency axis signal S5, and the frequency axis signal S7 Is output. The frequency axis signal S7 is input to the demodulation unit 108, and the demodulation signal S6 is output. Demodulated signal S6 is input to system control section 109. Hereinafter, the operation of each functional block of the receiving apparatus according to the present embodiment will be described.
[0021]
FIGS. 14A and 14B are main block diagrams schematically showing the operation of the reference oscillator in the OFDM communication system according to the present embodiment. FIG. 14A is a block diagram of the transmitting side Tx, and FIG. 14B is a block diagram of the receiving side (Rx). In the OFDM communication system according to the present embodiment, the RF signal generation and the reference clock generation in the transmission device and the reception device are each performed by one reference oscillator, and the RF (Radio Frequency) unit 1000 and the BB (BaseBand) in FIG. The unit 1001 is controlled by the same reference oscillator 10000. In this case, since the carrier frequency offset generated in the RF unit 1000 and the FFT window timing offset generated in the BB unit 1001 are generated by the same offset of the reference oscillator 10000, the oscillation frequency offset of the reference oscillator is detected from the detected carrier frequency offset. A clock offset can be detected from the detected oscillation frequency offset of the reference oscillator, an FFT window timing offset can be detected from the detected clock offset, and the FFT window timing offset can be corrected from the detected FFT window timing offset. First, the relationship between the carrier frequency offset and the oscillation frequency offset of the reference oscillator will be described.
[0022]
Equation (1) shown below indicates a carrier frequency offset between the transmitting and receiving apparatuses.
[0023]
(Equation 1)

[0024]
Where f _{carrieroffset} Is the carrier frequency offset between the transmitting and receiving devices, f _TxLO Is the frequency of the transmitter's local oscillator, f _RxLO Represents the frequency of the local oscillator of the receiving device.
[0025]
Equation (2) below shows the frequency offset of the reference oscillator between the transmitting and receiving devices.
[0026]
(Equation 2)

[0027]
Where f _TCXOffset Is the reference oscillation frequency offset between the transmitting and receiving devices, f _TxTCXO Is the frequency of the reference oscillator of the transmitter, f _RxTCXO Represents the frequency of the reference oscillator of the receiving device. The local oscillator compares the frequency of the output frequency of the voltage-controlled oscillator by N and the frequency of the reference oscillator, and controls the voltage of the voltage-controlled oscillator based on the comparison result. As shown in Equation (3), the ratio between the carrier frequency offset between the transmitting and receiving devices and the frequency of the local oscillator of the transmitting device, and the ratio between the reference oscillation frequency offset between the transmitting and receiving devices and the frequency of the reference oscillator of the transmitting device are equal.
[0028]
[Equation 3]

[0029]
As described above, the reference oscillation frequency offset between the transmitting and receiving apparatuses can be detected based on the detected carrier frequency offset between the transmitting and receiving apparatuses.
[0030]
Next, the relationship between the clock offset and the reference oscillation frequency offset will be described.
Equation (4) below shows a clock offset between the transmitting and receiving apparatuses.
[0031]
(Equation 4)

[0032]
Where f _clkoffset Is the clock offset between the transmitting and receiving devices, f _Txclk Is the clock frequency for controlling the BB section of the transmitting device, f _Rxclk Represents a clock frequency for controlling the BB unit of the receiving device. Since the clock frequency for controlling the BB unit is generated by the reference oscillator, as shown in the following equation (5), the ratio between the clock offset between the transmitting and receiving devices and the clock frequency for controlling the BB unit of the transmitting device and the transmitting and receiving device The ratio between the reference oscillation frequency offset and the frequency of the reference oscillator frequency of the transmission device can be expressed as equal.
[0033]
(Equation 5)

[0034]
As described above, based on the detected reference oscillation frequency offset between the transmitting and receiving apparatuses, the clock offset between the transmitting and receiving apparatuses can be detected. From the above equations (3) and (5), the relationship between the carrier frequency offset and the clock offset can be expressed as the following equation (6).
[0035]
(Equation 6)

[0036]
Using the above equation (6), the clock offset detector 110 calculates a clock offset corresponding to the oscillation frequency of the local oscillator 100 based on the carrier frequency offset output from the frequency offset detector 104.
[0037]
Next, the relationship between the FFT window timing offset and the clock offset will be described. In the OFDM communication system according to the present embodiment, based on the synchronization information detected from the symbol at the head of the packet signal, the FFT window timing is set with a fixed timing interval for each subsequent symbol for each subsequent data symbol. Therefore, the FFT window timing offset increases in proportion to the time interval from the symbol at the head of the packet signal where the synchronization information is detected. Since the BB section is controlled by the clock, as shown in the following equation (7), the ratio of the time interval from the symbol of the packet signal head of the data symbol to be subjected to the FFT processing in the FFT section to the FFT window timing offset is obtained. It can be expressed that the ratio between the clock offset between the transmitting and receiving apparatuses and the clock frequency for controlling the BB unit of the transmitting apparatus is equal.
[0038]
(Equation 7)

[0039]
Here, Δt represents an FFT window timing offset, and T represents a time interval from a symbol at the head of a packet signal of a data symbol to be subjected to FFT processing in the FFT unit. As described above, the FFT window timing offset between the transmitting and receiving apparatuses can be detected for each data symbol based on the detected clock offset between the transmitting and receiving apparatuses. Using the above equation (7), the phase difference detection unit 111 calculates the clock offset output from the clock offset detection unit 110 and the time interval between the symbol of the packet signal head and the data symbol output from the system control unit 109. Based on this, an FFT window timing offset is calculated.
[0040]
Next, the relationship between the phase difference between the symbol at the head of the packet signal and the data symbol and the FFT timing offset will be described. According to the following equation (8), the time waveform of the symbol at the head of the packet signal input to the FFT unit is represented by the following equation (9). Can be shown.
[0041]
(Equation 8)

[0042]
(Equation 9)

[0043]
Where a _k Is the I-phase signal point arrangement, bk is the Q-phase signal point arrangement, N is the number of subcarriers, f _k Represents a subcarrier frequency, and t represents time.
[0044]
FIGS. 15A and 15B are explanatory diagrams showing the phase difference between the symbol at the head of the packet signal and the data symbol for each subcarrier. As an example, a signal point arrangement of QPSK (Quadrature Phase Shift Keying) is used. Here, a white point is a signal point arrangement when there is no FFT window timing offset, and a black point is a signal point arrangement when there is an FFT window timing offset. In addition, k → low in FIG. 15A indicates a subcarrier having a low frequency, and k → high in FIG. 15B indicates a subcarrier having a high frequency.
[0045]
When the FFT window timing offset occurs, the data symbol and the phase difference θ without the FFT window timing offset _k Occurs. This phase difference θ _k Indicates an initial phase shift from the symbol at the head of the packet signal. Phase difference θ for each subcarrier _k Can be expressed as the following equation (11) from the following equation (10) obtained by expanding the above equation (9).
[0046]
(Equation 10)

[0047]
(Equation 11)

[0048]
As shown in the above equation (11), the phase difference increases as the subcarrier frequency increases. Using the above equations (7) and (11), the phase difference detection section 111 calculates a phase difference according to the subcarrier frequency based on the calculated FFT window timing offset. The phase difference correction unit 112 calculates the amount of phase rotation for each subcarrier of the data symbol after the FFT processing based on the phase difference output from the phase difference detection unit 111. Expression (12) shown below is an expression obtained by expanding expression (10). Note that θ _k = 2πf _k Δt is used. In the following equation (13), the following equation (12) is expressed as cos (2πf _k t) and sin (2πf) _k The equation summarized in t) is shown.
[0049]
(Equation 12)

[0050]
(Equation 13)

[0051]
The following equations (14) and (15) show the I and Q phases of the frequency waveform obtained by performing the FFT processing on the time waveform of the above equation (13). Cos (2πf) shown in the above equation (13) _k t) and sin (2πf) _k After performing the FFT processing, the coefficient of t) is output as I-phase and Q-phase data, respectively.
[0052]
[Equation 14]

[0053]
(Equation 15)

[0054]
Equation (16) below shows the rotation matrix.
(Equation 16)

[0055]
The data after the FFT processing has a phase θ as shown in the above equations (14) and (15). _k It is rotating. In the phase difference correction unit 112, as shown in the following equation (17), the matrix having the above equations (14) and (15) and the phase are θ _k The phase rotation is removed by calculating the rotation matrix of the above equation (16).
[0056]
[Equation 17]

[0057]
The following equations (18) and (19) show the I phase and the Q phase after the calculation of the above equation (17).
[0058]
(Equation 18)

[0059]
[Equation 19]

[0060]
The phase difference correction unit 112 removes the phase rotation for each subcarrier of the data symbol after the FFT processing by calculating the above equation (17), and outputs the data of the above equations (18) and (19).
[0061]
Normally, a plurality of values are set for the oscillation frequency of the local oscillator 100 within the system band. However, if the frequency difference between the different oscillation frequencies is not so large, the reference oscillator By setting the oscillation frequency to a fixed value, the circuit can be simplified and the amount of calculation can be reduced.
[0062]
In the present embodiment, the clock offset detection unit 110 calculates the above equation (6), the phase difference detection unit 111 calculates the above equations (7) and (11), and the phase difference correction unit 112 calculates the phase difference. Although the phase rotation is performed based on the phase difference output from the detection unit 111, a circuit having an expression obtained by substituting the expressions (6) and (7) into the expression (11) may be used. Alternatively, the circuit may be configured to rotate the phase as soon as the frequency offset output from the frequency offset detection unit 104 is input. That is, the clock offset detection unit 110, the phase difference detection unit 111, and the phase difference correction unit 112 can be combined to form one circuit configuration.
[0063]
Next, the circuit configuration of the receiving device of the OFDM communication system according to the first embodiment of the present invention will be described. FIG. 2 shows a circuit configuration example of the receiving device according to the present embodiment. 2, the same components as those in FIG. 1 are denoted by the same reference numerals. The operation will be described along with the operation of each block of the receiving apparatus. The signal output from the frequency offset detector 104 is the frequency offset f in the above description of the operation. _{carrieroffset} C1. In the clock offset detection unit 110, the frequency f of the local oscillator, which is the denominator term on the left side of the above equation (6), _TXLO Is stored in the ROM 1, a value corresponding to the frequency of the local oscillator to be used is output from the ROM 1, and the multiplier 2 multiplies the value by the frequency offset C1.
[0064]
FIG. 3 shows an example of values stored in the ROM 1. FIG. 3A is a schematic example of values stored in the ROM 1. In ROM1, 1 / f _TxLo Is stored. The input address is f _TxLo1 If so, ROM1 is 1 / f _TxLo1 Is output. FIG. 3B is a specific example of a value stored in the ROM 1, for example, a value corresponding to a use frequency described in “ARIB STD-T70”. The frequency used for communication is 5.170 × 10 ⁹ Hz, the address 1 is input to the ROM 1, and the ROM 1 reads 1 / 5.170 × 10 ⁹ Is output. As the output of the multiplier 2, the clock offset ratio f which is the right-hand term of the above equation (6) _clkoffset / F _TxclkC2 Is output and input to the phase difference detection unit 111 (FIG. 2). The phase difference detection unit 111 first calculates an FFT window timing offset Δt, which is a numerator of the left side of the above equation (7).
[0065]
The system control unit 109 outputs a time interval t from the known pattern of the packet signal head of the data symbol. The multiplier 3 multiplies the clock offset ratio C2 by the time interval and outputs an FFT window timing offset C3.
Next, the phase difference θ which is the term on the left side of the above equation (11) _k Is calculated. ROM4 (FIG. 2) stores 2πf which is a part of the right-hand side term of the above equation (11). _k In the multiplier 5, the FFT window timing offset C3 and 2πf for each subcarrier are stored. _k , And outputs several phase carriers C4 as subcarriers, and inputs them to the phase difference correction unit 112.
[0066]
FIG. 4 is a diagram illustrating an example of values stored in the ROM 4. FIG. 4A is an example of values stored in the ROM 4. In ROM4, 2πf _k Is stored. The input address is f ₁ Then, ROM4 is 2πf ₁ Is output. FIG. 4B is a specific example of a value stored in the ROM 4, for example, a value corresponding to the subcarrier arrangement described in “ARIB STD-T70”. Here, a case where the OFDM use frequency band is 20 MHz, the number of information subcarriers is 52, and the number of null subcarriers is 12 will be described. To output the phase difference C4 of the subcarrier having the lowest subcarrier frequency, the address 1 is input to the ROM 4, and the ROM 4 stores 2π × 312.5 × 10 ³ × (−26) is output, multiplied by the FFT window timing offset C3 in the multiplier 5, and output. To output the phase difference C4 of the subcarrier having the highest subcarrier frequency, the address 52 is input to the ROM 4, and the ROM 4 stores 2π × 312.5 × 10 ³ X26 is output, multiplied by the FFT window timing offset C3 in the multiplier 5, and output.
[0067]
The phase difference correction unit 112 removes the phase rotation of the frequency axis signal by performing a matrix operation on the rotation matrix and the frequency axis signal. The ROM 7 stores the element cos θ of the above equation (17) according to the phase, and the ROM 8 stores the element sin θ of the above equation (17) according to the phase. The controller 6 determines cos θ and sin θ to be used when performing phase rotation from the phase difference C4, and outputs corresponding addresses to the ROM 7 and ROM 8. The ROMs 7 and 8 output cos θ and sin θ according to the address input from the controller 6.
[0068]
FIG. 5 is a diagram illustrating an example of values stored in the ROM 7 and the ROM 8. The ROM 7 stores the value of cos θ. The ROM 8 stores the value of sin θ. If the input address is θ1, the ROM 7 outputs cos θ1 and the ROM 8 outputs sin θ1. FIGS. 6A and 6B are explanatory diagrams showing specific examples of values stored in the ROM 7 and the ROM 8, respectively. Here, for example, a case where the phase difference of the signal output from the phase difference detection unit 111 stores cos θ and sin θ corresponding to values of 1 °, 4 °, and 7 ° in the ROM 7 and the ROM 8 will be described. I have.
[0069]
The ROM 7 stores a value of cos 1 ° at address 1, a value of cos 4 ° at address 2, and a value of cos 7 ° at address 3. The ROM 8 stores a value of sin1 ° at address 1, a value of sin4 ° at address 2, and a value of sin7 ° at address 3. When the phase difference of the signal output from the phase difference detection unit 111 is 7 °, the controller 6 of the phase difference correction unit 112 outputs the address 3 to the ROM 7 and the ROM 8.
The ROM 7 to which the address 3 is input outputs 0.999810963, and the ROM 8 outputs 0.0194432319.
[0070]
The multiplier 10 receives cos θ at the first row and first column of the rotation matrix of the above equation (17), and the multiplier 11 receives sin θ at the second row and first column of the rotation matrix of the above equation (17). The cos θ in the second row and second column of the rotation matrix of the above equation (17) is input to the multiplier 12, and the rotation matrix of the above equation (17) in which the sign of the output of the ROM 8 is inverted by the sign inversion unit 9 is input to the multiplier 13. -Sin θ in the first row and second column is input. Further, the I-phase S5.1 of the frequency axis signal is input to the multipliers 10 and 12, and the Q-phase S5.2 of the frequency axis signal is input to the multipliers 11 and 13, and is multiplied by the input from the ROMs 7 and 8. The adder 14 adds the outputs of the multipliers 10 and 13 as shown in the above equation (18), and outputs a frequency axis signal I-phase S7.1 from which the phase rotation has been removed. The adder 15 adds the outputs of the multipliers 11 and 12 as shown in the above equation (19), and outputs a frequency axis signal Q phase S7.2 from which phase rotation has been removed. Then, the frequency axis signal from which the phase rotation has been removed by the phase difference correction unit 112 is input to the demodulation unit.
[0071]
An operation procedure of the phase difference corrector 112 of the OFDM receiver according to the first embodiment of the present invention will be described. Since the FFT window timing offset generated between one OFDM symbol is a considerably small value, the effect is small when the packet length is short, and the reception error rate characteristic deteriorates when the packet length is long. Further, in the ROM 7 and the ROM 8 in FIG. _k Cos (θ _k ) And sin (θ _k ) Cannot be stored indefinitely. Therefore, a plurality of arbitrary values are stored in the ROM 7 and the ROM 8, and when the calculated phase difference reaches an arbitrarily set value, the phase difference correction unit 112 removes the phase rotation and sets the set value. Was updated to the next value, and when the calculated phase difference reached the updated value, the difference between the phase difference set in the phase difference judgment of the current step and the phase difference set in the previous step was determined. The phase rotation is removed using the phase, and the process proceeds to the next step of determining the phase difference. Thereafter, the above procedure is performed until packet reception is completed.
[0072]
FIG. 7 is a flowchart illustrating an example of the operation of the phase difference correction unit 112 according to the first embodiment of the present invention. FIG. 7 shows an example in which the number of phase difference determinations is two, and the phase difference determination is performed on a subcarrier having the largest phase difference and the highest frequency. When the output from the phase difference detection unit 111 is input to the phase difference correction unit 112, in step S1, the phase difference θ of the subcarrier having the highest frequency among the outputs from the phase difference detection unit 111 _max Is positive or negative. When the determination result is YES in step S1, the process proceeds to step S2L, and when the determination result is NO, the process proceeds to step S2S. If the process proceeds to step S2L, the phase difference θ _max Is a phase difference θ arbitrarily set in advance. _s1 Is performed to determine whether or not the difference has reached the threshold value.
[0073]
In step S2L, when the determination result is YES, the process proceeds to step S3L, and when the determination result is NO, a signal is output. If the process proceeds to step S3L, the phase θ used for determining the phase difference of the subcarrier having the highest frequency _s1 , The phase rotation is removed using the phase rotation amount of each subcarrier corresponding to, and the process proceeds to step S4L. The phase difference θ arbitrarily set in step S4L _s2 Is performed to determine whether or not the difference has reached the threshold value. In step S4L, if the determination result is YES, the process proceeds to step S5L, and if the determination result is NO, a signal is output. When the process proceeds to step S5L, the phase difference θ set in step S5L _s2 And the phase difference θ set in step S3L _s1 Difference (θ _s2 ―Θ _s1 ), The phase rotation is removed using the phase rotation amount of each subcarrier, and a signal is output. If the process proceeds to step S2S, the phase difference θ _max Is a phase difference θ arbitrarily set in advance. _s3 Is performed to determine whether or not the difference has reached the threshold value. When the determination result is YES in step S2S, the process proceeds to step S3S, and when the determination result is NO, a signal is output. When the process proceeds to step S3S, the phase θ used for the phase difference determination of the subcarrier having the highest frequency _s3 The phase rotation is removed by using the phase rotation amount of each subcarrier corresponding to, and the process proceeds to step S4S. The phase difference θ arbitrarily set in advance in step S4S _s4 Is performed to determine whether or not the difference has reached the threshold value. If the determination result in step S4S is YES, the process proceeds to step S5S, and if the determination result is NO, a signal is output.
[0074]
If the process proceeds to step S5S, the phase difference θ set in step S5S _s4 And the phase difference θ set in step S3S _s4 Difference (θ _s4 ―Θ _s3 ), The phase rotation is removed using the phase rotation amount of each subcarrier, and a signal is output.
[0075]
When the phase difference correction unit 112 determines whether or not the phase difference output from the phase difference detection unit 111 is equal to or larger than a arbitrarily set phase difference, the determination is not performed for one subcarrier. Can be determined in the sub-carriers. In this case, the determination can be made based on the average value, the maximum value, or the minimum value, or the intermediate value between the maximum value and the minimum value of the determination in a plurality of subcarriers.
[0076]
Further, in a subcarrier having a low subcarrier frequency, the phase difference caused by the FFT window timing offset is small, so that the operation of removing the phase rotation can be omitted. Further, instead of controlling the operation by the phase difference in the phase difference correction unit 112, the operation can be controlled by the frequency offset, clock offset, and FFT window timing offset output in each block in FIG.
[0077]
Next, an OFDM receiver according to a second embodiment of the present invention will be described. In the ROM 7 and the ROM 8 in FIG. _k Cos (θ _k ) And sin (θ _k ) Leads to an increase in circuit scale. An operation procedure of the phase difference corrector 112 of the OFDM receiver according to the second embodiment of the present invention will be described. When the calculated phase difference is equal to or greater than a predetermined value, the OFDM receiver according to the second embodiment of the present invention removes the phase rotation using a previously arbitrarily set phase as a parameter. By outputting when the phase difference of the signal becomes equal to or less than a predetermined value, the cos (θ _k ) And sin (θ _k ) Is stored for one set of subcarriers, thereby reducing the circuit scale.
[0078]
FIG. 8 is a flowchart illustrating an example of the operation of the phase difference correction unit 112 according to the second embodiment of the present invention. FIG. 8 shows a case where the phase difference determination is performed on a subcarrier having the largest phase difference and the highest frequency. When the output from the phase difference detection unit 111 is input to the phase difference correction unit 112, in step S11, the phase difference θ of the subcarrier having the highest frequency among the outputs from the phase difference detection unit 111 _max Is positive or negative. In step S11, when the result of the determination is YES, the process proceeds to step S12L, and when the result of the determination is NO, the process proceeds to step S12S. When the process proceeds to step S12L, the phase difference θ _max Is a phase difference θ arbitrarily set in advance. ₁ Is performed to determine whether or not the difference has reached the threshold value. In step S12L, when the determination result is YES, the process proceeds to step S13L, and when the determination result is NO, a signal is output. If the process proceeds to step S13L, the phase θ used to determine the phase difference of the subcarrier having the highest frequency ₁ The phase rotation is removed using the phase rotation amount of each subcarrier corresponding to the subcarrier, and the process proceeds to step S14L. The phase difference θ determined in step S12L in step S14L _max From θ ₁ , And subtract the resulting value from the phase difference θ. _max And returns to step S12L. Thereafter, the above steps are repeated until the result of the determination in step S12L is NO, and output.
[0079]
In FIG. 8, v is the number of repetitions of the above steps. If the process proceeds to step S12S, the phase difference θ _max Is a phase difference θ arbitrarily set in advance. _m Is performed to determine whether or not the difference has reached the threshold value. If the determination result in step S12S is YES, the process proceeds to step S13S, and if the determination result is NO, a signal is output. If the process proceeds to step S13S, the phase θ used to determine the phase difference of the subcarrier having the highest frequency _m , The phase rotation is removed using the phase rotation amount of each subcarrier corresponding to, and the process proceeds to step S14S. The phase difference θ determined in step S12S in step S14S _max To θ _m And the added value is used as the phase difference θ. _max And returns to step S12S. Thereafter, the above steps are repeated until the result of the determination in step S12S is NO, and output. In FIG. 8, w is the number of repetitions of the above steps.
[0080]
An OFDM receiver according to a third embodiment of the present invention will be described. FIG. 9 is a block diagram showing a main part of a schematic configuration of a receiving apparatus in an OFDM communication system according to a third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 9, reference numeral 113 denotes an FFT window timing offset detection unit. The function of the FFT window timing detection unit 106 is different from that according to the first embodiment of the present invention. An outline of the operation of the OFDM communication system according to the present embodiment will be described.
[0081]
The high-frequency signal S1 received by the antenna is input to the multiplier 101, multiplied and down-converted by a local oscillator output generated by the reference oscillator 10000, and a baseband signal S2 is output. The baseband signal S2 is input to an A / D converter 102 of a BB (Base Band) unit 1001 in which an OFDM signal is generated by a reference oscillator 10000, and is converted from an analog signal to a digital signal to output a baseband signal S3. You. Correlation detection section 103 calculates a correlation value between the same waveforms at the beginning of the received packet signal. The carrier frequency offset is calculated by the frequency offset detection unit 104 based on the correlation value, and the FFT window timing is detected by the FFT window timing detection unit 106. Based on the carrier frequency offset calculated by the frequency offset detection unit 104, the frequency offset correction unit 105 removes the carrier frequency offset from the baseband signal S3, and outputs the baseband signal S4. Based on the carrier frequency offset calculated by frequency offset detecting section 104, clock offset detecting section 110 calculates a clock offset. Based on the clock offset calculated by the clock offset detection unit 110 and the time interval between the symbol of the packet signal head and the data symbol output from the system control unit 109, the symbol of the packet signal head is detected by the FFT window timing offset detection unit 113. FFT window timing offset between the data symbol and the data symbol is calculated.
[0082]
Based on the FFT window timing offset calculated by the FFT window timing offset detection unit 113, the FFT window timing detection unit 106 corrects the FFT window timing. Based on the FFT window timing detected and corrected by the FFT window timing detection unit 106, the FFT unit 107 performs FFT processing on the baseband signal S4, converts the time axis signal into a frequency axis signal, and converts the time axis signal into a frequency axis signal. Is output. The frequency axis signal S5 is input to the demodulation circuit 108, and the demodulation signal S6 is output. Demodulated signal S6 is input to system control section 109. Hereinafter, the operation of each block of the receiving apparatus of the present invention will be described.
[0083]
For the symbol and data symbol at the head of the packet signal, the time waveforms input to the FFT unit 107 due to the FFT window timing offset are as shown in the above equations (8) and (9). The FFT window timing offset detection unit 113 detects the FFT window timing offset Δt as in the above equation (7).
The FFT window timing detection unit 106 outputs the corrected FFT window timing to the FFT unit 7 by shifting the FFT window timing by Δt. The FFT unit 7 sets an FFT window for the data symbol using the corrected FFT window timing. Conventionally, the FFT processing is performed on the time waveform as shown in the above equation (9), but the FFT processing is performed at the FFT window timing that results in the time waveform as shown in the above equation (8). The phase difference between the symbol and the data symbol is removed.
[0084]
A circuit configuration of the receiving device of the OFDM communication system according to the third embodiment of the present invention will be described. FIG. 10 shows an example of a circuit configuration of a block of the receiving device according to the third embodiment of the present invention. The same components as those in FIGS. 9 and 2 are denoted by the same reference numerals. Description will be made with reference to the description of the operation of each block of the receiving apparatus according to the first embodiment of the present invention.
[0085]
The signal output from the frequency offset detector 104 is the frequency offset f in the above description of the operation. _{carrieroffset} C1. In the clock offset detector 110, the reciprocal of the frequency of the local oscillator, which is the denominator on the left side of the above equation (6), is stored in the ROM1, and a value corresponding to the frequency of the local oscillator to be used is output from the ROM1. , Multiplier 2 multiplies the frequency offset C1. As the output of the multiplier 2, the clock offset ratio f which is the right-hand term of the above equation (6) _clkoffset / F _Txclk C2 is output and input to the FFT window timing offset detection unit 113. The FFT window timing offset detection unit 113 calculates an FFT window timing offset Δt, which is a numerator of the left side of the above equation (7). The system control unit 109 outputs a time interval t from the known pattern of the packet signal head of the data symbol. The multiplier 3 multiplies the clock offset ratio C2 by the time interval, outputs an FFT window timing offset C3, and inputs the FFT window timing offset C3 to the FFT window timing detection unit 106. The FFT window timing detecting section 106 corrects the FFT window timing based on the FFT window timing offset C3 output from the FFT window timing offset detecting section 113.
[0086]
As described above, according to the OFDM receiving apparatus according to each embodiment of the present invention, it is possible to reduce the deterioration of the error rate of the received signal due to the FFT window timing offset, and it is possible to transmit and receive at once while maintaining good communication quality. Packet length can be increased. Further, by extending the conventional frequency offset detection circuit and adopting a circuit configuration for correcting the FFT timing offset, it is possible to avoid a significant circuit change and an increase in circuit scale.
[0087]
As described above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to these. It will be apparent to those skilled in the art that various other modifications, improvements, and combinations are possible. For example, in the technology of generating the frequency of the local oscillator and generating the OFDM signal based on one reference oscillator, the technique is not necessarily limited to the case where only one reference oscillator is used. As long as the synchronization is achieved, a technique using two or more oscillators is also included.
[0088]
【The invention's effect】
According to the present invention, it is possible to reduce the deterioration of the error rate of a received signal due to the FFT window timing offset, and to increase the packet length that can be transmitted and received at one time while maintaining good communication quality. Further, by extending the conventional frequency offset detection circuit and adopting a circuit configuration for correcting the FFT timing offset, it is possible to avoid a significant circuit change and an increase in circuit scale.
[Brief description of the drawings]
FIG. 1 is a principal block diagram illustrating a schematic configuration of a receiving device of an OFDM communication system according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a circuit configuration example of a block of the receiving device according to the first embodiment of the present invention.
FIG. 3 is an explanatory diagram showing an example of values stored in a ROM 1 of a phase difference correction unit of the receiving device of the present invention.
FIG. 4 is an explanatory diagram showing an example of values stored in a ROM 4 of a phase difference correction unit of the receiving device of the present invention.
FIG. 5 is an explanatory diagram showing a schematic example of values stored in ROM 7 and ROM 8 of a phase difference correction unit of the receiving device of the present invention.
FIG. 6 is an explanatory diagram showing a specific example of values stored in ROM 7 and ROM 8 of the phase difference correction unit of the receiving device of the present invention.
FIG. 7 is a flowchart illustrating an operation of a phase difference correction unit according to the first embodiment of the present invention.
FIG. 8 is a flowchart illustrating an operation of a phase difference correction unit according to the second embodiment of the present invention.
FIG. 9 is a principal block diagram illustrating a schematic configuration of a receiving device of an OFDM communication system according to a third embodiment of the present invention.
FIG. 10 is a diagram illustrating an example of a circuit configuration of a block of a receiving device according to a third embodiment of the present invention.
FIG. 11 is a schematic diagram illustrating an example of a packet format of a conventional OFDM communication system.
FIG. 12 is an operation explanatory diagram showing propagation path fluctuation compensation of a received signal.
FIG. 13 is an explanatory diagram showing a relationship between a data symbol position in a packet, an offset of FFT window timing, and a data symbol phase difference.
FIG. 14 is a main block diagram schematically showing an operation of a reference oscillator of a system assumed in the present invention.
FIG. 15 is an explanatory diagram showing phases detected by FFT processing of a symbol and a data symbol at the beginning of a packet signal.
FIG. 16 is a main block diagram showing a schematic configuration of a receiving device of a conventional OFDM communication system.
[Explanation of symbols]
S1: High frequency signal
S2: Analog baseband signal
S3: Digital baseband signal
S4: frequency offset removed baseband signal
S5: frequency baseband signal
S5.1: Frequency axis baseband signal I phase
S5.2: Q-phase baseband signal Q-phase
S6: Demodulated signal
S7: Frequency axis signal after phase difference removal
S7.1: I phase of frequency axis signal after phase difference removal
S7.2: Q phase of frequency axis signal after phase difference removal
C1: frequency offset
C2: Clock offset ratio
C3: FFT window timing offset
C4: phase difference
1, 4, 7, 8: ROM
2, 3, 5, 10, 11, 12, 13: Multiplier
6: Controller
9: sign inversion unit
14, 15: adder
100: Local oscillator
101: Multiplier
102: A / D converter
103: Correlation detection unit
104: frequency offset detector
105: frequency offset correction unit
106: FFT window timing detection unit
107: FFT section
108: demodulation unit
109: System control unit
110: Clock offset detector
111: phase difference detection unit
112: phase difference correction unit
113: FFT window timing offset detector
1000: RF section
1001: BB section

Claims (20)

In an OFDM receiver that generates a local oscillator frequency and an OFDM signal based on one reference oscillator,
Clock offset calculating means for calculating a clock offset from the offset of the reference oscillator,
FFT window timing offset calculating means for calculating an FFT window timing offset based on the clock offset calculated by the clock offset calculating means;
An OFDM receiver comprising: FFT window timing adjustment means for adjusting the setting of FFT window timing based on the FFT window timing offset calculated by the FFT window timing offset calculation means. In an OFDM receiver that performs frequency generation of a local oscillator and OFDM signal generation based on one reference oscillator,
Clock offset calculating means for calculating a clock offset from the offset of the reference oscillator,
FFT window timing offset calculating means for calculating an FFT window timing offset based on the clock offset calculated by the clock offset calculating means;
Phase difference calculating means for calculating a phase difference between the signal in the ideal state and the actual output signal of the FFT unit using the FFT window timing offset calculated by the FFT window timing offset calculating means;
An OFDM receiver comprising: a phase difference correcting unit that corrects a phase of an output signal of an FFT unit based on a phase difference of a signal calculated by the phase difference calculating unit. As a calculation means of the reference oscillator offset,
Frequency offset detection means for detecting the frequency offset of the local oscillator,
3. The OFDM receiver according to claim 1, further comprising a reference oscillator offset calculating unit that calculates an offset of the reference oscillator using a frequency offset of the local oscillator detected by the frequency offset detecting unit. . As a calculation means of the reference oscillator offset,
3. The OFDM according to claim 1, further comprising: a unit that calculates an offset of the reference oscillator using a value in which the frequency of the local oscillator is fixed and a detected frequency offset of the local oscillator. Receiving machine. As a calculation means of the reference oscillator offset,
The apparatus according to claim 1, further comprising: a unit that calculates an offset of the reference oscillator based on a value of a frequency of the local oscillator used at the time of receiving the OFDM signal and a detected frequency offset of the local oscillator. 3. The OFDM receiver according to 2. As the FFT window timing offset means,
3. The OFDM receiver according to claim 1, further comprising means for calculating an FFT window timing offset based on a symbol interval, which is time interval information of a data signal from a known signal, and a clock offset. Machine. As the phase difference correction means,
When the absolute value of the phase difference of the signal calculated by the phase difference calculating means exceeds a set determination value, the phase difference of the signal is corrected by using the set phase difference of the signal. An OFDM receiver according to claim 2. As the phase difference correction means,
Means for calculating the number of corrections of the phase difference of the signal using the absolute value of the phase difference of the signal calculated in the phase difference calculation means,
3. The OFDM receiver according to claim 2, further comprising: means for correcting a phase of a repetitive signal using a correction value of a phase difference of a fixed signal based on the number of times of correction of the phase difference. In an OFDM receiver that generates a local oscillator frequency and an OFDM signal based on one reference oscillator,
A clock offset calculation procedure for calculating a clock offset from the offset of the reference oscillator,
An FFT window timing offset calculating procedure for calculating an FFT window timing offset based on the clock offset;
An FFT window timing adjustment procedure for adjusting the setting of the FFT window timing based on the calculated FFT window timing offset. In an OFDM receiver that generates a frequency generation OFDM signal of a local oscillator based on one reference oscillator,
A clock offset calculation procedure for calculating a clock offset from the offset of the reference oscillator,
An FFT window timing offset calculation procedure for calculating an FFT window timing offset based on the clock offset;
A phase difference calculation procedure for calculating a phase difference between the signal in the ideal state and the actual output signal of the FFT unit using the calculated FFT window timing offset;
A phase difference correcting procedure for correcting the phase of the output signal of the FFT unit using the calculated phase difference of the signal. As a method of calculating the reference oscillator offset,
10. A frequency offset detecting procedure for detecting a frequency offset of the local oscillator, and a reference oscillator offset calculating procedure for calculating an offset of the reference oscillator using the detected frequency offset of the local oscillator. Or the OFDM demodulation method according to 10. As a reference oscillator offset calculation procedure,
11. The OFDM demodulation method according to claim 9, further comprising a step of calculating an offset of a reference oscillator by using a value in which a frequency of the local oscillator is fixed and a frequency offset of the detected local oscillator. . As a reference oscillator offset calculation procedure,
11. The method according to claim 9, further comprising calculating an offset of a reference oscillator using a value of a frequency of the local oscillator used at the time of receiving the OFDM signal and a detected frequency offset of the local oscillator. OFDM demodulation method. 10. The FFT window timing offset procedure comprising a step of calculating an FFT window timing offset using a symbol interval, which is time interval information between a known signal and a data signal, and a clock offset. The OFDM demodulation method according to claim 10. As the phase difference correction procedure,
11. The method according to claim 10, further comprising the step of correcting the phase of the signal with the phase difference of the set signal when the absolute value of the phase difference of the signal calculated in the phase difference calculation procedure exceeds a set determination value. The OFDM demodulation method according to the above. As the phase difference correction procedure, a procedure of calculating the number of corrections of the phase difference of the signal using the absolute value of the phase difference of the signal calculated in the phase difference calculation procedure,
11. The OFDM demodulation method according to claim 10, further comprising: a step of correcting the phase of the repetitive signal using a correction value of the phase difference of the fixed signal based on the number of times of correction of the phase difference. As the phase difference correction procedure,
In the phase difference for each subcarrier calculated in the phase difference calculation procedure, by using the subcarrier having the largest absolute value of the subcarrier frequency, it is determined whether the set determination value has been reached. The OFDM demodulation method according to claim 10, wherein 18. Software for causing a computer to execute the procedure according to any one of claims 9 to 17. A computer-readable information recording medium on which is recorded software for causing a computer to execute the procedure according to any one of claims 9 to 17. An OFDM receiver comprising a recording unit that records a procedure for executing the procedure according to any one of claims 9 to 17.

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