JP2004312033A - Method of manufacturing single crystal silicon wafer and single crystal silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance gettering effect and flatness in a single crystal silicon wafer having an extrinsic gettering layer by polysilicon. <P>SOLUTION: Figures 1 (a)-(c) indicate slice, wrapping, and etching of an oxide film of the single crystal silicon. In Fig.(d), a rear surface of a wafer 1 is ground to high flatness. As shown in Fig.(e), a polysilicon layer 3 is formed using a CVD equipment in the condition with mechanical deformation in the rear surface by the grinding process. In Fig.(f), the surface side of the wafer is subjected to mirror-finished surface polishing with super low stock removal so as to be made into haze free mirror-finished surface. Since a mechanical deformation layer 2 and a deformation layer by polysilicon are formed in a form of double gettering site, the gettering effect becomes higher than conventional method, and the duration of the effect is increased. At the same time, since flatness of the wafer is improved by the surface grinding, high planarization of the wafer after mirror-finished polishing can be realized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a single crystal silicon wafer having an extrinsic gettering site.

  In recent years, in order to cope with higher integration of semiconductor elements, higher quality of semiconductor substrates has been required. In a single crystal silicon wafer generally used as the semiconductor substrate, as a means for removing defects, impurities, and the like induced during a device process from an active region in which a device is formed, intrinsic gettering (hereinafter referred to as IG) is used. ) And extrinsic gettering (hereinafter referred to as EG). IG is a method in which a single crystal silicon wafer is subjected to a predetermined heat treatment to form a bulk minute defect inside the wafer, and is used as a trapping point for heavy metal impurities or point defects that enter the wafer in a device process. . On the other hand, typical methods of EG include a method in which mechanical strain such as backside damage is intentionally applied to the back surface of a single-crystal silicon wafer to serve as a trapping base for contamination impurities and point defects, and a method in which a polysilicon layer is used. There is a method of forming a strain layer on the back surface of a wafer.

  A conventional processing process for providing an EG layer of polysilicon on the back surface of a single crystal silicon wafer is as shown in FIG. That is, as shown in FIG. 3 (a), a single crystal silicon ingot is sliced into a wafer 1 free of processing strain, chamfered if necessary, and then wrapped in FIG. 3 (b). 3 (c), the oxide film is etched. Next, in FIG. 3D, the polysilicon layer 3 is formed by subjecting the wafer 1 to a CVD process or the like to form a strained layer. In FIG. 3E, the surface of the wafer 1 is mirror-polished, and the wafer is finally cleaned. Further, in some cases, mechanical distortion is generated by sandblasting the back surface of the wafer instead of the polysilicon coating.

  When a polysilicon layer is formed as a strained layer on the back surface of a wafer, it has been confirmed that this polysilicon layer is oriented in a direction of single crystallization in a high-temperature region such as a well diffusion heat treatment in a device process. Further, gettering sites are reduced in the process of the single crystallization, so that the gettering effect is reduced. This is also apparent from the high bulk contamination measured after the wafer was intentionally contaminated with Fe. Further, in a conventional processing process for providing an EG layer, single crystal silicon is sliced, lapping is performed, etching is performed so as not to lose its shape, and a predetermined flatness is formed by a mirror polishing process. After the etching, the wafer surface is not flattened before the mirror polishing step. And, since the TTV (total thickness variation) of the etched wafer is about 3 μm or more, the load at the time of mirror polishing is large, and the yield to the high flatness standard is poor. Furthermore, since the TTV of the etched wafer is large, the polishing allowance in the mirror polishing step is increased, which is a factor of deteriorating the flatness.

  The present invention has been made in view of the above-described conventional problems. In a single crystal silicon wafer having an EG layer made of polysilicon, a single crystal silicon wafer capable of improving both the gettering effect and the flatness is provided. It is intended to provide a manufacturing method.

  In order to achieve the above object, a method for manufacturing a single crystal silicon wafer according to the present invention is to form a polysilicon layer on the rear surface of the single crystal silicon wafer after surface grinding and applying a mechanical strain layer to the rear surface. In the surface grinding of a single crystal silicon wafer, the surface of the wafer is sucked on a flat plate having a predetermined flatness, and the back surface of the wafer is ground. Further, the single crystal silicon wafer according to the present invention is characterized in that a mechanically strained layer and a strained layer made of polysilicon are provided on the back surface of the wafer as an extrinsic gettering site.

  In the method of manufacturing a single-crystal silicon wafer configured as described above, a mechanically strained layer formed by surface grinding and a strained layer formed by coating with polysilicon are applied together to the back surface of the wafer. The gettering effect of the wafer can be higher than that of the conventional wafer, and the sustainability of the gettering effect is improved. In addition, the flatness of the wafer is improved by performing an order of magnitude higher than that of sandblasting, thereby improving the flatness of the wafer. Can be realized.

  Hereinafter, embodiments of the method for manufacturing a single crystal silicon wafer according to the present invention will be described with reference to the drawings. FIG. 1 is an explanatory view of a manufacturing process of a single-crystal silicon wafer according to the present invention. As shown in FIG. 1A, a single-crystal silicon ingot is sliced into a wafer 1 and, if necessary, chamfered. 2B, both surfaces of the wafer 1 are wrapped, and the oxide film is etched in FIG. 1C. The steps so far are the same as the conventional manufacturing process. Next, as shown in FIG. 1 (d), a surface grinder to which a surface of the wafer 1 finished without processing distortion is strongly attracted to a flat plate having a predetermined flatness and a diamond grindstone is attached. Then, the back surface of the wafer 1 is ground to a high flatness. By this grinding, a mechanical strain layer 2 is provided on the back surface of the wafer 1. In this state, when the polysilicon layer 3 is formed using a CVD apparatus as shown in FIG. 1E, the mechanically strained layer 2 formed by the surface grinding and the strained layer formed by the formation of the polysilicon layer 3 form the wafer 1. It is provided by being laminated on the back surface. Thereafter, mirror polishing with an ultra-low allowance is performed so that the surface of the wafer 1 becomes a haze-free mirror surface in FIG. Mirror polishing with an extremely low allowance is made possible by grinding the back surface of the wafer 1 to a high flatness. Finally, the wafer is cleaned.

  FIG. 2 is a diagram showing the results of observing a cross section near the back surface of a silicon wafer (before CMOS heat treatment) manufactured as an experimental example of the method for manufacturing a single crystal silicon wafer according to the present invention by a transmission electron microscope. Using a 6-inch FZ wafer as an experimental example, lapping and etching were performed according to the above manufacturing process, and then surface grinding was performed with a # 2000 diamond grindstone to provide a mechanical strain layer 2 as shown in FIG. This wafer was subjected to reduced pressure CVD with monosilane gas at 650 ° C. to form a polysilicon layer 3 having a thickness of about 1 μm, and then the wafer surface was mirror-polished. The surface of the FZ wafer thus treated was intentionally contaminated with Fe at 10 13 atoms / cm 2, subjected to a diffusion heat treatment at 1000 ° C. for 1 hour, and the Fe concentration was measured by the SPV method. The results are as shown in Table 1. The double gettering sites of the mechanical strain caused by the surface grinding using the diamond grindstone and the strain caused by the polysilicon coating were formed on the wafer of this experimental example. The effect is great, and the Fe concentration in the bulk is lower than that of the conventional EG wafer. Also, this wafer has a long gettering effect duration.

  Table 2 is a table comparing the TTV after mirror polishing between the case where the EG treatment was performed by the conventional method and the present experimental example using an 8-inch CZ wafer. However, for the wafer according to this experimental example, the measured value is after the CMOS heat treatment. It can be seen that the average value, variation and maximum value of the TTV are reduced to about 1/3 of the conventional value. Table 3 is a table comparing the dust generation of the wafer according to this experimental example with an etched wafer and a conventional EG wafer. This table shows the results of the first measurement performed after the final cleaning of the wafer and the results of the second measurement performed after cleaning with the SC-1 cleaning solution (NH4 OH + H2 O2) for the number of particles having a particle diameter of 0.2 μm or more. This shows the difference from. Although the wafer according to the present experimental example has mechanical distortion, the dusting property is not different from the conventional EG wafer.

  In this embodiment, the back surface of the etched silicon wafer is subjected to surface grinding and polysilicon coating. However, as an application example, a gettering site may be formed on the back surface of the wafer only by surface grinding.

It is explanatory drawing of the manufacturing process of the single crystal silicon wafer which has an EG layer. FIG. 3 is a diagram showing a result of observing a cross section near the back surface of a single crystal silicon wafer having an EG layer with a transmission electron microscope. It is explanatory drawing of the conventional manufacturing process of the single crystal silicon wafer which has the EG layer by polysilicon. As described above, the present invention forms a polysilicon layer after performing high-flatness surface grinding on an etched wafer to form a mechanically strained layer on the back surface of the wafer and improve flatness, and then forming a polysilicon layer. is there. As a result, the mechanical strain layer and the polysilicon strain layer are formed in the form of double gettering sites as the EG layer, so that the gettering effect is higher than before and the sustainability of the gettering effect is improved. I do. At the same time, since the flatness of the wafer is improved by the surface grinding, it is possible to realize a high flatness of the wafer after mirror polishing. Further, this wafer has the effect of covering the surface ground surface with polysilicon despite having a mechanical strain layer on the back surface, and thus has an advantage that generation of particles is small.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Wafer 2 Mechanical strain layer 3 Polysilicon layer

Claims (3)

A method for manufacturing a single-crystal silicon wafer, comprising: forming a polysilicon layer on the rear surface of a single-crystal silicon wafer in a state where a rear surface of the single-crystal silicon wafer is ground to provide a mechanical strain layer. The surface of the single crystal silicon wafer according to claim 1, wherein the surface of the single crystal silicon wafer is ground on a flat plate having a predetermined flatness, and then the surface of the wafer is ground. Production method. A single crystal silicon wafer comprising a mechanically strained layer on the back surface of the wafer and a strained layer covered with polysilicon.

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