JP2004304333A - Oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit which oscillates at a desired frequency regardless of surrounding states and provides a stable oscillation frequency with a satisfactory response. <P>SOLUTION: The oscillation circuit has an oscillation means (11) for oscillating in a frequency matching the control voltage, a compensation means (12) for generating a compensation signal for compensating the control voltage so that the oscillation frequency of the oscillation means becomes a prescribed frequency and a holding means (13) for holding the compensation signal generated by the compensation means at the prescribed frequency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an oscillation circuit, and more particularly, to an oscillation circuit that oscillates at a desired frequency regardless of surrounding conditions.
[0002]
[Prior art]
In recent years, the frequency band of usable radio waves has been narrowed with the development of communication technology. For this reason, high precision is required for the frequency of the oscillation output of the oscillation circuit mounted on the communication device or the like. However, a vibrator used in an oscillation circuit has a so-called temperature characteristic in which the characteristic of vibration changes according to temperature.
[0003]
For this reason, in the oscillation circuit, correction is performed so that the oscillation frequency does not change due to the change in the oscillation frequency of the vibrator (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP-A-10-290118 (FIG. 1, paragraphs 0040 to 0054)
[0005]
[Problems to be solved by the invention]
However, in the conventional oscillation circuit, the output analog signal of the temperature sensor is converted into digital data, and the converted digital data is subjected to arithmetic processing to remove noise and the like, so that the circuit configuration becomes complicated. With it, it becomes expensive. In addition, since the arithmetic processing is performed, there is a problem that a response to a rise at the time of startup is poor, and further, it is not possible to rapidly respond to a sudden change in an analog signal from a sensor.
[0006]
In addition, if control is directly performed using analog signals without converting to digital data, frequency fluctuations due to voltage noise cannot be ignored, and this is not suitable for high precision.
[0007]
The present invention has been made in view of the above points, and has as its object to provide an oscillation circuit capable of obtaining a stable oscillation frequency in a state of good responsiveness.
[0008]
[Means for Solving the Problems]
The present invention provides an oscillating means (11) oscillating at a frequency corresponding to a control voltage, and a correcting means for generating a correction signal for correcting the control voltage so that the oscillating frequency of the oscillating means (11) becomes a predetermined frequency. (12) The sample and hold of the correction signal generated by the correction unit (12) are sequentially performed at different timings at a frequency corresponding to the oscillation frequency corresponding to the oscillation unit (11), and a plurality of sample-hold outputs are synthesized. And a sample-and-hold means (13) for outputting as a control voltage.
[0009]
According to the present invention, the sample-and-hold means (13) sequentially samples and holds at a different timing at a frequency corresponding to the oscillation frequency corresponding to the oscillating means (11), synthesizes a plurality of sample-hold outputs, and generates a control voltage. By outputting, it is possible to obtain an output that is averaged in a predetermined cycle and has reduced noise.
[0010]
Further, according to the present invention, by simultaneously charging all the hold capacitors provided in each of the plurality of sample and hold circuits at the time of startup, the oscillation output can be controlled in accordance with the correction signal immediately after the startup of the oscillation unit. At the time of startup, the oscillation frequency can be quickly set to a desired frequency.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a circuit configuration diagram of an embodiment of the present invention.
[0012]
The oscillating circuit 1 of this embodiment is configured to include a voltage controlled oscillating circuit 11, a correction circuit 12, and a sample and hold circuit unit 13.
[0013]
The voltage-controlled oscillation circuit 11 is configured by, for example, a voltage-controlled crystal oscillation circuit, and has a configuration in which the output oscillation frequency changes according to the control voltage.
[0014]
FIG. 2 shows an example of a block diagram of the voltage controlled oscillation circuit 11.
[0015]
The voltage controlled oscillation circuit 11 includes an oscillator 21, an inverter 22, a feedback resistor Rf, DC cut capacitors C1, C2, variable capacitance diodes Cv1, Cv2, and a buffer amplifier 23.
[0016]
The oscillator 21 is composed of, for example, a crystal oscillator, and is connected to the inverter 22 in parallel. The feedback resistor Rf is connected to the inverter 22 in parallel. A variable capacitance diode Cv1 is connected to one end of a parallel circuit composed of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf via a capacitor C1 with a reverse polarity. Further, a variable capacitance diode Cv2 is connected to the other end of the parallel circuit including the crystal oscillator 21, the inverter 22, and the feedback resistor Rf via the capacitor C2 with the opposite polarity. The control voltage Vcnt is applied to the anode of the variable capacitance diode Cv1 via the input resistance Rin1, and the control voltage Vcnt is applied to the anode of the variable capacitance diode Cv2 via the input resistance Rin2. The capacitance of the variable capacitance diodes Cv1 and Cv2 changes according to the control voltage Vcnt. As a result, the capacitance component of the crystal oscillator 21 changes, and oscillation occurs at an oscillation frequency corresponding to the control voltage.
[0017]
The other end of the parallel circuit of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf is connected to the output terminal Tout via the buffer amplifier 23. The buffer amplifier 23 amplifies an oscillation signal generated at the other end of the parallel circuit of the crystal oscillator 21, the inverter 22, and the feedback resistor Rf, and supplies the amplified signal to the output terminal Tout.
[0018]
At this time, the oscillation frequency of the voltage controlled oscillation circuit 11 has a so-called temperature characteristic that changes according to the temperature. Generally, the oscillation frequency f is
f = αT ＾ 3 + βT + γ (1)
It is known to have a temperature characteristic approximated by
[0019]
The correction circuit 12 is a circuit for correcting the temperature characteristics of the oscillation frequency, reducing the temperature dependence of the oscillation frequency, and outputting a constant oscillation frequency.
[0020]
The correction circuit 12 includes a reference voltage generation circuit 31, a temperature sensor 32, a cubic function generation circuit 33, conductance amplifiers 34 to 36, and an adder 37. The reference voltage generation circuit 31 is a circuit that generates a reference voltage Vref. The γ component of equation (1) is adjusted by the reference voltage generation circuit 31.
[0021]
The temperature sensor 32 is a circuit that is driven by a reference voltage Vref that is stable with respect to the temperature generated by the reference voltage generation circuit 31 and that generates an output that is a linear function with respect to temperature. The β component of equation (1) is adjusted by the output of the temperature sensor 32.
[0022]
Further, the cubic function generating circuit 33 is a circuit that changes the output of the temperature sensor 32 into a cubic function and outputs the result. The α component of equation (1) is adjusted by the output of the cubic function generation circuit 33.
[0023]
The reference voltage Vref generated by the reference voltage generation circuit 31 is supplied to the adder 37 after gain adjustment by the conductance amplifier 34. The output of the temperature sensor 32 is supplied to an adder 37 after gain adjustment by a conductance amplifier 35. The output of the cubic function generating circuit 33 is supplied to an adder 37 after gain adjustment by a conductance amplifier 36.
[0024]
The adder 37 adds the output of the conductance amplifier 34, the output of the conductance amplifier 35, and the output of the conductance amplifier 36, and outputs the sum. The output of the adder 37 is a signal that corrects the frequency variation according to the temperature in the equation (1). The output of the adder 37 is supplied to the sample and hold circuit unit 13.
[0025]
FIG. 3 shows a block diagram of the sample-and-hold circuit unit 13.
[0026]
The sample hold circuit section 13 is a circuit for reducing low frequency noise to be removed from the correction signal supplied from the correction circuit 12 to the voltage controlled oscillation circuit 11, and includes a timing generation circuit 41 and a sample hold circuit 42. .
[0027]
FIG. 4 shows a block diagram of the timing generation circuit 41.
[0028]
The timing generation circuit 41 includes an inverter 51, an AND gate 52, a T-flip-flop 53, a counter 54, OR gates 55-1 to 55-4, and gate circuits 56-1 to 56-4. It outputs four clock signals CLK1 to CLK4 sequentially output according to the oscillation output of the circuit 11.
[0029]
The oscillation output from the voltage controlled oscillation circuit 11 is supplied to the inverter 51. Inverter 51 inverts and outputs the oscillation output from voltage controlled oscillation circuit 11. The output of the inverter 51 is supplied to an AND gate 52 and a counter 54.
[0030]
The output of the inverter 51 and the inverted output / Q of the T-flip-flop 53 are supplied to the AND gate 52. AND gate 52 outputs an AND logic of the output of inverter 51 and the inverted output / Q of T-flip-flop 53.
[0031]
The T-flip-flop 53 is reset by the power-on reset signal, and inverts the logic level when the T terminal is at a high level, and does not invert the logic level when the T terminal is at a low level. The inverted output / Q is an output obtained by inverting the output logic. The output of the T-flip-flop 53 is supplied to the AND gate 52 and the OR gates 55-1 to 55-4.
[0032]
The counter 54 is formed of a 2-bit counter, counts the output of the inverter 51, and outputs the 2-bit count value. The 2-bit output of the counter 54 is supplied to each of the gate circuits 56-1 to 56-4.
[0033]
The gate circuit 56-1 inverts the 2-bit output of the counter 54 and takes an AND logic. Therefore, the output of the gate circuit 56-1 is "1" when the output of the counter 54 is "00", and is "0" when the output of the counter 54 is any other value. The output of the gate circuit 56-1 is supplied to the OR gate 55-1. The OR gate 55-1 outputs an OR logic of the inverted output / Q of the T-flip-flop 53 and the output of the gate circuit 56-1.
[0034]
Further, the gate circuit 56-2 inverts the upper bit of the 2-bit output of the counter 54 and takes an AND logic with the lower bit. Therefore, the output of the gate circuit 56-2 becomes "1" when the 2-bit output of the counter 54 is "01", and becomes "0" when the 2-bit output is any other value. The OR gate 55-1 outputs OR logic of the inverted output / Q of the T-flip-flop 53 and the output of the gate circuit 56-2.
[0035]
Further, the gate circuit 56-3 takes an AND logic of a value obtained by inverting the upper bit and the lower bit of the 2-bit output of the counter 54. Therefore, the output of the gate circuit 56-3 becomes "1" when the 2-bit output of the counter 54 is "10", and becomes "0" when the 2-bit output is any other value. The OR gate 55-3 outputs the OR logic of the inverted output / Q of the T-flip-flop 53 and the output of the gate circuit 56-3.
[0036]
Further, the gate circuit 56-4 takes an AND logic of the upper bit and the lower bit of the 2-bit output of the counter 54. Therefore, the output of the gate circuit 56-4 becomes "1" when the 2-bit output of the counter 54 is "11", and becomes "0" when the 2-bit output is any other value. The OR gate 55-4 outputs the OR logic of the inverted output / Q of the T-flip-flop 53 and the output of the gate circuit 56-4.
[0037]
Next, the operation of the timing generation circuit 41 will be described.
[0038]
FIG. 5 is a diagram illustrating the operation of the timing generation circuit 41 at the time of startup. 5A shows the oscillation output of the voltage controlled oscillation circuit 11, FIG. 5B shows the output of the inverter 51, and FIG. 5C shows the output of the T-flip-flop 53.
[0039]
When power is turned on at time t1, T-flip-flop 53 is reset by a power-on reset signal. When the T-flip-flop 53 is reset, the inverted output / Q goes high.
[0040]
When the inverted output / Q of the T-flip-flop 53 goes high, the clock signals CLK1 to CLK4, which are the outputs of the OR gates 55-1 to 55-4, all go high.
[0041]
All the outputs of the OR gates 55-1 to 55-4 become high level. As a result, the sample and hold circuit 42 is always in a sample state, and the correction signal generated by the correction circuit 12 passes through the sample and hold circuit 42 in a substantially through state and is supplied to the voltage controlled oscillation circuit 11. Thus, the oscillation output of the voltage controlled oscillation circuit 11 can quickly reach a desired frequency.
[0042]
At time t2, the voltage controlled oscillation circuit 51 rises, and when its oscillation output exceeds the threshold value Vth, the output of the inverter 51 is inverted as shown in FIG. When the output of the inverter 51 is inverted, the output of the AND gate 52 is inverted to a high level. Since the T-flip-flop 53 is inverted, the output of the T-flip-flop 53 is inverted to a low level. When the output of the T-flip-flop 53 goes low, the output of the AND gate 52 is fixed at a low level regardless of the output level of the inverter 51. When the output of the AND gate 52 is fixed at a low level, the inverted output / Q of the T-flip-flop 53 is fixed at a low level.
[0043]
When the inverted output / Q of the T-flip-flop 53 is fixed at a low level, the OR gates 55-1 to 55-4 become equivalent to the outputs of the gate circuits 56-1 to 56-4 and are output during normal operation. Clocks CLK1 to CLK4 can be supplied to the sampling and holding circuit 41.
[0044]
FIG. 6 is a waveform diagram of the output clock during the normal operation of the timing generation circuit 41.
[0045]
During normal operation, the counter 54 counts the output of the inverter 51, that is, the oscillation output of the oscillation control circuit 11. The counter 54 counts the rise or fall of the output of the inverter 51 and outputs 2-bit data. The 2-bit data output from the counter 54 is sequentially output in the order of "00", "01", "10", and "11".
[0046]
When the 2-bit data output from the counter 54 becomes “00” at times t11, t21, and t31, the output of the gate circuit 56-1 becomes “1” or a high level, and the outputs of the gate circuits 56-2 to 56-4. Becomes "0" or low level. Thus, the clock CLK1 output from the OR gate 55-1 becomes high level, and the clocks CLK2 to CLK4 output from the OR gates 55-2 to 55-4 become low level.
[0047]
Next, when the 2-bit data output from the counter 54 becomes “01” at times t12, t22, and t32, the output of the gate circuit 56-2 becomes “1” or a high level, and the gate circuits 56-1, 56- The outputs of 3, 56-4 become "0" or low level. As a result, the clock CLK2 output from the OR gate 55-2 goes high, and the clocks CLK1, CLK3, and CLK4 output from the OR gates 55-1, 55-3, and 55-4 go low.
[0048]
Next, when the 2-bit data output from the counter 54 becomes "10" at times t13, t23, and t33, the output of the gate circuit 56-3 becomes "1" or a high level, and the gate circuits 56-1, 56-2 , 56-4 are "0" or low level. As a result, the clock CLK3 output from the OR gate 55-3 goes high, and the clocks CLK1, CLK2, CLK4 output from the OR gates 55-1, 55-2, 55-4 go low.
[0049]
Next, when the 2-bit data output from the counter 54 becomes “11” at times t14, t24, and t34, the output of the gate circuit 56-4 becomes “1” or a high level, and the gate circuits 56-1 to 56-3. Is "0" or low level. As a result, the clock CLK4 output from the OR gate 55-4 becomes high level, and the clocks CLK1 to CLK3 output from the OR gates 55-1 to 55-3 become low level.
[0050]
The clocks CLK1 to CLK4 generated by the clock generation circuit 41 are supplied to a sample and hold circuit 42.
[0051]
FIG. 7 is a circuit diagram of the sample and hold circuit 42.
[0052]
The sample and hold circuit 42 includes a first sample and hold circuit 61-1, a second sample and hold circuit 61-2, a third sample and hold circuit 61-3, and a fourth sample and hold circuit 61-4. ing.
[0053]
The first sample and hold circuit 61-1 includes an inverter INV, transistors Q1 and Q2, a hold capacitor CH, and an amplifier AMP.
[0054]
The inverter INV and the transistors Q1 and Q2 form a switch circuit. The transistors Q1 and Q2 have a CMOS structure, and have a configuration in which a back gate is connected to the input side. With such a structure, leakage current can be reduced. By reducing the leak current, the leak current is prevented from affecting as low frequency noise.
[0055]
FIG. 8 shows a cross-sectional configuration diagram of the transistors Q1 and Q2 on a semiconductor chip.
[0056]
Transistor Q1 is formed of an N-channel MOS transistor, and is formed by a CMOS process. The transistor Q1 includes a buried region 211, a source region 212, a drain region 213, a gate oxide film 214, a gate 215, a back gate region 216, and an isolation region 217 formed in the semiconductor substrate 201.
[0057]
The source region 212 is connected to the correction circuit 12 side, and receives a correction signal. The drain region 213 is connected to the hold capacitor CH, and outputs a correction signal. The back gate region 216 is connected to the correction circuit 12 side, and is configured to have the same potential as the source region 212.
[0058]
Transistor Q2 is formed of a P-channel MOS transistor, and is formed on semiconductor substrate 201 adjacent to transistor Q1. The transistor Q2 includes a well region 221 formed in the semiconductor substrate 201, a source region 222, a drain region 223 formed in the well region 221, a gate oxide film 224, a gate 225, and a back gate region 226. .
[0059]
The source region 222 is connected to the correction circuit 12 side, and receives a correction signal. The drain region 223 is connected to the hold capacitor CH, and outputs a correction signal. The back gate region 226 is connected to the correction circuit 12 side, and is configured to have the same potential as the source region 222.
[0060]
At this time, as shown in FIG. 8, the parasitic diodes D11, D12, and D13 are formed in the transistor Q1, and the parasitic diodes D21, D22, and D23 are formed in the transistor Q2. When a potential difference occurs between the correction signal and the hold capacitor CH, a leak current occurs through the parasitic diodes D11 and D21. At this time, the potential difference between the parasitic diode D11 and the parasitic diode D21 is the same, a current loop is formed by the parasitic diode D11 and the parasitic diode D21, the leak currents cancel each other, and the charge of the hold capacitor CH is not affected. .
[0061]
Therefore, it is possible to prevent the leak current from affecting the output and to prevent the leak current from acting as noise.
[0062]
In the first sample and hold circuit 61-1, the switching circuit including the inverter INV and the transistors Q1 and Q2 is controlled by the first clock CLK1. The switch circuit including the inverter INV and the transistors Q1 and Q2 is turned on when the first clock CLK1 is at a high level and turned off when the first clock CLK1 is at a low level.
[0063]
When the first clock CLK1 becomes high level and the switch circuit turns on the inverter INV and the transistors Q1 and Q2, the correction signal from the correction circuit 12 is supplied to the hold capacitor CH through the switch circuit. The hold capacitor CH is charged by the correction signal from the correction circuit 12 while the first clock CLK1 is at the high level. Further, the hold capacitor CH holds the potential charged by the correction signal during a holding period in which the first clock CLK1 is at a low level and a sampling period immediately before the holding period in which the first clock CLK1 is at a high level. The potential of the hold capacitor CH is amplified by the amplifier AMP and output through the resistor R.
[0064]
The second sample and hold circuit 61-2 has the same configuration as the first sample and hold circuit 61-2, and the switch circuit including the inverter INV and the transistors Q1 and Q2 is switched by the clock CLK2. . Thus, the correction signal is sampled when the clock CLK2 is at a high level, and is held when the clock CLK2 is at a low level.
[0065]
The third sample-and-hold circuit 61-3 has the same configuration as that of the first sample-and-hold circuit 61-2, and the switch circuit including the inverter INV and the transistors Q1 and Q2 is switched by the clock CLK3. . Thus, the correction signal is sampled when the clock CLK3 is at a high level, and is held when the clock CLK3 is at a low level.
[0066]
Further, the fourth sample and hold circuit 61-4 has a configuration similar to that of the first sample and hold circuit 61-1. The switch circuit including the inverter INV and the transistors Q1 and Q2 is switched by the clock CLK4. Thus, the correction signal is sampled when the clock CLK4 is at a high level, and is held when the clock CLK4 is at a low level.
[0067]
The outputs of the first to fourth sample hold circuits 61-1 to 61-4 are combined at the node Nout, averaged, and then supplied to the control terminal Tcnt of the voltage controlled oscillation circuit 11 as the control voltage Vcnt. You.
[0068]
According to the present embodiment, a period equal to or longer than the period of the low-frequency noise to be removed by the first to fourth sample and hold circuits 61-1 to 61-4, that is, a frequency lower than the frequency of the low-frequency noise to be removed. The noise can be reduced to １ ／ by sampling and holding at different timings and averaging.
[0069]
Further, according to the present embodiment, when the power is turned on, the clocks CLK1 to CLK4 are all controlled to the high level, so that the clocks CLK1 to CLK4 are built in the first to fourth sample and hold circuits 61-1 to 61-4. Since the hold capacitor CH can be charged quickly, the correction operation based on the correction signal can be performed at high speed, so that the oscillation output of the voltage controlled oscillation circuit 11 can be quickly set to a desired frequency.
[0070]
In the present embodiment, the output of the correction circuit 12 for performing the temperature correction is held by the hold circuit 13 at a frequency lower than the frequency of the low-frequency noise to be removed, and the low-frequency noise to be updated is removed. 12 is not limited to the temperature correction, but can be applied to a case where correction is performed by other factors.
[0071]
Further, in the present embodiment, the sample hold is performed by the four sample hold circuits of the first to fourth sample hold circuits 61-1 to 61-4, and the first to fourth sample hold circuits 61-1 to 61-1 are performed. Although the output of −4 is synthesized and averaged to obtain the control voltage of the voltage controlled oscillation circuit 11, the number of the sample and hold circuits is not limited to four, but may be two or more. For example, noise can be reduced to 1 / n or less by providing n sample and hold circuits.
[0072]
【The invention's effect】
As described above, according to the present invention, sample-and-hold means performs sample-and-hold at a frequency corresponding to the oscillation frequency corresponding to the oscillating means at sequentially different timings, combines a plurality of sample-and-hold outputs, and outputs as a control voltage. As a result, it is possible to obtain an output that is averaged in a predetermined cycle and has reduced noise.
[0073]
Further, according to the present invention, by simultaneously charging all the hold capacitors provided in each of the plurality of sample and hold circuits at the time of startup, the oscillation output can be controlled in accordance with the correction signal immediately after the startup of the oscillation unit. At the time of startup, the oscillation frequency can be quickly set to a desired frequency.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 2 is a block diagram of a voltage controlled oscillation circuit 11;
FIG. 3 is a block diagram of a sample and hold circuit unit 13;
FIG. 4 is a block diagram of a timing generation circuit 41;
FIG. 5 is an explanatory diagram of the operation of the timing generation circuit 41 at startup.
FIG. 6 is a waveform diagram of an output clock during a normal operation of the timing generation circuit 41.
FIG. 7 is a circuit configuration diagram of a sample and hold circuit 42;
FIG. 8 is a sectional configuration diagram of transistors Q1 and Q2 on a semiconductor chip.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 oscillation circuit 11 voltage controlled oscillation circuit, 12 correction circuit, 13 sample hold circuit section 21 oscillator, 22 inverter, 23 output amplifier 31 reference voltage generation circuit, 32 temperature sensor, 33 cubic function generation circuit 34, 35, 36 amplifier , 37 adder 41 sample hold circuit section, 42 timing generation circuit 51 inverter, 52 AND gate, 53 T-flip-flop 54 counter, 55-1 to 55-4 OR gate 56-1 to 56-4 gate circuit 61-1 ~ 61-4 Sample hold circuit INV Inverter, Q1, Q2 transistor, CH hold capacitor AMP amplifier, R resistor

Claims (7)

Oscillating means for oscillating at a frequency according to the control voltage;
Correction means for generating a correction signal for correcting the control voltage so that the oscillation frequency of the oscillation means is a predetermined frequency,
A sample in which the correction signal generated by the correction unit is sampled and held sequentially at different timings at a frequency corresponding to an oscillation frequency corresponding to the oscillation unit, and a plurality of sample and hold outputs are synthesized and output as the control voltage. An oscillation circuit having a holding means. A plurality of sample and hold circuits for sequentially performing sample and hold at different timings,
3. The oscillation circuit according to claim 1, further comprising: a timing generation unit configured to generate a clock for determining a timing of sample-hold of the plurality of sample-hold circuits based on an oscillation output of the oscillation unit. 3. The oscillation circuit according to claim 1, wherein the sample-and-hold unit acquires sequentially different timings for executing the sample-and-hold based on an oscillation frequency of the oscillation unit. The oscillation circuit according to claim 1, wherein the predetermined frequency is a frequency corresponding to an oscillation frequency of the oscillation unit. The oscillation circuit according to any one of claims 1 to 4, wherein the predetermined frequency is set to a frequency lower than a frequency of a noise component. 6. The oscillation circuit according to claim 1, wherein the correction unit generates a correction signal for correcting a change in an oscillation frequency of the oscillation unit according to an ambient temperature. The plurality of sample and hold circuits each have a hold capacitor,
The oscillation circuit according to any one of claims 2 to 6, further comprising a startup circuit that simultaneously charges hold capacitors of the plurality of sample and hold circuits at startup.

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