JP2004304033A - Semiconductor device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a cell structure of a DRAM for facilitating countermeasures to the fining and high integration of a design rule in recent years with the cells of the DRAM which are excellent in charge holding capability, and a method for manufacturing the semiconductor device. <P>SOLUTION: This semiconductor device comprises two trench capacitors 2a and 2b formed inside a semiconductor substrate 1, a first diffusion area 12 formed on those two trench capacitors 2a and 2b, a gate electrode 13 formed on a portion of the first diffusion area 12 and a second diffusion area 16 formed in the periphery of a gate electrode 13 on the surface of the semiconductor substrate 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a cell structure of a DRAM (Dynamic Random Access Memory) and a method of manufacturing the same.
[0002]
[Prior art]
The cell structure of the DRAM has one transistor 101 and one capacitor 102 as shown in FIG. A trench capacitor 102 formed in the depth direction of a silicon substrate 103 to increase the capacitor area, and one source / drain 104 of the transfer transistor 101 are formed adjacent to the trench capacitor 102. The gate electrode 105 of the transfer transistor 101 is connected to a word line (not shown), and the other source / drain 106 of the transfer transistor 101 is connected to a bit line 108 via a contact 107.
[0003]
However, due to recent miniaturization of design rules and high integration tendency, there has been proposed a structure in which a DRAM cell structure is formed on a trench capacitor with a vertical transfer transistor (see, for example, Patent Document 1).
[0004]
In the DRAM cell structure, since the transfer transistor is formed on the trench capacitor, the area for the transfer transistor in the cell structure of FIG. 9 can be omitted, which is effective for miniaturization and high integration.
[0005]
[Patent Document 1]
JP-A-10-313100 (FIG. 8)
[0006]
[Problems to be solved by the invention]
However, with the recent trend of miniaturization, the opening of the trench capacitor is also miniaturized. This phenomenon reduces the capacity of the trench capacitor, which leads to a decrease in the charge holding ability of the cell.
[0007]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a DRAM cell structure which is excellent in the charge holding ability of a DRAM cell and is compatible with recent miniaturization and high integration, and a method of manufacturing the same.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate, a vertical transfer transistor provided on a surface of the semiconductor substrate, wherein charge carriers move in a direction perpendicular to the surface of the semiconductor substrate, Provided is a semiconductor device including a plurality of trench capacitors provided below a transistor.
[0009]
Further, according to the present invention, a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a gate electrode formed below the first insulating film, and a side surface of the gate electrode are formed. A gate insulating film, a second diffusion region formed on the surface of the semiconductor substrate and at the periphery of the gate insulating film, a second insulating film formed below the gate electrode, A first diffusion region formed below the insulating film, and a plurality of trench capacitors formed below the diffusion region. The storage electrode of the trench capacitor is connected to the first diffusion region. A semiconductor device is provided.
[0010]
Further, in the semiconductor device, a step of forming a plurality of trench capacitors inside a semiconductor substrate, and a step of forming a trench having a size over the plurality of trench capacitors in the semiconductor substrate above the trench capacitors, Forming a first diffusion region between the trench groove and the trench capacitor; depositing an insulating film on side and bottom surfaces of the trench groove; and forming a gate insulating film on the side surface of the trench groove. Forming a gate electrode by burying a conductive film in a trench groove in which the insulating film is deposited; and forming a second diffusion region on the surface of the semiconductor substrate and at the periphery of the gate electrode. It can be manufactured by a manufacturing method of a semiconductor device provided.
[0011]
The semiconductor device may further include a step of forming a plurality of trench capacitors each having a storage electrode containing an impurity inside the semiconductor substrate, and forming the plurality of trench capacitors over the plurality of trench capacitors in the semiconductor substrate above the trench capacitors. Forming a trench groove having, and annealing the semiconductor substrate to diffuse impurities contained in a storage electrode of the trench capacitor to form a first diffusion region between the trench groove and the trench capacitor Forming an insulating film on the side and bottom surfaces of the trench groove, forming a gate insulating film on the side surface of the trench groove, and embedding a conductive film in the trench groove on which the insulating film is deposited to form a gate electrode. Forming a second diffusion region on the surface of the semiconductor substrate and at the periphery of the gate electrode It can be produced by a production method of a semiconductor device and a degree.
[0012]
According to the above solution, a plurality of trench capacitors can secure a large capacity, so that a cell having a high charge retention ability can be realized. Further, by forming the capacitor and the transfer transistor so as to overlap with each other, an increase in the cell area can be suppressed.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a sectional view of a DRAM cell showing an example of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA of the sectional view shown in FIG. FIG. 3 is a plan view of an example of the embodiment of the present invention as viewed from above.
[0014]
One DRAM cell is formed between adjacent STIs 14. This one DRAM cell includes two trench capacitors 2a and 2b formed inside a semiconductor substrate 1 and a vertical transfer transistor 20 formed on the surface of the semiconductor substrate 1 above the two trench capacitors 2a and 2b. It is composed of
[0015]
The trench capacitor includes an n − -type plate electrode 3 formed on the periphery of a trench formed in a depth direction of the semiconductor substrate, a capacitor dielectric film 4 formed on a wall of the trench, It comprises a storage electrode 5 embedded in the trench. The two trench capacitors 2a and 2b have the same configuration.
[0016]
The capacitor dielectric film 4 is made of SiN, and the storage electrode 5 is made of As (arsenic) doped polysilicon.
[0017]
The vertical transfer transistor 20 includes a gate electrode 13 formed on the surface of the semiconductor substrate 1, a second diffusion region 16 also formed on the surface of the semiconductor substrate 1 and on the periphery of the gate electrode 13, And a first diffusion region 12 formed below.
[0018]
The insulating film 11 is formed on the side surface, the bottom surface, and the upper surface of the gate electrode 13. The insulating film 11 formed on the side surface of the gate electrode 13 corresponds to the gate insulating film 11 of the vertical transfer transistor 20.
[0019]
The first diffusion region 12 formed below the gate electrode 13 is connected to the storage electrodes 5 of the two trench capacitors 2a and 2b.
[0020]
A contact 18 connected to the bit line 20 is formed on the second diffusion region 16 and the gate electrode 13. Since the insulating film 17 is formed on the upper surface of the gate electrode 13, it is not electrically connected to the contact 18, and the contact 18 is a contact 18 that connects the second diffusion region 16 and the bit line 20. is there.
[0021]
Here, the storage capacity of the capacitor increases in proportion to the total area where the storage electrode 5 and the plate electrode 3 face each other (hereinafter, referred to as “capacitor area”). Therefore, in order to increase the storage capacity of the capacitor, it is necessary to increase the area of the capacitor.
[0022]
Therefore, when the depth of the trench is the same, providing a plurality of trench capacitors even if the opening is small can increase the capacitor area and increase the storage capacity of the capacitor as compared with a single trench capacitor having a large opening. it can.
[0023]
Next, a first method for manufacturing the DRAM cell structure of the present invention will be described with reference to FIGS.
[0024]
First, as shown in FIG. 4A, a first trench groove (not shown) is formed in a semiconductor substrate 1, and a plate electrode 3 and side walls of the first trench groove are formed on the outer peripheral edge of the first trench groove. The trench capacitors 2a and 2b are formed on the bottom surface of the capacitor dielectric film 4 and the storage electrode 5 in which the first trench is buried. The capacitor dielectric film 4 is made of SiN, and the storage electrode 5 is made of As-doped polysilicon.
[0025]
Next, as shown in FIG. 4B, the polysilicon 5 doped with As is removed by CDE (Chemical Dry Etching). Subsequently, the TEOS 6 is removed to below the polysilicon 5 removed by wet etching.
[0026]
Next, as shown in FIG. 4C, a first dummy silicon oxide film 7 is deposited on the entire surface of the semiconductor substrate 1 to form a buried-nwell layer 8 and a pwell layer 9.
[0027]
Next, as shown in FIG. 5D, a second trench 10 for the gate electrode of the transfer transistor is formed by RIE (Reactive Ion Etching). Further, the first dummy silicon oxide film 7 deposited in FIG. 4C is removed with hydrofluoric acid or the like.
[0028]
Next, as shown in FIG. 5E, a first silicon oxide film 11 is deposited on the surface of the second trench 10 formed in FIG. 5D. As the semiconductor substrate 1 is annealed, As in the P-doped polysilicon used for the storage electrodes 5 of the trench capacitors 2a and 2b is diffused, and between the upper portions of the trench capacitors 2a and 2b and the second trench groove 10. Then, an n-type first diffusion region 12 is formed. Next, n + type polysilicon 13 is buried in the second trench 10 by a CVD (Chemical Vapor Deposition) method. Since extra polysilicon 13 and first silicon oxide film 11 are deposited on pwell layer 9, these are removed by CMP (Chemical Mechanical Polishing) and planarized to form gate electrode 13. . Subsequently, an STI (Shallow Trench Isolation) 14 that is separated from an adjacent element is formed.
[0029]
Next, as shown in FIG. 5F, a second dummy silicon oxide film 15 is deposited on the entire surface of the pwell layer 9. An n-type impurity is ion-implanted from the upper surface of the second dummy silicon oxide film 15 to form an n-type second diffusion region 16 on the surface of the pwell layer 9 between the gate electrode 13 and the STI 14. The second dummy silicon oxide film 15 is removed with hydrofluoric acid or the like.
[0030]
Next, as shown in FIG. 6G, after the second silicon oxide film 17 is deposited on the entire surface of the pwell layer 9, the second silicon oxide film 17 is removed by wet etching so that only the gate electrode 13 remains.
[0031]
Next, as shown in FIG. 6H, a contact 18 of the n-type second diffusion region 16 is formed. Subsequently, an interlayer insulating film 19 is deposited, and a bit line 20 is formed.
[0032]
Next, a second method for manufacturing the DRAM cell structure of the present invention will be described with reference to FIGS. The second manufacturing method is the same as the above-described first manufacturing method and the manufacturing steps shown in FIGS. 4A to 5D are omitted because they are the same.
[0033]
As shown in FIG. 7A, a first silicon oxide film 11 is deposited on the trench 10 and the pwell layer 9 shown in FIG. Next, the first silicon oxide film 11 is anisotropically etched by RIE to remove the first silicon oxide film 11 deposited on the pwell layer 9 and the bottom of the trench 10 so as to be thin. At this time, the first silicon oxide film 11 deposited on the inner wall of the trench 10 is not removed.
[0034]
Next, as shown in FIG. 7B, an n-type impurity is ion-implanted from the upper surface of the pwell layer 9. An n-type first diffusion region is formed on the lower surface of the trench groove 10, and an n-type second diffusion region 16 is formed on the upper surface of the pwell layer 9. In the first manufacturing method, the n-type first diffusion region 12 is formed by thermally diffusing As-doped polysilicon used for the storage electrode 5 of the trench capacitor 2. The concentration was low. However, since the n-type first diffusion region 12 is also ion-implanted with the n-type impurity in the second manufacturing method, the n-type first diffusion region 12 is adjusted by adjusting the concentration of the impurity ion to be implanted. Can be adjusted.
[0035]
Next, as shown in FIG. 7C, n + type polysilicon 13 is buried in the trench 10 by the CVD method. Since an extra polysilicon or silicon oxide film is deposited on the pwell layer 9, these are removed by the CMP method and flattened. Subsequently, the STI 14 is formed.
[0036]
Next, as shown in FIG. 8D, after depositing a second silicon oxide film 17 on the entire surface of the pwell layer 9, the second silicon oxide film 17 is removed by wet etching so that only the gate electrode 13 remains.
[0037]
Next, as shown in FIG. 8E, a contact 18 of the n-type second diffusion region 16 is formed. Subsequently, an interlayer insulating film 19 is deposited, and a bit line 20 is formed.
[0038]
In this way, a vertical transfer transistor can be formed on the two trench capacitors 2a and 2b.
[0039]
By using two trench capacitors 2a and 2b in one cell, the storage capacity of the cell can be increased, and the charge retention ability can be increased.
[0040]
Although two trench capacitors are formed, they are formed below the vertical transfer transistor, and do not lead to an increase in area.
[0041]
Although two trench capacitors are used in the present embodiment, the present invention is not limited to this, and three or more trench capacitors may be formed below one vertical transfer transistor.
[0042]
In the above-described embodiment, the description has been made using the n-type capacitor and the n-type transfer transistor. However, the present invention is not limited to this. For example, the first diffusion region of the p-type transfer transistor can be formed by using polysilicon doped with B (boron) for the storage electrode of the p-type trench capacitor.
[0043]
【The invention's effect】
As described in detail above, the present invention can provide a semiconductor device having a DRAM cell structure which is excellent in the charge holding ability of a DRAM cell and is compatible with recent miniaturization and high integration, and a method of manufacturing the same. .
[Brief description of the drawings]
FIG. 1 is a sectional view of a DRAM cell showing an example of an embodiment of the present invention.
FIG. 2 is a sectional view taken along line AA of FIG.
FIG. 3 is a plan view of an example of an embodiment of the present invention as viewed from above.
FIG. 4 is a sectional view showing a first method of manufacturing a DRAM cell structure according to the present invention.
FIG. 5 is a cross-sectional view illustrating a first method of manufacturing a DRAM cell structure according to the present invention; FIG. 6 is a cross-sectional view illustrating a first method of manufacturing a DRAM cell structure according to the present invention; FIG. 8 is a cross-sectional view illustrating a second method of manufacturing the DRAM cell structure according to the present invention. FIG. 8 is a cross-sectional view illustrating a second method of manufacturing the DRAM cell structure according to the present invention. It is sectional drawing which showed an example of the cell structure.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2a, 2b ... Trench capacitor 3 ... Plate electrode 4 ... Capacitor insulating film 5 ... Storage electrode 8 ... Buried-nwell layer 9 ... Pwell layer 10 ... · Trench grooves 11, 17 ··· silicon oxide film 12 ··· first diffusion region 13 ··· gate electrode (n + type polysilicon)
14 ... STI
16 second diffusion region 18 contact 19 interlayer insulating film 20 bit line

Claims (9)

A semiconductor substrate;
A vertical transfer transistor provided on the surface of the semiconductor substrate, wherein charge carriers move in a direction perpendicular to the surface of the semiconductor substrate;
A plurality of trench capacitors provided below the vertical transfer transistor;
A semiconductor device comprising: A semiconductor substrate;
A first insulating film formed on the surface of the semiconductor substrate;
A gate electrode formed below the first insulating film;
A gate insulating film formed on a side surface of the gate electrode;
A second diffusion region formed on a periphery of the gate insulating film on a surface of the semiconductor substrate;
A second insulating film formed below the gate electrode;
A first diffusion region formed below the second insulating film;
A plurality of trench capacitors formed below the diffusion region;
With
The semiconductor device according to claim 1, wherein the storage electrode of the trench capacitor is connected to the first diffusion region. 3. The semiconductor device according to claim 2, wherein said storage electrode is made of a conductive film containing impurities. 4. The semiconductor device according to claim 1, wherein the plurality of trench capacitors are two trench capacitors. 5. Forming a plurality of trench capacitors inside the semiconductor substrate;
Forming a trench in the semiconductor substrate above the trench capacitor, the trench having a size extending over the plurality of trench capacitors;
Forming a first diffusion region between the trench groove and the trench capacitor;
Depositing an insulating film on side and bottom surfaces of the trench groove, and forming a gate insulating film on the side surface of the trench groove;
Forming a gate electrode by burying a conductive film in the trench where the insulating film is deposited;
Forming a second diffusion region on the periphery of the gate electrode on the surface of the semiconductor substrate;
A method for manufacturing a semiconductor device comprising: Forming a plurality of trench capacitors each having a storage electrode containing an impurity inside the semiconductor substrate;
Forming a trench in the semiconductor substrate above the trench capacitor, the trench having a size extending over the plurality of trench capacitors;
Annealing the semiconductor substrate and diffusing impurities contained in a storage electrode of the trench capacitor to form a first diffusion region between the trench groove and the trench capacitor;
Depositing an insulating film on side and bottom surfaces of the trench groove, and forming a gate insulating film on the side surface of the trench groove;
Forming a gate electrode by burying a conductive film in the trench where the insulating film is deposited;
Forming a second diffusion region on the periphery of the gate electrode on the surface of the semiconductor substrate;
A method for manufacturing a semiconductor device comprising: The step of forming the first diffusion region includes:
6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of ion-implanting impurities into a bottom surface of the trench groove after forming the trench groove. The method according to claim 5, wherein the first diffusion region and the second diffusion region are formed simultaneously. 9. The method according to claim 5, wherein the plurality of trench capacitors are two trench capacitors.

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