JP2004303799A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can reduce a thermal budget and restrain a hydrogen atom from spreading into a gate insulated film. <P>SOLUTION: The semiconductor device is provided with the gate insulated film 3 formed on a silicon substrate 1, a gate electrode 10 formed on the gate insulated film 3, a silicon nitride film 8 covering at least the upper surface of the gate electrode 10, and side wall 13s which are formed of second silicon nitride films 12 on both side surfaces of the gate insulated film and the electrode 10. In the semiconductor device, a first hydrogen spread suppression film 7 is formed between the gate electrode 10 and the first silicon nitride film 8, and restrains a hydrogen atom generated in the silicon nitride film 8 from spreading to the upper surface of the gate electrode 10. A second hydrogen spread suppression film 11 is formed between the gate electrode 10 and the side walls 13, and restrains a hydrogen atom generated in the side wall 13 from spreading to the gate insulated film 3 and the gate electrode 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using a polymetal gate electrode or a silicide gate electrode capable of reducing the thickness of a gate insulating film and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in an LSI (Large Scale Integrated circuit), in order to increase the degree of integration of a chip, miniaturization of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which is an element constituting the LSI, and reduction in operating voltage are performed. Have been.
[0003]
On the other hand, high integration of elements causes an increase in wiring resistance, and lowers the speed of the elements. Therefore, for the purpose of improving the speed of the device, for example, in a gate electrode connected to a word line of a memory, a poly-silicon film using a tungsten film having a lower resistance than the conventional cobalt silicide film is used. Research on metal gate electrodes is underway.
[0004]
A conventional semiconductor device provided with a polymetal gate electrode will be described with reference to FIGS. 5 and 6 (for example, see Patent Document 1). First, the configuration of a conventional semiconductor device will be described with reference to FIG. FIG. 5 is a cross-sectional view showing a configuration of a conventional semiconductor device. FIG. 5 shows only a p-channel MOS transistor constituting a part of the semiconductor device, and only an insulating portion is hatched.
[0005]
As shown in FIG. 5, the conventional semiconductor device includes a p-type silicon substrate 41. A plurality of element isolations 42a and 42b (only a pair of element isolations 42a and 42b are shown in FIGS. 5 and 6) are provided at predetermined intervals on the silicon substrate 41 by STI (Shallow Trench Isolation). Are formed so as to be exposed on the silicon substrate 41.
[0006]
A p-channel MOS transistor is formed between the element isolations 42a and 42b. Specifically, an n-well is formed in the silicon substrate 41 from the element isolations 42a to 42b. Between the element isolations 42a and 42b on the silicon substrate 41, a gate insulating film 43 and a polymetal gate electrode 49 are stacked so as to be aligned with each other in order. The polymetal gate electrode 49 includes an amorphous silicon film 44 formed on the gate insulating film 43, a tungsten nitride (WN) film 45 formed on the amorphous silicon film 44, and a tungsten nitride (WN) film 45. And a tungsten (W) film 46 formed thereon. On the polymetal gate electrode 49, a silicon nitride film 47 serving as a gate cap layer is laminated so as to match the polymetal gate electrode 49.
[0007]
Further, sidewalls 51 are formed so as to cover both side surfaces of the gate insulating film 43, the polymetal gate electrode 49, and the silicon nitride film 47. LDD (Lightly Doped Drain) regions 52a and 52b are formed in the surface layer portion of the silicon substrate 41 below each sidewall 51, respectively. A source (p +) region 53 is formed in the surface layer of the silicon substrate 41 between the element isolation 42a and the sidewall 51, and the surface layer of the silicon substrate 41 between the element isolation 42b and the sidewall 51 is formed. Has a drain (p +) region 54 formed therein.
[0008]
Next, a method for manufacturing the conventional semiconductor device shown in FIG. 5 will be described with reference to FIG. 6A to 6E are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 5, and FIGS. 6A to 6E show a series of main steps. In FIG. 6, as in FIG. 5, only the p-channel MOS transistor constituting a part of the semiconductor device is shown, and only the insulating portion is hatched.
[0009]
First, as shown in FIG. 6A, isolations 42a and 42b are formed on a silicon substrate 41. Specifically, a plurality of shallow trenches for element isolation are formed at predetermined intervals on the surface of the silicon substrate 41, and a silicon oxide film is formed on the entire surface of the silicon substrate 41. The silicon oxide film is formed until the inside of the groove is filled with the silicon oxide film. Further, the surface is planarized by a CMP (Chemical Mechanical Polishing) method or the like until the surface of the silicon nitride film deposited inside the trench and the surface of the silicon substrate 41 are aligned. After the formation of the element isolations 42a and 42b, phosphorus (P) and arsenic (As) are ion-implanted into the ion-implanted region sandwiched therebetween to form an n-well inside the silicon substrate 41.
[0010]
Next, as shown in FIG. 6B, rapid heating is performed by an RTP (Rapid Thermal Process) device to form an oxide film or an oxynitride film so as to cover the silicon substrate 41 and the element isolations 42a and 42b. The formed gate insulating film 43 is formed. Further, SiH is deposited on the gate insulating film 43 by the LP-CVD apparatus. ₄ An amorphous silicon (Amorphous Si) film 44 is formed in a gas atmosphere, and boron (B) is ion-implanted to perform gate doping.
[0011]
Thereafter, a tungsten nitride (WN) film 45 and a tungsten (W) film 46 are sequentially formed on the amorphous silicon film 44. Then, a silicon nitride film 47 serving as a gate cap layer is formed on the tungsten film 46 by SiH. ₂ Cl ₂ Gas and NH ₃ The film is formed under an atmosphere of a mixed gas with a gas. The silicon nitride film 47 is an LP-SiN (Low Pressure Chemical Vapor Deposition Silicon Nitride) film. Further, in order to form a gate pattern, a photoresist pattern 48 is formed at a predetermined position on the silicon nitride film 47 between the element isolations 42a and 42b.
[0012]
Next, as shown in FIG. 6C, using the photoresist pattern 48 as a mask, the gate insulating film 43, the amorphous silicon film 44, the tungsten nitride (WN) film 45, the tungsten (W) film 46, and the silicon nitride film 47. Is etched. As a result, a polymetal gate electrode 49 composed of the amorphous silicon film 44, the tungsten nitride (WN) film 45, and the tungsten (W) film 46 is obtained. After that, the photoresist pattern 48 is removed.
[0013]
Next, as shown in FIG. 6D, a SiH is formed so as to cover the silicon substrate 41 and the stacked body composed of the gate insulating film 43, the polymetal gate electrode 49 and the silicon nitride film 47. ₂ Cl ₂ Gas and NH ₃ The silicon nitride film 50 is formed under an atmosphere of a mixed gas with the gas. The silicon nitride film 50 is also an LP-SiN film similar to the silicon nitride film 47 described above.
[0014]
Next, as shown in FIG. 6E, the silicon nitride film 50 is subjected to anisotropic dry etching to form sidewalls covering both side surfaces of the gate insulating film 43, the polymetal gate electrode 49 and the silicon nitride film 47. 51 are formed. Next, using the sidewalls 51 as a mask, boron (B) ions are implanted at a low concentration into the silicon substrate 41, and thereafter boron (B) ions are implanted at a high concentration. Thus, the LDD (Lightly Doped Drain) regions 52a and 52b below the sidewall 51, the source (p +) region 53 located between the element isolation 42a and the sidewall 51, and the element isolation 42b and the sidewall 52 A drain (p +) region 54 located therebetween is formed.
[0015]
In the MOS transistor having the polymetal gate electrode 49 formed in this manner, the wiring resistance can be reduced, and therefore, even if the degree of integration is high, a reduction in speed can be suppressed.
[0016]
[Patent Document 1]
JP 2001-168097 A
[0017]
[Problems to be solved by the invention]
However, in the polymetal gate electrode 49 formed of the amorphous silicon film 44, the tungsten nitride (WN) film 45, and the tungsten (W) film 46 formed by the method shown in FIG. A large amount of hydrogen atoms (H) are present at the interface between the gate insulating film 44 and the gate insulating film 43 and near this interface. Therefore, there is a problem that the threshold voltage (Vth) of the transistor fluctuates and the on-current (Ion) is deteriorated by the hydrogen atoms (H). This problem will be described below.
[0018]
In the example of FIG. 6, the silicon-nitride film 47 forming the gate cap layer and the silicon nitride film 50 forming the sidewalls 51 are formed with Si—H bonds as described above. A silicon source gas containing nitrogen and a source gas of nitrogen containing NH bonds are used. The silicon nitride film 47 forming the gate cap layer is formed at a temperature of 650 ° C. to 800 ° C., whereas the silicon nitride film 50 forming the sidewall 51 has a reduced thermal budget. Therefore, the film is formed at a temperature of 400 ° C. to 600 ° C.
[0019]
For this reason, in the silicon nitride film 50 formed at a relatively low temperature, unreacted Si—H bonds and N—H bonds are easily generated at the time of film formation, and silicon nitride is formed in the sidewalls 51 (silicon nitride film 50). The unreacted Si—H bond and N—H bond generated during the formation of the silicon nitride film 50 are more present than in the nitride film 47.
[0020]
After the formation of the sidewalls 51, various processes are performed on the silicon substrate 41 and heat is applied to the silicon substrate 41 in the silicon nitride film 47 constituting the gate cap layer and the sidewalls 51 (silicon nitride film 50). A hydrogen atom (—H group) is separated from unreacted Si—H bonds and N—H bonds therein. The separated hydrogen atoms (-H groups) diffuse into the gate insulating film 43 and the gate electrode 49.
[0021]
In this case, since the number of unreacted Si—H bonds and N—H bonds included in the sidewalls 51 is large, many hydrogen atoms (—H groups) are generated from the sidewalls 51 by the gate insulating film 43 and the gate. It diffuses to the electrode 49 and acts as an electron trap. As a result, the above-described variation in the threshold voltage of the transistor and deterioration in the on-current occur. The number of unreacted Si—H bonds and N—H bonds contained in the silicon nitride film 47 is small, and the number of hydrogen atoms (—H groups) diffused from the silicon nitride film 47 is small. Such a problem is not expected to occur.
[0022]
On the other hand, the problem due to hydrogen diffusion can be solved by setting the film forming temperature of the silicon nitride film 50 forming the side wall 51 to be the same as the film forming temperature of the silicon nitride film 47. There is a problem that the budget cannot be reduced.
[0023]
Focusing only on the reduction of the thermal budget, it is preferable that both the silicon nitride film 50 and the silicon nitride film 47 be formed at the low temperature described above. It is required to suppress the diffusion of hydrogen atoms (-groups) after forming both at the above-mentioned low temperature.
An object of the present invention is to provide a semiconductor device capable of reducing a thermal budget and suppressing diffusion of hydrogen atoms into a gate insulating film, and a method for manufacturing the same.
[0024]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and at least an upper surface of the gate electrode. Any one of the first silicon nitride film formed, the sidewall formed of a second silicon nitride film on both side surfaces of the gate insulating film and the gate electrode, and the first silicon nitride film and the sidewall And hydrogen diffusion suppressing means for suppressing diffusion of hydrogen atoms generated in one or both of them into the gate insulating film and the gate electrode.
[0025]
In the above-described semiconductor device according to the present invention, the hydrogen diffusion suppressing means is provided between the gate electrode and the first silicon nitride film to transfer hydrogen atoms generated in the first silicon nitride film to the gate electrode. A first hydrogen diffusion suppressing film formed so as to suppress the diffusion of, and between the gate insulating film and the gate electrode and the sidewall, the gate insulating film of hydrogen atoms generated in the sidewall and It is preferable to include a second hydrogen diffusion suppressing film formed so as to suppress the diffusion to the gate electrode.
[0026]
In the above aspect, the first hydrogen diffusion suppressing film and the first silicon nitride film are formed so as to match the gate electrode, and the sidewall is a nitride film, the gate insulating film, It is preferable that the gate electrode, the first hydrogen diffusion suppressing film, and the first silicon be formed so as to cover side surfaces of the first silicon. Further, in the above aspect, the first hydrogen diffusion suppressing film is formed so as to cover the semiconductor substrate, the gate electrode, the second hydrogen diffusion suppressing film, and the sidewall, and Preferably, a silicon nitride film is formed so as to cover the first hydrogen diffusion suppression film.
[0027]
Next, in order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention comprises a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, A method of manufacturing a semiconductor device having at least a first silicon nitride film covering at least an upper surface and a sidewall formed of a second silicon nitride film on a side surface of the gate electrode, wherein (A) the first Forming a hydrogen diffusion suppressing means for suppressing hydrogen atoms generated in one or both of the silicon nitride film and the sidewall from diffusing into the gate insulating film and the gate electrode. .
[0028]
In the method for manufacturing a semiconductor device according to the present invention, the step (A) is performed on the first silicon nitride film between (a) the gate electrode and the first silicon nitride film. Forming a first hydrogen diffusion suppressing film for suppressing the diffusion of hydrogen atoms to the gate electrode; and (b) generating the first hydrogen diffusion suppressing film on the sidewall between the gate insulating film and the gate electrode and the sidewall. Forming a second hydrogen diffusion suppressing film for suppressing the diffusion of hydrogen atoms into the gate insulating film and the gate electrode.
[0029]
In the above aspect, the step (a) includes forming the gate insulating film, the conductive film serving as the gate electrode, the first hydrogen diffusion suppressing film, and the first silicon nitride on the semiconductor substrate. Forming a resist pattern on the first silicon nitride film; performing etching using the resist pattern as a mask to form the gate insulating film, the gate electrode, the first Forming a stacked body of the hydrogen diffusion suppressing film and the first silicon nitride film, wherein the step (b) is performed by removing the stacked body obtained in the step (a). A step of covering with a second hydrogen diffusion suppression film, a step of covering the second hydrogen diffusion suppression film with the second silicon nitride film, and a step of covering the second hydrogen diffusion suppression film and the second silicon nitride film. Perform anisotropic etching, The side surfaces of the serial laminate through the second hydrogen diffusion suppressing film preferably has a step of forming a sidewall of the second silicon nitride film. In this case, the conductor film serving as the gate electrode is preferably formed by stacking a plurality of types of metal films.
[0030]
Further, in the above aspect, a step of laminating the gate insulating film and a silicon conductive film to be the gate electrode on the semiconductor substrate; and a step of forming a resist pattern on the silicon conductive film. Performing etching using the resist pattern as a mask to form a stacked body of the gate insulating film and the gate electrode, and further comprising a step of silicidizing a part of the upper surface side of the gate electrode, (B) covering the stacked body with the second hydrogen diffusion suppressing film; covering the second hydrogen diffusion suppressing film with the second silicon nitride film; Anisotropic etching is performed on the diffusion suppressing film and the second silicon nitride film, and a side wall of the second silicon nitride film is formed on a side surface of the stacked body via the second hydrogen diffusion suppressing film. And (b) forming the second hydrogen diffusion suppressing film and the sidewall obtained in the step (b). It is preferable that the method further includes a step of covering with a hydrogen diffusion suppression film and a step of covering the first hydrogen diffusion suppression film with the first silicon nitride film.
[0031]
Further, in the above aspect, the first hydrogen diffusion suppression film and the second hydrogen diffusion suppression film are silicon nitride films, and a silicon source gas containing no bond between silicon atoms and hydrogen atoms and a nitrogen source gas. The first silicon nitride film and the second silicon nitride film are formed by using a source gas of silicon including a bond between silicon atoms and hydrogen atoms and a source gas of nitrogen. It is preferable that the film is formed by using.
[0032]
In this case, tetrachloro silicon (SiCl ₄ ) Or hexachlorodisilane (Si ₂ Cl ₆ ). The source gas of silicon containing a bond between the silicon atom and the hydrogen atom is SiH ₂ Cl ₂ , SiH ₂ [NH (C ₄ H ₉ )] ₂ , SiH ₄ Gas containing at least one of the above. Further, as the nitrogen source gas, ammonia (NH ₃ ), Monomethylamine (CNH) ₅ ), Hydrazine (N ₂ H ₄ ) Or a gas containing at least one of these derivatives.
[0033]
In the above aspect, it is preferable that the first hydrogen diffusion suppression film is a silicon nitride film formed at a film formation temperature higher than a film formation temperature of the first silicon nitride film. Specifically, the first hydrogen diffusion suppressing film is formed at a film formation temperature of 750 to 800 ° C., and the first silicon nitride film is formed at a film formation temperature of 400 ° C. to 650 ° C. Preferably, it is coated. Further, it is preferable that the second hydrogen diffusion suppressing film is a silicon nitride film formed at a film forming temperature higher than the film forming temperature of the second silicon nitride film. Specifically, the second hydrogen diffusion suppressing film is formed at a temperature of 750 to 800 ° C., and the second silicon nitride film is formed at a film forming temperature of 400 ° C. to 650 ° C. Is preferred.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Hereinafter, a semiconductor device and a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view illustrating a configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 1 shows only a p-channel MOS transistor constituting a part of the semiconductor device, and only an insulating portion is hatched.
[0035]
As shown in FIG. 1, the semiconductor device according to the first embodiment also includes a p-type silicon substrate 1 as in the related art. On the p-type silicon substrate 1, a plurality of element isolations 2a and 2b (only the element isolations 2a and 2b are shown in FIG. 1) are formed on the silicon substrate 1 at predetermined intervals by the STI method. It is formed so as to be exposed to.
[0036]
A p-channel MOS transistor is formed between the element isolations 2a and 2b. Specifically, as in the conventional case, an n-well is formed in the silicon substrate 1 from the element isolations 2a to 2b. Further, between the element isolations 2a and 2b on the silicon substrate 1, the gate insulating film 3 and the gate electrode 10 are laminated so as to be aligned with each other in order.
[0037]
The gate electrode 10 is formed on the amorphous silicon film 4 formed on the gate insulating film 3, the titanium nitride (TiN) film 5 formed on the amorphous silicon film 4, and the titanium nitride (TiN) film 5. This is a polymetal gate electrode constituted by the formed tungsten (W) film 6.
[0038]
However, in the first embodiment, unlike the conventional case, the hydrogen diffusion suppressing film 7 is formed between the gate electrode 10 and the silicon nitride film 8 serving as the gate cap layer. Therefore, the diffusion of hydrogen atoms (−H groups) generated in the silicon nitride film 8 into the gate electrode 10 is suppressed by the hydrogen diffusion suppression film 7. The hydrogen diffusion suppressing film 7 and the silicon nitride film 8 are formed so as to match the gate electrode 10.
[0039]
Further, in the first embodiment, both side surfaces of the gate insulating film 3, the gate electrode 10, the first hydrogen diffusion suppressing film 7, and the silicon nitride film 47, and the side walls 13 formed of the second silicon nitride film are formed. Between them, a hydrogen diffusion suppression film 11 is formed. Therefore, the diffusion of the hydrogen atoms generated in the sidewalls 13 into the gate insulating film 3 and the gate electrode 10 is suppressed by the hydrogen diffusion suppression film 11. In addition, the hydrogen diffusion suppression film 11 suppresses the hydrogen atoms generated in the silicon nitride film 8 from entering the sidewalls 13, so that the hydrogen atoms generated in the silicon nitride film 8 are Diffusion into the gate insulating film 3 and the gate electrode 10 is also suppressed. The sidewall 13 is formed so as to cover the hydrogen diffusion suppression film 11.
[0040]
In this specification, the silicon nitride film located on the upper surface of the gate electrode is hereinafter referred to as a first silicon nitride film, and the hydrogen diffusion suppressing film located on the upper surface of the gate electrode is hereinafter referred to as a first hydrogen diffusion suppressing film. . Further, in this specification, a silicon nitride film serving as a sidewall of a gate electrode is hereinafter referred to as a second silicon nitride film, and a hydrogen diffusion suppressing film covered with the second silicon nitride film is referred to as a second hydrogen diffusion film. It is called a suppression film.
[0041]
Also in the first embodiment, LDD (Lightly Doped Drain) regions 14a and 14b are formed in the surface layer portion of the silicon substrate 1 below each sidewall 13 as in the related art. Further, a source (p +) region 15 is formed in a surface layer portion of the silicon substrate 1 between the element isolation 2 a and the sidewall 13, and a surface layer portion of the silicon substrate 1 between the element isolation 2 b and the sidewall 13 is formed. Has a drain (p +) region 16 formed therein.
[0042]
Next, a method for manufacturing the semiconductor device according to the first embodiment shown in FIG. 1 will be described with reference to FIG. 2A to 2E are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 1, and FIGS. 2A to 2E show a series of main steps. FIG. 2 shows only a p-channel MOS transistor constituting a part of the semiconductor device, as in FIG. 1, and only an insulating portion is hatched.
[0043]
First, as shown in FIG. 2A, element isolations 2a and 2b are formed at a predetermined interval on a p-type silicon substrate 1, and ion implantation sandwiched between the element isolations 2a and 2b is performed. Phosphorus (P) and arsenic (As) are ion-implanted into the region to form an n-well. The process shown in FIG. 2A is performed in the same manner as the conventional process described with reference to FIG. In the present invention, the element isolation can be formed by using a LOCOS method or the like instead of the STI method.
[0044]
Next, as shown in FIG. 2B, rapid heating is performed by an RTP device to form a gate insulating film 3 of an oxide film or an oxynitride film so as to cover the silicon substrate 1 and the element isolations 2a and 2b. I do. Further, SiH is deposited on the gate insulating film 3 by an LP-CVD apparatus. ₄ An amorphous silicon film 4 is formed in a gas atmosphere, and boron (B) is ion-implanted to perform gate doping.
[0045]
Thereafter, a titanium nitride (TiN) film 5 and a tungsten (W) film 6 are sequentially formed on the amorphous silicon film 4. The amorphous silicon film 4, the titanium nitride film 5, and the tungsten film 6 are conductor films serving as gate electrodes, as shown in FIG. Up to this point, the process is performed in the same manner as the conventional process described with reference to FIG. 6B in the related art except that the titanium nitride film 5 is used instead of the tungsten nitride film.
[0046]
However, in the first embodiment, as shown in FIG. 2B, a first hydrogen diffusion suppression film 7 is formed on the tungsten film 6, and the first hydrogen diffusion suppression film 7 is formed on the first hydrogen diffusion suppression film 7. A silicon nitride film 8 serving as a gate cap layer is formed, which is different from the conventional process of forming the silicon nitride film 8 directly on the tungsten film 6.
[0047]
Thereafter, as shown in FIG. 2B, a resist pattern for forming a gate pattern is formed at a predetermined position on the first silicon nitride film 8 between the element isolations 2a and 2b, as in the conventional case. 9 is formed by photolithography.
[0048]
Next, as shown in FIG. 2C, using the resist pattern 8 as a mask, the gate insulating film 3, the amorphous silicon film 4, the titanium nitride (TiN) film 5, the tungsten (W) film 6, and the first hydrogen diffusion The suppression film 7 and the silicon nitride film 8 are etched. After that, the photoresist pattern 9 is removed. As a result, a gate electrode 10 composed of the amorphous silicon film 4, the titanium nitride film 5, and the tungsten film 6 is obtained. The process shown in FIG. 2C is performed in the same manner as the conventional process described with reference to FIG. 6C in the related art, except that the gate insulating film 3, the amorphous silicon film 4, the titanium nitride (TiN) 1) In addition to the film 5, the tungsten (W) film 6 and the first silicon nitride film 8, the first hydrogen diffusion suppressing film 7 is also different in that etching is performed.
[0049]
Next, as shown in FIG. 2D, in the first embodiment, the gate insulating film 3, the gate electrode 10, the first hydrogen diffusion suppressing film 7, and the first silicon nitride film 8 are formed. A second hydrogen diffusion suppression film 11 is formed so as to cover the stacked body and the silicon substrate 1. Further, a second silicon nitride film 12 serving as a sidewall is formed so as to cover the second hydrogen diffusion suppression film 11.
[0050]
Next, as shown in FIG. 2E, anisotropic dry etching is performed on the second hydrogen diffusion suppressing film 11 and the second silicon nitride film 12. As a result, both sides of the stacked body composed of the gate insulating film 3, the gate electrode 10, the first hydrogen diffusion suppressing film 7, and the first silicon nitride film 8 are covered with the second hydrogen diffusion suppressing film 11. The second hydrogen diffusion suppressing film 11 is covered with a sidewall 13 formed by the second silicon nitride film 12.
[0051]
Next, using the sidewalls 13 as a mask, boron (B) ions are implanted into the silicon substrate 1 at a low concentration, and then boron (B) ions are implanted at a high concentration. Accordingly, LDD (Lightly Doped Drain) regions 14 a and 14 b under each sidewall 13, source (p +) region 15 located between element isolation 2 a and sidewall 13, element isolation 2 b and sidewall 13 And a drain (p +) region 16 located therebetween. Note that this ion implantation step is performed in the same manner as the conventional step described with reference to FIG. Thereafter, an interlayer insulating film, a contact hole, a via hole, and a metal wiring (not shown) are formed, and a semiconductor device is completed.
[0052]
Here, the first hydrogen diffusion suppressing film 8, the second hydrogen diffusion suppressing film 11, the first silicon nitride film 7 forming the gate cap layer, and the second forming the side wall 13 in the first embodiment. The formation of the silicon nitride film 12 and the suppression of the diffusion of hydrogen atoms by the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 11 will be described.
[0053]
In the first embodiment, the first silicon nitride film 8 and the second silicon nitride film 12 are formed by using a silicon source gas including a bond between silicon atoms and hydrogen atoms (Si—H bond), This is performed under an atmosphere of a mixed gas with the source gas.
[0054]
For this reason, when the first silicon nitride film 8 and the second silicon nitride film 12 are formed, many unreacted Si—H bonds and N—H bonds are generated. Therefore, as described in the related art, when heat is applied to the silicon substrate 1 after the step shown in FIG. 2E is completed, the formation of the first silicon nitride film 8 and the second silicon nitride film 12 is completed. Hydrogen atoms (—H groups) are separated from unreacted Si—H bonds and N—H bonds generated at the time of film formation, and the side formed by the first silicon nitride film 8 and the second silicon nitride film 12 is formed. The hydrogen atoms (-H groups) separated in the wall 13 diffuse toward the gate electrode 10 and the gate insulating film 3.
[0055]
Further, as will be described later, in the first embodiment, unlike the conventional semiconductor device described with reference to FIGS. 5 and 6, the first silicon nitride film 8 also has a silicon source gas containing a Si—H bond. And is formed at a relatively low temperature. For this reason, in the first embodiment, the gate electrode 10 and the gate insulating film generated in the first silicon nitride film 8 and the side wall 13 are different from the conventional semiconductor device described with reference to FIGS. It can be said that the number of hydrogen atoms (—H groups) diffusing toward 3 is large.
[0056]
On the other hand, in the first embodiment, the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 11 are silicon nitride films, and these films are formed by a single-wafer CVD apparatus using silicon atoms. It is performed in an atmosphere of a mixed gas of a silicon source gas not containing a bond with a hydrogen atom (Si-H bond) and a nitrogen source gas.
[0057]
Therefore, when the first hydrogen diffusion suppressing film 7 and the second hydrogen diffusion suppressing film 8 are formed, only N—H bonds are generated as unreacted hydrogen bonds, so that the step shown in FIG. After that, it can be said that the number of hydrogen bonds separated from unreacted hydrogen bonds is smaller than that of the first silicon nitride film 8 and the second silicon nitride film 12. In general, since a silicon nitride film has a dense molecular structure, hydrogen atoms diffused from the outside into the silicon nitride film are controlled by the silicon nitride film.
[0058]
Therefore, if a silicon nitride film having a small number of unreacted hydrogen bonds is provided as the first hydrogen diffusion suppressing film 7 and the second hydrogen diffusion suppressing film 8 as shown in FIGS. The number of hydrogen atoms diffusing into the electrode 10 and the gate insulating film 3 is reduced as compared with the examples of FIGS. 5 and 6 shown in the prior art.
[0059]
That is, the diffusion of hydrogen atoms (-H groups) generated in the first silicon nitride film 8 constituting the gate cap layer to the upper surface of the gate electrode 10 is caused by the first hydrogen diffusion suppression film 7. Be suppressed. The diffusion of hydrogen atoms (-H groups) generated in the second silicon nitride film 12 constituting the sidewall 13 to the side surfaces of the gate electrode 10 is caused by the second hydrogen diffusion suppression film 11. Be suppressed. Further, the intrusion of the hydrogen atoms generated in the first silicon nitride film 8 into the sidewalls 13 is also suppressed. As a result, the hydrogen atoms generated in the first silicon nitride film 8 are Diffusion to the side surface of the gate electrode 10 is also suppressed by the second hydrogen diffusion suppression film 11.
[0060]
For this reason, in the first embodiment, as described above, although the number of generated hydrogen atoms (—H groups) is larger than in the related art, they are transferred to the gate electrode 10 and the gate insulating film 3. And diffusion is suppressed.
[0061]
Preferred examples of a silicon source gas containing a Si—H bond used for forming the first silicon nitride film 8 and the second silicon nitride film 12 include SiH 2 Cl 2 (dichlorosilane) gas and SiH 2 gas. ₂ [NH (C ₄ H ₉ )] ₂ (Victorary butyl silane (BTBAS)) gas and SiH ₄ (Silane) gas.
[0062]
Preferred examples of the silicon source gas containing no Si—H bond used for forming the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 11 include SiCl 4 (tetrachlorosilicon) gas and , Si ₂ Cl ₆ (Hexachlorodisilane) gas.
[0063]
Further, as an example of a nitrogen source gas used for forming the first hydrogen diffusion suppressing film 7, the second hydrogen diffusion suppressing film 11, the first silicon nitride film 8, and the second silicon nitride film 12, ammonia (NH ₃ ) Gas, monomethylamine (CNH) ₅ ) Gas, hydrazine (N ₂ H ₄ ) Gases, and mixtures thereof. Further, ammonia (NH ₃ ), Monomethylamine (CNH) ₅ ), Hydrazine (N ₂ H ₄ )) Is also included.
[0064]
Further, the first silicon nitride film 8 and the second silicon nitride film 12 are formed using the silicon source gas containing Si—H bonds as described above. Therefore, the first silicon nitride film 8 and the second silicon nitride film 12 can be formed at a temperature lower than a general silicon nitride film formation temperature (700 ° C. to 800 ° C.). In the first embodiment, the temperature at which the first hydrogen diffusion suppressing film 7 and the second hydrogen diffusion suppressing film 11 are formed is higher than the temperature at which the first silicon nitride film 8 and the second silicon nitride film 12 are formed. Is also set high.
[0065]
Specifically, the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 11 are set at a film formation temperature of 700 ° C. to 850 ° C., preferably 750 ° C. to 800 ° C., and a film formation time of 10 minutes. The film is formed by setting the time to seconds to 2 minutes, preferably 30 seconds to 1 minute. The first silicon nitride film 8 and the second silicon nitride film 12 are set at a film forming temperature of 400 ° C. to 650 ° C., preferably 500 ° C. to 600 ° C., and a film forming time of 60 minutes to 400 minutes, preferably The film is formed for 200 minutes to 300 minutes.
[0066]
As described above, in the first embodiment, the deposition temperature of the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 11 is set to a relatively high temperature, and the first silicon nitride film 8 and the second Since the film formation temperature of the silicon nitride film 12 is set to a relatively high temperature, the number of unreacted hydrogen bonds generated in the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 11 is the first. Is smaller than the number of unreacted hydrogen bonds generated in the silicon nitride film and the second silicon nitride film.
[0067]
That is, in the first embodiment, the number of hydrogen atoms (-H groups) generated in the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 11 is also reduced by the first film formation temperature even when the film formation temperature is set. Is smaller than the number of hydrogen atoms (-H groups) generated in the silicon nitride film and the second silicon nitride film. Therefore, according to the first embodiment, it is possible to more preferably suppress the above-described diffusion of the hydrogen atom (—H group).
[0068]
In general, when a silicon nitride film is formed by setting the film formation temperature to a relatively low temperature of 400 ° C. to 650 ° C., the number of diffused hydrogen atoms increases. In 1, diffusion of hydrogen atoms into the gate electrode 10 and the gate insulating film 3 is suppressed by the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 8.
[0069]
Further, in the first embodiment, both the first silicon nitride film 8 forming the gate cap layer and the second silicon nitride film 12 forming the side wall 13 are formed of the normal silicon nitride film as described above. The film is formed at a temperature lower than the film forming temperature. Therefore, according to the first embodiment, the thermal budget is reduced as compared with the conventional semiconductor device shown in FIGS. 5 and 6 in which only the silicon nitride film forming the sidewall is formed at a low temperature. Is also planned.
[0070]
In the first embodiment, the second hydrogen diffusion suppressing film 11 is formed at a high temperature of 750 ° C. to 800 ° C., and the second hydrogen diffusion suppressing film 11 Hydrogen atoms (-H groups) are separated from unreacted hydrogen bonds generated in one silicon nitride film 8. However, the separated hydrogen atoms (—H groups) cannot diffuse into the gate electrode 10 due to the presence of the first hydrogen diffusion suppressing film 7, and thus are diffused outside the first silicon nitride film 8. In the first embodiment, the formation of the second hydrogen diffusion suppression film 11 also suppresses diffusion of hydrogen atoms (-H groups) into the gate electrode 10 and the gate insulating film 3.
[0071]
As described above, in the first embodiment, the hydrogen atoms generated in the first silicon nitride film 8 forming the gate cap layer and the second silicon nitride film 12 forming the sidewall 13 are converted into the gate insulating film 3 and the gate A hydrogen diffusion suppressing means (first hydrogen diffusion suppressing film 7 and second hydrogen diffusion suppressing film 11) for suppressing diffusion to electrode 10 is provided.
[0072]
For this reason, according to the first embodiment, the thermal budget is reduced by both the first silicon nitride film 8 forming the gate cap layer and the second silicon nitride film 12 forming the sidewall 13. In addition, it is possible to suppress a change in threshold voltage of the transistor and a deterioration in on-state current due to a hydrogen atom (-H group).
[0073]
(Embodiment 2)
Next, a semiconductor device and a method of manufacturing the semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. First, the configuration of the semiconductor device according to the second embodiment will be described with reference to FIG. FIG. 3 is a cross-sectional view illustrating a configuration of the semiconductor device according to the second embodiment of the present invention. In FIG. 3, as in FIG. 1, only the p-channel MOS transistor constituting a part of the semiconductor device is shown, and only the insulating portion is hatched.
[0074]
As shown in FIG. 3, the semiconductor device according to the second embodiment also includes a silicon substrate 21, similarly to the semiconductor device according to the first embodiment. The silicon substrate 21 is the same as the silicon substrate 1 shown in FIGS. 1 and 2 in the first embodiment. Element isolations 22a and 22b are formed on the silicon substrate 21. The element isolations 22a and 22b are the same as the element isolations 2a and 2b shown in FIGS. 1 and 2 in the first embodiment.
[0075]
Also, in the second embodiment, as in the first embodiment, a p-channel MOS transistor is formed between element isolations 22a and 22b. As in the first embodiment, this MOS transistor includes a gate insulating film 23 formed on a silicon substrate 21, LDD regions 32a and 32b formed in a surface layer portion of the silicon substrate 21 under each sidewall 28, A source (p +) region 33 formed in the surface layer portion of the silicon substrate 21 between the region 22a and the sidewall 28, and a drain (formed in the surface layer portion of the silicon substrate 21 between the element isolation 22b and the side wall 28) (p +) region 34.
[0076]
However, in the second embodiment, unlike in the first embodiment, the gate electrode 25 provided on the gate insulating film 23 is a silicide gate electrode. A part 29 on the upper surface side of the gate electrode 25 is silicided. Further, in the second embodiment, unlike the first embodiment, the second hydrogen diffusion suppressing film 26 is formed so as to cover only both side surfaces of the gate electrode 25 and the gate insulating film 23. The sidewall 28 is formed so as to cover the second hydrogen diffusion suppression film 26.
[0077]
Further, in the second embodiment, unlike the first embodiment, the first hydrogen diffusion suppressing film 30 covers the silicon substrate 21, the gate electrode 25, the second hydrogen diffusion suppressing film 26, and the sidewall 28. Is formed. Further, the second silicon nitride film 31 is formed so as to cover the first hydrogen diffusion suppression film 30.
[0078]
Next, a method for manufacturing the semiconductor device according to the first embodiment shown in FIG. 3 will be described with reference to FIG. 4A to 4E are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 3, and FIGS. 4A to 4E show a series of main steps.
[0079]
First, as shown in FIG. 4A, element isolations 22a and 22b are formed at predetermined intervals on a p-type silicon substrate 21, and ion implantation sandwiched between the element isolations 22a and 22b is performed. Phosphorus (P) and arsenic (As) are ion-implanted into the region to form an n-well. Further, a gate insulating film 23 of an oxide film or an oxynitride film is formed by an RTP device. The steps up to this point are performed in the same manner as the conventional steps described with reference to FIG.
[0080]
After that, in the second embodiment, unlike the related art and the first embodiment, the SiH is ₄ Under a gas atmosphere, a polysilicon film 24 is formed so as to cover the gate insulating film 23, and boron (B) is ion-implanted to perform gate doping.
[0081]
Next, as shown in FIG. 4B, a resist pattern (not shown) for forming a gate pattern is formed at a predetermined position on the polysilicon film 24 between the element isolations 22a and 22b. It is formed by a photolithography method. Next, using this resist pattern as a mask, the gate insulating film 23 and the polysilicon film 24 are etched to form a gate electrode 25 having a polysilicon pattern. Thereafter, by removing the photoresist pattern, the state shown in FIG. 4B is obtained.
[0082]
Next, as shown in FIG. 4C, a second hydrogen diffusion suppressing film is formed so as to cover the stacked body of the gate electrode 25 and the gate insulating film 23, the element isolations 22a and 22b, and the silicon substrate 21. 26 is formed. Further, a second silicon nitride film 27 serving as a sidewall is formed so as to cover the second hydrogen diffusion suppression film 26.
[0083]
Next, as shown in FIG. 4D, anisotropic dry etching is performed on the second hydrogen diffusion suppressing film 26 and the second silicon nitride film 27. As a result, both side surfaces of the stacked body of the gate electrode 25 and the gate insulating film 23 are covered with the second hydrogen diffusion suppressing film 26, and the second hydrogen diffusion suppressing film 26 is formed of the second silicon nitride film 27. It is covered by the formed sidewall 28.
[0084]
Next, using the sidewalls 28 as a mask, boron (B) ions are implanted into the silicon substrate 21 at a low concentration, and then boron (B) ions are implanted at a high concentration. Thereby, the LDD (Lightly Doped Drain) regions 32a and 32b below each sidewall 28, the source (p +) region 33 located between the element isolation 22a and the sidewall 28, and the element isolation 22b and the sidewall 28 And a drain (p +) region 34 located therebetween. Note that this ion implantation step is performed in the same manner as the conventional step described with reference to FIG.
[0085]
Next, as shown in FIG. 4E, a metal film (not shown) of titanium, cobalt or nickel is formed to cover the gate electrode 25, and the silicon substrate 21 is heated. By this step, a part 29 on the upper surface side of the gate electrode 25 is silicided, and the gate electrode 25 becomes a silicide gate electrode. Thereafter, the metal film (not shown) is peeled off.
[0086]
Next, a first hydrogen diffusion suppressing film 30 is formed so as to cover the stacked body of the silicided gate electrode 25 and the gate insulating film 23, the second hydrogen diffusion suppressing film 26, and the sidewall 28.
[0087]
Thereafter, as shown in FIG. 4F, a first silicon nitride film 31 serving as a liner layer is formed so as to cover the first hydrogen diffusion suppression film 30, and a MOS transistor is completed. Thereafter, an interlayer insulating film, a contact hole, a via hole, and a metal wiring (not shown) are formed, and a semiconductor device is completed.
[0088]
Here, the first hydrogen diffusion suppressing film 30, the second hydrogen diffusion suppressing film 26, the first silicon nitride film 31 forming the liner layer, and the second hydrogen forming the side wall 28 in the second embodiment. The formation of the silicon nitride film 27 and the suppression of the diffusion of hydrogen atoms by the first hydrogen diffusion suppression film 30 and the second hydrogen diffusion suppression film 26 will be described.
[0089]
In the second embodiment, the first hydrogen diffusion suppression film 30 and the second hydrogen diffusion suppression film 26 are the same as the first hydrogen diffusion suppression film 7 and the second hydrogen diffusion suppression film 11 described in the first embodiment. This is a silicon nitride film formed under the same film forming conditions. Further, the first silicon nitride film 31 forming the liner layer and the second silicon nitride film 27 forming the sidewall 28 are formed by the first silicon nitride film 8 and the second silicon nitride film shown in the first embodiment. This is a silicon nitride film formed under the same film forming conditions as the film 12.
[0090]
For this reason, in the second embodiment, as in the first embodiment, the first silicon nitride film 31 and the second silicon nitride film 31 are different from those of the conventional semiconductor device described with reference to FIGS. It can be said that the number of hydrogen atoms (-H groups) generated in the nitride film 27 and diffused toward the gate electrode 25 and the gate insulating film 23 is large.
[0091]
However, in the second embodiment, the diffusion of hydrogen atoms (-H groups) generated in the first silicon nitride film 31 constituting the liner layer to the upper surface of the gate electrode 25 is caused by the first hydrogen The diffusion is suppressed by the diffusion suppressing film 30. The hydrogen atoms (-H groups) generated in the second silicon nitride film 27 forming the sidewalls 28 diffuse into the side surfaces of the gate insulating film 23 and the gate electrode 25 only when the second hydrogen The diffusion is suppressed by the diffusion suppressing film 26.
[0092]
Also, in the second embodiment, similarly to the first embodiment, the first silicon nitride film 31 forming the liner layer and the second silicon nitride film 27 forming the sidewall 28 are formed with a relatively low thickness. Since the film can be formed at the film temperature, the thermal budget is reduced as compared with the conventional semiconductor device shown in FIGS.
[0093]
In the second embodiment, since the first hydrogen diffusion suppression film 30 is formed at a high temperature of 750 ° C. to 800 ° C., side heat is applied when the first hydrogen diffusion suppression film 30 is formed. Hydrogen atoms (-H groups) are separated from unreacted hydrogen bonds generated in the second silicon nitride film 27 constituting the wall 28. However, since the separated hydrogen atoms (—H groups) cannot diffuse into the gate electrode 25 due to the presence of the second hydrogen diffusion suppression film 26, the second hydrogen diffusion suppression film 26 and the first hydrogen diffusion With the suppression film 30, the state is sealed in the sidewall 28.
[0094]
As described above, in the second embodiment, the hydrogen atoms generated in the first silicon nitride film 31 forming the liner layer and the second silicon nitride film 27 forming the sidewall 28 are converted into the gate insulating film 23 and the gate electrode. And a hydrogen diffusion suppressing means (a first hydrogen diffusion suppressing film 30 and a second hydrogen diffusion suppressing film 26) for suppressing diffusion to 25.
[0095]
Therefore, according to the second embodiment, both the first silicon nitride film 31 forming the liner layer and the second silicon nitride film 27 forming the sidewall 28 reduce the thermal budget. In addition, fluctuation of the threshold voltage of the transistor and deterioration of the on-state current due to hydrogen atoms (-H groups) can be suppressed.
[0096]
In the second embodiment, the first silicon nitride film and the second silicon nitride film are made of a silicon source gas containing no Si—H bond, for example, Si gas. ₂ Cl ₆ A film can also be formed at a low temperature (400 ° C. to 650 ° C.) using a (hexachlorodisilane) gas. In this case, a large amount of unreacted N—H bonds are generated due to the lowering of the film formation temperature, and a large amount of hydrogen atoms are separated therefrom. Is also suppressed by the first hydrogen diffusion suppressing film 30 and the second hydrogen diffusion suppressing film 26.
[0097]
In the present invention, the first hydrogen diffusion suppressing film and the second hydrogen diffusion suppressing film are formed of a first silicon nitride film and a second silicon nitride film by using a silicon source gas containing no Si—H bond. The present invention is not limited to a silicon nitride film obtained by forming a film at a film forming temperature higher than the film forming temperature. Materials for forming the hydrogen diffusion suppression film that can be used in the present invention include TiAlO (titanium aluminum oxide), TiAlN (titanium aluminum nitride), SiC (silicon carbide), and Al. ₂ O ₃ (Aluminum oxide) and the like.
[0098]
In the present invention, the first hydrogen diffusion suppressing film and the second hydrogen diffusion suppressing film are silicon nitride films formed at a high temperature of 750 ° C. to 800 ° C. using a silicon source gas containing Si—H bonds. It may be. Further, the first and second hydrogen diffusion suppressing films may be silicon nitride films formed at a low temperature of 400 ° C. to 650 ° C. using a silicon source gas containing no Si—H bond.
[0099]
Further, in the present invention, an embodiment may be provided in which only one of the first hydrogen diffusion suppression film and the second hydrogen diffusion suppression film is provided. However, when only the first hydrogen diffusion suppression film is provided, the first silicon nitride film is formed at 700 ° C. to 850 ° C., preferably 750 ° C. to 800 ° C. using a silicon source gas containing no Si—H bond. It is preferable to form a film. In the case where only the second hydrogen diffusion suppressing film is provided, the second silicon nitride film is formed at 700 ° C. to 850 ° C., preferably 750 ° C. to 800 ° C. using a silicon source gas containing no Si—H bond. It is preferable to form a film.
[0100]
【The invention's effect】
As described above, according to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, the thermal budget is reduced, and at the same time, the threshold voltage of the transistor due to the diffusion of hydrogen atoms (-H groups) into the gate electrode and the gate insulating film Voltage fluctuations and deterioration of on-current can be suppressed.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention;
2A to 2E are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 1 and show a series of main steps.
FIG. 3 is a sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;
4A to 4E are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 3, showing a series of main steps.
FIG. 5 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.
6A to 6E are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 5, and FIGS. 6A to 6E show a series of main steps.
[Explanation of symbols]
1,21 silicon substrate
2a, 2b, 22a, 22b Element isolation
3,23 gate insulating film
4 Amorphous silicon film
5 Titanium nitride film
6 Tungsten film
7, 30 First hydrogen diffusion suppression film
8, 31 First silicon nitride film
9 Resist pattern
10, 25 Gate electrode
11, 26 Second hydrogen diffusion suppressing film
12, 27 Second silicon nitride film
13, 28 Side wall
14a, 14b, 32a, 32b LDD region
15, 33 source area
16, 34 drain region
24 polysilicon film
29 Silicided portion of gate electrode

Claims (15)

A gate insulating film formed on a semiconductor substrate,
A gate electrode formed on the gate insulating film;
A first silicon nitride film formed so as to cover at least an upper surface of the gate electrode;
Sidewalls formed of a second silicon nitride film on both side surfaces of the gate insulating film and the gate electrode;
Hydrogen diffusion suppressing means for suppressing hydrogen atoms generated in one or both of the first silicon nitride film and the sidewall from diffusing into the gate insulating film and the gate electrode. Semiconductor device. The hydrogen diffusion suppressing means,
A first hydrogen diffusion suppressing film formed between the gate electrode and the first silicon nitride film so as to suppress diffusion of hydrogen atoms generated in the first silicon nitride film into the gate electrode; When,
A second hydrogen diffusion formed between the gate insulating film and the gate electrode and the sidewall to suppress diffusion of hydrogen atoms generated in the sidewall into the gate insulating film and the gate electrode; The semiconductor device according to claim 1, further comprising a suppression film. The first hydrogen diffusion suppressing film and the first silicon nitride film are formed so as to match the gate electrode;
3. The semiconductor device according to claim 2, wherein the sidewall is formed so as to cover side surfaces of the gate insulating film, the gate electrode, the first hydrogen diffusion suppressing film, and the first silicon nitride film. The first hydrogen diffusion suppression film is formed so as to cover the semiconductor substrate, the gate electrode, the second hydrogen diffusion suppression film, and the sidewall,
3. The semiconductor device according to claim 2, wherein said first silicon nitride film is formed so as to cover said first hydrogen diffusion suppressing film. A gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a first silicon nitride film covering at least an upper surface of the gate electrode, and a second silicon nitride film on a side surface of the gate electrode. A method of manufacturing a semiconductor device having at least a sidewall formed of a silicon nitride film,
(A) forming hydrogen diffusion suppressing means for suppressing diffusion of hydrogen atoms generated in one or both of the first silicon nitride film and the sidewall to the gate insulating film and the gate electrode; A method for manufacturing a semiconductor device, comprising: The step (A) comprises:
(A) forming a first hydrogen diffusion suppressing film for suppressing diffusion of hydrogen atoms generated in the first silicon nitride film into the gate electrode between the gate electrode and the first silicon nitride film; The process of
(B) a second hydrogen diffusion suppressing film for suppressing diffusion of hydrogen atoms generated in the sidewall between the gate insulating film and the gate electrode and the sidewall to the gate insulating film and the gate electrode; 6. The method for manufacturing a semiconductor device according to claim 5, further comprising the step of: The step (a) includes:
A step of sequentially stacking the gate insulating film, a conductor film serving as the gate electrode, the first hydrogen diffusion suppressing film, and the first silicon nitride film on the semiconductor substrate; Forming a resist pattern on the silicon nitride film, and performing etching using the resist pattern as a mask to form the gate insulating film, the gate electrode, the first hydrogen diffusion suppressing film, and the first silicon nitride film; Forming a laminate of the film,
The step (b) comprises:
A step of covering the laminate obtained in the step (a) with the second hydrogen diffusion suppression film, a step of covering the second hydrogen diffusion suppression film with the second silicon nitride film, Anisotropic etching is performed on a second hydrogen diffusion suppressing film and the second silicon nitride film, and the second silicon nitride film is formed on a side surface of the stacked body via the second hydrogen diffusion suppressing film. Forming a sidewall of the semiconductor device. A step of stacking the gate insulating film and a silicon conductive film to be the gate electrode on the semiconductor substrate, a step of forming a resist pattern on the silicon conductive film, and using the resist pattern as a mask Performing etching to form a stacked body of the gate insulating film and the gate electrode, and further comprising a step of silicidizing a part of an upper surface side of the gate electrode,
The step (b) comprises:
A step of covering the stacked body with the second hydrogen diffusion suppressing film, a step of covering the second hydrogen diffusion suppressing film with the second silicon nitride film, and a step of covering the second hydrogen diffusion suppressing film and the second Performing anisotropic etching on the silicon nitride film to form sidewalls of the second silicon nitride film on the side surfaces of the stacked body via the second hydrogen diffusion suppressing film. ,
The step (a) includes:
Covering the stacked body, the second hydrogen diffusion suppressing film and the sidewall obtained in the step (b) with the first hydrogen diffusion suppressing film, 7. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of covering the first hydrogen diffusion suppression film. The first hydrogen diffusion suppressing film and the second hydrogen diffusion suppressing film are silicon nitride films, and are formed by using a silicon source gas containing no bond between silicon atoms and hydrogen atoms and a nitrogen source gas. Filmed,
7. The film according to claim 6, wherein the first silicon nitride film and the second silicon nitride film are formed using a silicon source gas containing a bond of a silicon atom and a hydrogen atom and a nitrogen source gas. Manufacturing method of a semiconductor device. The manufacturing method of a semiconductor device according to claim 9, wherein the silicon source gas not containing a bond between silicon atoms and hydrogen atoms is a gas containing tetrachlorosilicon (SiCl ₄ ) or hexachlorodisilane (Si ₂ Cl ₆ ). 11. Method. The gas according to claim 9, wherein the nitrogen source gas is a gas containing at least one of ammonia (NH ₃ ), monomethylamine (CNH ₅ ), hydrazine (N ₂ H ₄ ), or one of their derivatives. The manufacturing method of the semiconductor device described in the above. The source gas of silicon containing a bond between a silicon atom and a hydrogen atom is a gas containing at least one of SiH ₂ Cl ₂ , SiH ₂ [NH (C ₄ H ₉ )] ₂ , and SiH _4. Item 10. A method for manufacturing a semiconductor device according to item 9. The first hydrogen diffusion suppression film is a silicon nitride film formed at a film formation temperature higher than the film formation temperature of the first silicon nitride film;
7. The method of manufacturing a semiconductor device according to claim 6, wherein the second hydrogen diffusion suppression film is a silicon nitride film formed at a film formation temperature higher than a film formation temperature of the second silicon nitride film. The first hydrogen diffusion suppression film and the second hydrogen diffusion suppression film are formed at a deposition temperature of 750 to 800 ° C., and the first silicon nitride film and the second silicon nitride film are 14. The method for manufacturing a semiconductor device according to claim 13, wherein the film is formed at a film formation temperature of 400 to 650 ° C. The method of manufacturing a semiconductor device according to claim 7, wherein the conductor film serving as the gate electrode is formed by stacking a plurality of types of metal films.

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