JP2004302510A - Data processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing device that reduces the number of computing elements used for wavelet lifting computation and shortens total processing time to the utmost, especially in a data processing device used for two-dimensional discrete wavelet transformation. <P>SOLUTION: The data processing device comprises one or more computing elements for feeding back computation result data on input computational data to perform lifting computation and outputting the computation result data, in a period wherein computational data and computation result data can be once read from and written into a memory respectively. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data processing device that performs an operation according to a lifting method, and particularly to a data processing device that performs a wavelet transform used in JPEG2000.
[0002]
[Prior art]
In recent years, JPEG2000 has been receiving attention as a compression / expansion method for high-definition images. According to the JPEG2000, a two-dimensional discrete wavelet transform is performed on image data. When the wavelet transform is performed by an operation according to a lifting method defined by the JPEG2000 standard (referred to as a wavelet lifting operation), the amount of operation is reduced. .
[0003]
A data processing device that performs the wavelet lifting operation is disclosed in, for example, Patent Document 1 below.
[0004]
[Patent Document 1]
JP-A-2002-19775 [0005]
FIG. 5 is a diagram showing a circuit configuration of a conventional data processing device 200 that performs a wavelet lifting operation. The data processing device 200 performs wavelet transform using an IR9: 7 filter, that is, image data of nine consecutive pixels for calculating a low-pass wavelet transform coefficient, and image of seven consecutive pixels for calculating a high-pass wavelet transform coefficient. A wavelet lifting operation is performed using the data.
[0006]
Each of the arithmetic units 210, 220, 230 and 240 has the same configuration, and adds data obtained by adding data obtained by multiplying (weighting) image data of pixels input before and after a specified number to image data of a target pixel. Output.
[0007]
The arithmetic unit 210 includes two adders 210a and 210c and one multiplier 210b. Image data of the X (2n + 2) th pixel read from a memory (not shown) is input to a terminal A of the arithmetic unit 210, and X (2n) temporarily recorded by the registers 211 and 212 is input to a terminal B. The image data of the X-th pixel is input to the terminal C, and the image data of the X (2n + 1) -th pixel temporarily recorded by the register 211 is input to the terminal C. Inside the arithmetic unit 210, the adder 210a calculates the sum of the image data of the X (2n + 2) th and X (2n) th pixels input to the terminals A and B, and the multiplier 210b outputs the output of the adder 210a. , And the adder 210c adds the image data of the X (2n + 1) -th pixel of interest input to the terminal C to the value multiplied by α by the multiplier 210b, and adds the added value to Y (2n + 1). ) Output as the data of the result of the wavelet lifting calculation in step S1.
[0008]
The data of the Y (2n + 1) -th wavelet lifting check result obtained in step S1 obtained in the above-described computing unit 210 is input to terminal A of computing unit 220, and is temporarily recorded in terminal B by register 221 in terminal B. The Y (2n-1) -th data is input, and the same image data of the X (2n) -th pixel as input to the terminal B of the arithmetic unit 210 in the preceding stage is input to the terminal C. The arithmetic unit 220 multiplies the sum of the Y (2n + 1) -th and Y (2n-1) -th data input to the terminal A and the terminal B by β, and further inputs the sum to the terminal C by the β-multiplied value. The value obtained by adding the image data of the X (2n) th pixel of interest is output as the data of the wavelet lifting operation result of the Y (2n) th step S2.
[0009]
The data of the Y (2n) -th step S2 wavelet lifting verification result obtained in the arithmetic unit 220 is input to the terminal A of the arithmetic unit 230, and the data is temporarily recorded by the register 231 in the terminal B. The Y (2n-2) -th data is input, and the same Y (2n-1) -th data as that input to the terminal B of the preceding computing unit 210 is input to the terminal C. The arithmetic unit 230 multiplies the sum of the Y (2n) -th and Y (2n-2) -th data input to the terminal A and the terminal B by γ, and further, Y (2n-1) input to the terminal C The value obtained by adding the data of interest is output as the data of the result of the wavelet lifting operation in the Y (2n-1) th step S3.
[0010]
The data of the Y (2n-1) -th wavelet lifting check result obtained in the arithmetic unit 230 is input to the terminal A of the arithmetic unit 240, and the data is temporarily recorded by the register 241 to the terminal B. The Y (2n−3) th data is input to the terminal C, and the same Y (2n−2) th data as input to the terminal B of the arithmetic unit 230 in the previous stage is input to the terminal C. The arithmetic unit 240 multiplies the sum of the Y (2n−1) th and Y (2n−3) th data input to the terminal A and the terminal B by σ, and furthermore, Y (2n−) input to the terminal C. The value obtained by adding the 2) th data of interest is output as the data of the Y (2n-2) th wavelet lifting calculation result in step S4.
[0011]
A high-pass component of a wavelet coefficient obtained by multiplying the data of the Y (2n-1) -th wavelet lifting operation result output from the arithmetic unit 230 in step S3 by -K by the multiplier 232 (wavelet lifting operation result in step S5) Write to a memory (not shown) as -KY (2n-1).
[0012]
Further, a value obtained by multiplying the data of the wavelet lifting calculation result of the Y (2n-2) -th step S4 output from the calculator 240 by 1 / K by the multiplier 242 is a low-pass component of the wavelet coefficient (the wavelet lifting in step S6). The result is written into a memory (not shown) as 1 / KY (2n-2) and output.
[0013]
In the data processing device 200 having the above configuration, for example, when the calculation of step S1 is completed for the image data of the X1th pixel, and when the calculation of step S2 is performed using the data obtained by the calculation of step S1, the following X2 The operation of step S1 can be performed on the image data of the ith pixel. The same can be said for the other steps S2, S3, S4.
[0014]
FIG. 6A is a diagram illustrating the highest throughput of the data processing device 200. T1 to t6 described above represent one cycle period of the drive clock signal. As shown in the figure, in the data processing device 200 having the above configuration, the wavelet lifting calculation result of the final step S6 can be obtained from the wavelet lifting calculation result of step S1 in four cycles. Also, once the calculation is started, the result of the wavelet lifting calculation in the final step S6 for the image data of the next pixel can be obtained one after another without a pause.
[0015]
[Problems to be solved by the invention]
Reading image data for calculation from the memory requires one cycle of the driving clock signal, but writing data of the calculation result to the memory also requires one cycle of time. Therefore, the image data can be read out only every other cycle. Therefore, in practice, as shown in FIG. 6B, the result of the wavelet lifting calculation in the final step S6 for the image data of the next pixel can be obtained only every other cycle.
[0016]
That is, in the conventional data processing apparatus 200, although processing can be performed at higher speed, half of the processing efficiency is reduced due to the restriction on reading the image data for calculation from the memory and writing the data of the calculation result into the memory. Was working on.
[0017]
In addition, the conventional data processing device 200 has a problem that the scale of the data processing device 200 is large because the operation of each step is performed by four dedicated arithmetic units. If one arithmetic unit is shared by time-division processing, the number of arithmetic units to be used can be reduced. However, in this case, the processing time is extended four times or more.
[0018]
The present invention relates to a data processing apparatus used for performing the two-dimensional discrete wavelet transform, wherein the number of arithmetic units used for performing a wavelet lifting operation is reduced, and the data processing apparatus is capable of reducing the overall processing time as much as possible. It is intended to provide a device.
[0019]
[Means for Solving the Problems]
The first data processing device of the present invention performs the operation on the input operation data during a period in which the operation data can be read from the memory and the operation result data can be written to the memory once. It is characterized in that one or more arithmetic units are provided which perform lifting-type arithmetic by feeding back the arithmetic result data and output the arithmetic result data.
[0020]
According to a second data processing device of the present invention, in the first data processing device, when two or more arithmetic units are provided, the output terminal of the arithmetic unit located at the preceding stage and the signal input of the arithmetic unit located at the subsequent stage are provided. A gate is provided between the terminals, the gate being opened for a predetermined time in a period in which data can be read from the memory and data can be written to the memory once.
[0021]
The third data processing device of the present invention is characterized in that, in the second data processing device, when three or more arithmetic units are provided and two or more gates are provided between the arithmetic units, the third data processing device is viewed from a signal input side. The timing of opening and closing the odd-numbered gate and the even-numbered gate is set opposite.
[0022]
A fourth data processing device according to the present invention is characterized in that, in the second data processing device, a wavelet transform conforming to JPEG2000 is executed.
[0023]
According to a fifth data processing device of the present invention, in the above fourth data processing device, data in which wavelet coefficient data of one or more LL subbands of each level are mixed as data for calculation in addition to image data. It is characterized by processing.
[0024]
According to a sixth data processing device of the present invention, in the above-described fourth data processing device, data obtained by converting image data into data of three color components obtained by performing color conversion, wherein data of each color component is mixed. The method is characterized in that data is processed as data for calculation.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit diagram of a data processing device 100 that performs a wavelet lifting operation. The data processing apparatus 100 has the highest throughput with only two arithmetic units (conventionally four, see FIG. 5) for a normal memory system that reads image data X once every two cycles of the drive clock signal. Specifically, it is designed so as to obtain the throughput shown in FIG. 6B described in the section of the related art.
[0026]
Hereinafter, after describing the configuration of the data processing apparatus 100, the actual operation will be described separately for the timings (timing A and timing B) of two drive clock signals. Timing A refers to a period of an odd cycle of the drive clock signal. Timing B refers to a period of an even cycle of the drive clock signal.
[0027]
Image data for calculation read out from a memory (not shown) and input to the data processing device 100 is input to a signal input terminal 111 b of a multiplexer (denoted as MUX in the figure) 111 and also via a register 112. The signal is input to the signal input terminal 115 b of the multiplexer 115, and further input to the signal input terminal 114 b of the multiplexer 114 via the register 113.
[0028]
The signal fed back from the output terminal D of the arithmetic unit 110 is input to the other signal input terminal 111a of the multiplexer 111. The signal fed back from the output terminal D of the arithmetic unit 110 is input to the other signal input terminal 114a of the multiplexer 114 after being temporarily recorded by the register 117. The output signal of the multiplexer 114 is input to the other signal input terminal 115a of the multiplexer 115.
[0029]
The multiplexers 111, 114 and 115 pass the signals input to the lower input terminals 111b, 114b and 115b in the figure at timing A, and the signals input to the upper input terminals 111a, 114a and 115a at timing B. Through.
[0030]
The arithmetic unit 110 is composed of two adders 110a and 110c and one multiplier 110b whose magnification is switched to α or β every cycle of the drive clock signal. In the arithmetic unit 110, the adder 110a and the multiplier 110b multiply the sum of the image data on both sides of the target pixel input to the terminal A and the terminal B by α at the timing A and β by the timing B. The adder 110c adds the α- or β-multiplied value to the image data of the target pixel input from the terminal C, and outputs the added value. Switching of the magnification is performed according to the drive clock signal.
[0031]
The output terminal D of the arithmetic unit 110 is connected to the gate 121 which closes at the timing A and opens at the timing B. The output of the gate 121 is connected to a delay circuit 122 that delays the input signal by one cycle of the driving clock signal and outputs the delayed signal. The output of the delay circuit 122 is connected to the signal input terminal 123b of the multiplexer 124 and also to the signal input terminal 125b of the multiplexer 125 via the register 124. The signal fed back from the output terminal D of the arithmetic unit 120 is input to the remaining signal input terminal 123a of the multiplexer 123. The signal that has been fed back from the output terminal D of the arithmetic unit 120 is input to the other signal input terminal 125 a of the multiplexer 125 via the register 128. The output signal of the multiplexer 125 is input to the signal input terminal 127a of the multiplexer 127, and the signal output from the multiplexer 114 is input to the other signal input terminal 127b of the delay circuit 126 for one cycle of the driving clock signal. Input with only a delay.
[0032]
The multiplexers 123, 125, and 127 pass the signals input to the upper input terminals 123a, 125a, and 127a at the timing A, and the signals input to the lower input terminals 123b, 125b, and 127b at the timing B. Through.
[0033]
The arithmetic unit 120 has the same configuration as that of the arithmetic unit 110, and multiplies the sum of the data before and after the target data input to the terminals A and B by σ at the timing A, and multiplies the sum of the terminals C by γ at the timing B. The value of the input data of interest is added and output.
[0034]
The output terminal D of the arithmetic unit 120 is connected to the signal input terminal 129a of the multiplexer 129. The multiplexer 129 outputs a signal from the output terminal 129c to the multiplier 131 at the timing A, and outputs a signal from the output terminal 129b to the multiplier 130 at the timing B.
[0035]
Hereinafter, the processing performed by the data processing apparatus 100 having the above configuration at the timing A will be described. FIG. 2 is a diagram in which only components effective at timing A are extracted and displayed from the circuit diagram of the data processing device 100 shown in FIG.
[0036]
At timing A, the wavelet lifting operation of step S1 is executed in the operation unit 110 in the preceding stage, and the wavelet lifting operation in steps S4 and S6 is executed in the operation unit 120 in the subsequent stage.
[0037]
At timing A, the image data of the X (2n + 1) -th pixel of interest is input to the signal input terminal C of the arithmetic unit 110, and the signal input terminal A of the X (2n + 2) -th pixel located before the pixel of interest. The image data of the pixel is input, and the image data of the X (2n) -th pixel located after the pixel of interest is input to the signal input terminal B. The arithmetic unit 110 obtains Y (2n + 1) = X (2n + 1) + α (X (2n) + X (2n + 2)) as the data of the wavelet lifting operation in step S1 of the Y (2n + 1) -th data, and outputs the obtained data. I do.
[0038]
On the other hand, in the subsequent operation unit 120 in which data input from the operation unit 110 is cut off by the gate 121, the Y (2n−2) th data is input to the signal input terminal C as data of interest, and the signal input terminal A , The Y (2n-1) th data located before the data of interest is input, and the Y (2n-3) th data located after the data of interest is input to the signal input terminal B. The data input to the signal input terminal A is data of the result of the wavelet lifting operation in step S3 output from the arithmetic unit 120 at a timing B described later. The arithmetic unit 120 calculates Y (2n−2) = Y (2n−2) + σ (Y (2n−1) + Y (2n−3)) as the data of the wavelet lifting calculation in the Y (2n−2) th step S4. And outputs the obtained data.
[0039]
Further, the data output from the arithmetic unit 120 is multiplied by 1 / K by the multiplier 131 as a wavelet lifting operation in step S6, and written into a memory (not shown) as high-pass component data of the wavelet coefficient (data of the operation result).
[0040]
Subsequently, the processing performed by the data processing device 100 at the timing B will be described. FIG. 3 is a diagram in which only the components that function effectively at the timing B are extracted and displayed from the circuit diagram of the data processing device 100 illustrated in FIG.
[0041]
At the timing B, the wavelet lifting operation in step S2 is executed in the operation unit 110 in the preceding stage, and the wavelet lifting operation in steps S3 and S5 is executed in the operation unit 120 in the subsequent stage.
[0042]
At the timing B, the image data of the X (2n) -th pixel located after the pixel of interest at the immediately preceding timing A is input to the signal input terminal C of the arithmetic unit 110 as the data of interest. , The Y (2n + 1) th data located before the target data is input, and the Y (2n−1) th data located after the target data is input to the signal input terminal B. The arithmetic unit 110 obtains Y (2n) = X (2n) + β (Y (2n−1) + Y (2n + 1)) as the data of the wavelet lifting operation in the Y (2n) -th step S2, and outputs the obtained data. I do.
[0043]
At the timing B, the gate 121 is open, and the Y (2n) -th data output from the arithmetic unit 110 is delayed by one cycle of the driving clock signal by the delay circuit 122, and then the data immediately before the target data is obtained. Is input to the signal input terminal A of the arithmetic unit 120. The Y (2n−2) th data is input to the signal input terminal B as data immediately after the target data. The Y (2n-1) -th data is input to the signal input terminal C as the data of interest. The arithmetic unit 120 obtains Y (2n-1) = Y (2n-1) + γ (Y (2n-2) + Y (2n)) as data of the Y (2n-1) th wavelet lifting operation in step S3. And output the obtained data.
[0044]
The data output from the arithmetic unit 120 is further multiplied by −K by the multiplier 130 and written to a memory (not shown) as low-pass component data (data of a calculation result) of the wavelet coefficient obtained by the wavelet lifting calculation in step S5. .
[0045]
FIG. 4 is a diagram showing the highest throughput realized in the data processing device 100 having the above configuration. T1 to t6 described above represent one cycle of the drive clock signal. As shown in the figure, the data processing device 100 can obtain the final wavelet lifting operation result in step S6 from the wavelet lifting operation result in step S1 in four cycles. Further, once the calculation is started, the result of the wavelet lifting calculation in the final step S6 for the image data of the next pixel can be obtained every other cycle of the drive clock signal.
[0046]
4 is the same as the achievable throughput (see FIG. 6B) of the data processing device 200 described in the section of the related art with reference to FIG. That is, in the data processing apparatus 100, the same throughput can be obtained even though the number of arithmetic units is reduced to half and the circuit scale is reduced as compared with the conventional data processing apparatus 200. You can do it. This is because the processing speed is doubled by executing the wavelet lifting operation of the next step without resting the two arithmetic units while writing the data of the result of the wavelet lifting operation to the memory (not shown). Because it is.
[0047]
In addition, in the data processing device 100, after the calculations in steps S1 and S2 for the image data of a certain pixel are completed, image data of another pixel completely unrelated to the image data of the processed pixel can be input. Therefore, after all the image data is processed by the data processing apparatus 100 and converted into wavelet coefficients of level 1, the processing of the image data proceeds to some extent in addition to processing all the data of the 1LL subband by the data processing apparatus 100. At this stage, wavelet coefficients of the 1LL subband may be processed to obtain level 2 wavelet coefficients. The same applies to higher levels. As described above, the data processing device 100 can process data in which wavelet coefficient data of one or more LL subbands of each level in addition to image data are mixed as calculation data. Level of wavelet coefficients can be obtained more quickly.
[0048]
Further, after converting the image data into three color components of Y, Cr, and Cb, the data of each color component may be processed as one block in the data processing device 100, or may be data of the Y component, data of the Cr component, and data of the Cb. Processing may be performed in parallel in the order of the component data. As described above, in the data processing apparatus 100, data obtained by converting image data into three color component data obtained by performing color conversion, and in which data of each color component are mixed, is processed as calculation data. This has the advantage that the wavelet coefficients of the desired color component can be obtained more quickly.
[0049]
The data processing apparatus 100 that performs the IR9: 7 filter processing has been described above. However, during the period in which the reading of the calculation data from the memory and the writing of the calculation result data to the memory can be performed once, the input calculation The data processing apparatus according to the present invention, which has a basic concept of providing at least one arithmetic unit for performing a lifting method operation by feeding back data of the operation result performed on the data of the above and outputting the data of the operation result By applying the configuration described above, it is also possible to configure an IR5: 3 filter and a decoder that can perform quick processing with a small number of arithmetic units.
[0050]
【The invention's effect】
The data processing device of the present invention performs the operation by the lifting method by feeding back the first operation result data within the time required to read the operation data from the memory and write the operation result data to the memory. Thus, the same throughput can be realized with half the number of arithmetic units as compared with a data processing circuit of a type that performs one operation continuously for each cycle of the drive clock signal.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a data processing device.
FIG. 2 is a diagram showing components operating at a timing A in the data processing device.
FIG. 3 is a diagram showing components operating at a timing B in the data processing device.
FIG. 4 is a diagram illustrating a throughput of the data processing device.
FIG. 5 is a circuit diagram of a conventional data processing device.
FIG. 6A is a diagram showing the theoretical maximum throughput of a conventional data processing apparatus, and FIG. 6B is a diagram showing the throughput actually obtained from the restriction on the timing of reading and writing data to and from a memory. FIG.
DESCRIPTION OF SYMBOLS 100 data processing device, 110, 120 arithmetic unit, 111, 114, 115, 123, 125, 127 multiplexer, 112, 113, 117, 124, 128 register, 122, 126 delay circuit

Claims (6)

During the period in which the operation data can be read from the memory and the operation result data can be written to the memory once, the operation result data input to the input operation data is fed back to the lifting method. A data processing device comprising one or more arithmetic units for performing an operation and outputting data of the operation result. The data processing device according to claim 1,
When two or more arithmetic units are provided, data is read from the memory and data is written to the memory between the output terminal of the arithmetic unit located at the preceding stage and the signal input terminal of the arithmetic unit located at the subsequent stage. A data processing device comprising a gate that opens for a fixed time within a period in which each can be performed once. The data processing device according to claim 2,
When three or more arithmetic units are provided and two or more gates are provided between the arithmetic units, the timing of opening and closing the odd-numbered gate and the even-numbered gate when viewed from the signal input side is opposite. Data processing device set to. 3. The data processing apparatus according to claim 2, wherein the data processing apparatus executes a wavelet transform based on JPEG2000. The data processing device according to claim 4,
A data processing device for processing data in which wavelet coefficient data of one or more LL subbands of each level in addition to image data are mixed as calculation data. The data processing device according to claim 4,
A data processing apparatus for processing data obtained by converting image data into data of three color components obtained by performing color conversion, wherein data in which data of each color component is mixed is processed as calculation data.

Images