KR100628441B1 - Apparatus for lifting discrete wavelet transform of JPEG2000 - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a JPEG2000 lifting discrete wavelet transform apparatus capable of processing a lifting discrete wavelet transform in real time while reducing the size of hardware compared to conventional structures. A horizontal module for performing filtering on the row direction of the first level of the transform; And a vertical module for performing filtering on the signal from the horizontal module in both the row direction and the column direction of the second level or more, as well as filtering in the column direction of the first level.

Lifting Discrete Wavelet Transform, Real Time, Horizontal Filter, Vertical Filter, Processing Unit

Description

Lifting Discrete Wavelet Transformer of XP2000

1 is a view for explaining a conventional lifting step,

2 is a view for explaining a lifting step for a conventional (5,3) filter,

3 is a view for explaining a lifting step for a conventional (9,7) filter,

4 is a view for explaining the configuration of a processing unit for a conventional lifting operation,

5 is a block diagram of a lifting discrete wavelet converter of JPEG2000 according to an embodiment of the present invention;

6 is a schematic configuration diagram of a processing unit applied to the present invention;

7 is a diagram illustrating an internal configuration of the horizontal filter illustrated in FIG. 5;

8 is a view for explaining a lifting operation for the (9,7) / (5,3) filter applied to the present invention,

9 is a table showing a calculation procedure of the horizontal filter shown in FIG.

FIG. 10 is a diagram illustrating arithmetic scheduling in the vertical module shown in FIG. 5;

11 is a calculation timing diagram of even rows of the vertical module illustrated in FIG. 5;

12 is an internal configuration diagram of the signal buffer shown in FIG. 5;

FIG. 13 is a diagram illustrating an internal configuration of the vertical filter illustrated in FIG. 5;

14 is an internal configuration diagram of the first processing unit in the vertical filter shown in FIG. 13;

* Explanation of symbols for main parts of the drawings

20: horizontal module 22: splitter

24: horizontal filter 30: vertical module

32: signal buffer 34: vertical filter

40, 41, 62, 64, 86, 88, 192, 195: multiplexer

Pipeline registers 42, 43, 51, 52, 60, 61, 142, 145, 148, 149, 152, 155, 158, 193

44, 53, 63, 120, 191, 194: multiplier

48, 49, 57, 58, 126, 130: adder

50, 59, 128: Delay register 70: First buffer

72, 74, 76, 78: second buffer 80, 82: third buffer

84: register 90, 92, 94, 96: processing unit

The present invention relates to a lifting discrete wavelet transform apparatus of JPEG2000, and more particularly to a lifting discrete wavelet transform for a bi-orthogonal (9,7) / (5,3) filter of JPEG2000. Relates to a device.

JPEG2000, which performs compression based on the Discrete Wavelet Transform (DWT), provides greater functionality and efficiency than JPEG, which performs compression based on the Discrete Cosine Transform (DCT). On the other hand, execution time has increased. In particular, the discrete wavelet transform of JPEG2000 requires extensive operations because it is implemented using filter banks.

In order to further reduce such a large amount of computation, a lifting based discrete wavelet transform method has been proposed. Lifting operations include many advantages, including fast calculations, integer-to-integer conversion, and easy inverse implementation. Due to these advantages, JPEG2000 supports lifting filtering methods in addition to the convolution method for discrete wavelet transform operations.In the default mode, the irreversible transform uses a biorthogonal (9,7) filter and a reversible transform. To do this, use the (5,3) filter. However, since the discrete wavelet transform of JPEG2000 must be processed in both the row direction and the column direction, sophisticated hardware is essential for real time processing.

Mallet has developed one- and two-dimensional wavelet transform algorithms. In the case of two-dimensional wavelet transform, the first image is divided into two subbands (low frequency (L), high frequency) by filtering and downsampling in the row direction. These two subbands are again divided into four subbands (low-low frequency (LL), low-frequency (LH), high-frequency-low frequency (HL) by filtering and downsampling in the column direction. ), And high frequency (HH)). Multilevel segmentation of more than two levels is performed repeatedly with the low frequency-low frequency band instead of the input image. As a result, the input image (J = 0, J represents the number of division levels of the wavelet transform) is divided into 3J +1 subbands at the J level, and the size of each subband is ( N × N) / 4 ^J decreases in size.

And, lifting theory was proposed by I. Daubeches and W. Sweldens to efficiently calculate filter banks, and split the discrete wavelet transform operations into simple filtering steps. Lifting steps are performed in three steps, as shown in FIG. 1, split, predict, and update.

 In the dividing step, the input signals X are divided into even samples Xeven and odd samples Xodd. In the prediction step, even samples Xeven are used to predict odd samples Xodd, and a high frequency coefficient is calculated by calculating a difference between the odd samples Xodd and the prediction values. In the update step, the low frequency coefficients are calculated using the high frequency coefficients provided in the prediction step.

The lifting discrete wavelet transform calculation for the biorthogonal (9,7) / (5,3) filter used in JPEG2000 can be expressed by the following equation (1).

Formula (1)

d ⁰ (i) = X (2i + 1), s ⁰ (i) = X (2i)

d ¹ (i) = d ⁰ (i) + α (s ⁰ (i) + s ⁰ (i + 1)), s ¹ (i) = s ⁰ (i) + β (d ¹ (i-1) + d ¹ (i))

d ² (i) = d ¹ (i) + γ (s ¹ (i) + s ¹ (i + 1)), s ² (i) = s ¹ (i) + δ (d ² (i-1) + d ² (i))

H (i) = d (i) = d ¹ (i) L (i) = s (i) = s ¹ (i) for (5,3) filter

= (1 / ζ) d ² (i) = ζs ² (i) for (9,7) filter

α = -0.5 β = 0.25 for (5,3) filter

  = -1.586134342 = -0.0529811854 for (9,7) filter

γ = 0.8829110762, δ = 0.4435068522, ζ = 1.149604398

In Equation (1), X (n) represents an input sequence and n = 0,1,2, ... N for N input sequences. In the case of i, i = 0, 1, 2, ... N / 2. D (i) denotes a high frequency result by a prediction step, and s (i) denotes a low frequency result by an update step.

In Equation (1), ζ and 1 / ζ represent a scaling factor, which is 1 for the (5,3) filter. In the case of the (5,3) filter, as shown in FIG. 2, the low frequency and high frequency results can be calculated using one prediction step and the update step, whereas the (9,7) filter performs the prediction step and the update step once more as shown in FIG. By calculating the high frequency and low frequency results.

Assuming that even and odd samples are input simultaneously for each cycle, the processing unit structure for each lifting step calculation is shown in FIG.

The processing element (PE) of FIG. 4 for the lifting operation is composed of one multiplier 10 and two adders 11 and 12, and one multiplier 10 and two adders 11. , 12) has a critical path. The critical path is a path between a register and a register or a path between an input and an output.

As such, the conventional VLSI structures for the two-dimensional lifting discrete wavelet transform used in JPEG2000 are classified into three types.

The first structure is a single one-dimensional discrete wavelet module consisting of two processing units (PE) to perform a row (column) operation to store in the external memory, and read it back to the same module It performs column (row) direction operation, and after the one level operation is completed, the next level is also performed in the same way, it requires an external memory of N ² size for the N ㅧ N image.

The second structure uses two discrete wavelet modules consisting of two processing units (row direction and column direction) to perform operations on one level of discrete wavelets simultaneously in the row direction and in the column direction. after performing all of the operations and a structure for performing the following operation level it needs the N ^2/4 size of the memory module of the.

The third structure implements the Recursive Pyramid Algorithm (RPA) using two discrete wavelet modules (row and column) each consisting of four processing units. The iterative pyramid algorithm structure uses only line memories without external memory but has twice the processing units (ie eight processing units) compared to the second structure due to the low hardware availability.

SUMMARY OF THE INVENTION The present invention has been proposed in view of the above-mentioned conventional circumstances, and an object of the present invention is to reduce the discrete discrete wave of JPEG2000 in real time to handle the discrete discrete wavelet transform while reducing the size of hardware compared to the conventional structures. To provide a lett inverter.

In order to achieve the above object, a lifting discrete wavelet transform apparatus of JPEG2000 according to a preferred embodiment of the present invention performs filtering on a row direction of a first level of lifting discrete wavelet transform on an input video signal. Horizontal module; And a vertical module for performing filtering on the signal from the horizontal module in both the row direction and the column direction of the second level or more, as well as filtering in the column direction of the first level.

Hereinafter, a lifting discrete wavelet converter of JPEG2000 according to an embodiment of the present invention will be described with reference to the accompanying drawings.

5 is a block diagram of a lifting discrete wavelet converter of JPEG2000 according to an embodiment of the present invention. The apparatus of the present invention comprises: a horizontal module 20 for performing filtering on a row direction of a first level of a lifting discrete wavelet transform on an input video signal; And a vertical module 30 that performs filtering on the signal from the horizontal module 20 in both the row direction and the column direction of the second level or more, as well as the filtering in the column direction of the first level.

The apparatus of FIG. 5 performs wavelet transform of the image in the vertical direction after wavelet transform of the image in the horizontal direction. The wavelet transform results in the horizontal direction are divided into L (low frequency) bands and H (high frequency) bands. The wavelet transform results in the vertical direction with respect to the L (low frequency) bands are LL (low frequency to low frequency) and LH ( The wavelet transform results in the vertical direction with respect to the H (high frequency) band are divided into HL (high frequency-low frequency) bands and HH (high frequency-high frequency) bands. That is, the result of the 1 level (J = 1) wavelet transform means LL (low frequency-low frequency), LH (low frequency-high frequency), HL (high frequency-low frequency), and HH (high frequency-high frequency). Here, the low frequency band has almost image information, and the high frequency result has information about a rapidly changing region such as an edge of the image. As an example, the LH result has a low frequency component in the horizontal direction and a high frequency component in the vertical direction. Compression using a wavelet transform such as JPEG2000 performs compression by allocating a lot of bits in a low frequency region having a lot of image information and a few bits in a high frequency region having almost no image information except an edge.

In FIG. 5, the horizontal module 20 includes: a splitter 22 which receives image inputs in every cycle in series and outputs two parallel data once in two clock cycles; And a horizontal filter 24 for performing a discrete wavelet transform operation in a row direction using two parallel data provided from the splitter 22 to output a low frequency result value L or a high frequency result value H. .

The horizontal filter 24 has two processing units internally for the lifting operation, which basically has one multiplier 14, two adders 15, 16 and state variables as shown in FIG. It consists of a register 17 for storage. In this case, the delay register 17 has two registers connected in series and has a propagation delay of two cycles.
The multiplier 14 multiplies the even-numbered outputs of the previous lifting step (prediction, update) by the filter coefficients α or β or γ or δ used in the current lifting step calculation.
The adder 15 adds the odd-numbered outputs of the previous lifting step (prediction, update) and the output of the multiplier 14 to output a current state variable, and the adder 16 outputs from the multiplier 14. The data value and the previous state variable inputted through the delay register 17 are added to perform a predetermined output calculation.
Since the critical path in the processing unit of FIG. 6 is a path from the even-numbered input signal PE_In (even) to the output signal PE_Out after passing through the multiplier 14 and the adder 16, the processing of FIG. The unit has a critical path of one multiplier and one adder. The critical path refers to the largest path among the path between the register and the register or the path between the input and the output.

In the case of the processing unit shown in FIG. 6, the following equation (2) is applied to the lifting step calculation.

Formula (2)

d ⁰ (i) = X (2i + 1), s ⁰ (i) = X (2i)

d ¹ (i) = αs ⁰ (i + 1) + q ₀ (i-1), s ¹ (i) = βd ¹ (i) + q ₁ (i-1)

q ₀ (i) = αs ⁰ (i + 1) + d ⁰ (i + 1), q ₁ (i) = βd ¹ (i) + s ⁰ (i + 1)

d ² (i) = γs ¹ (i + 1) + q ₂ (i-1), s ² (i) = δd ² (i) + q ₃ (i-1)

q ₂ (i) = γs ¹ (i + 1) + d ¹ (i + 1), q ₃ (i) = δd ² (i) + s ¹ (i + 1)

H (i) = d (i) = d ¹ (i) L (i) = s (i) = s ¹ (i) for (5,3) filter

= (1 / ζ) d ² (i) = ζs ² (i) for (9,7) filter

Equation (2) is obtained by decomposing Equation (1) using the state variable q (i), where X (n) represents an input sequence and n = 0, for N input sequences. 1,2, ... N. In the case of i, i = 0, 1, 2, ... N / 2. D (i) denotes a high frequency result by a prediction step, and s (i) denotes a low frequency result by an update step. In Equation (2), α, β, γ, and δ are filter coefficients, ζ and 1 / ζ represent scaling factors, and (1) for the filter (5, 3).

Since the horizontal module 20 performs the filtering operation with two columns (even and odd columns) of the image as in Equation (2), and the raster scan image is sequentially input. There is a need for a converter that converts the sequential data of the image into two parallel data. That is, the splitter 22 in the horizontal module 20 receives image inputs in every cycle in series and sends two parallel data to the horizontal filter 24 once in two clock cycles. The two parallel data from the splitter 22 are updated every two cycles of the wavelet converter frequency, and the horizontal filter 24 takes two columns (even and odd columns) of the image from the splitter 22. The above equation (2) is performed. Since the discrete wavelet transform operation requires both a high frequency result and a low frequency result, the horizontal filter 24 calculates a high frequency result or a low frequency result every cycle.

The internal configuration of the horizontal filter 24 will be described in more detail, as shown in FIG. 7. That is, in FIG. 7, the horizontal filter 24 includes an input image (X (n ₁ , 2n ₂ +1)) provided from the splitter 22 and a first feedback signal (from the pipeline register 60). A multiplexer 40 for receiving and multiplexing the signal); A multiplexer 41 for receiving and multiplexing an input image (X (n ₁ , 2n ₂ )) provided from the splitter 22 and a second feedback signal (signal from a pipeline register 61); A pipeline register (42) installed at an output of the multiplexer (40) to receive and store an output signal from the multiplexer (40) at every clock pulse; A pipeline register (43) installed at an output of the multiplexer (41) for receiving and storing an output signal from the multiplexer (41) at every clock pulse; A first processing unit (100) (PE0) which receives a signal from the pipeline registers (42, 43) and performs a calculation of a lifting prediction step; A pipeline register (51) for outputting after receiving the output signal of the pipeline register (43) every clock pulse; A pipeline register (52) for outputting the output signal (out) from the first processing unit (100) after receiving it every clock pulse; A second processing unit (110) (PE1) for receiving a signal from the pipeline registers (51, 52) and performing a calculation of a lifting update step; A pipeline register (60) which receives an output signal of the pipeline register (52) after every clock pulse and outputs it, but feeds the output signal as a first feedback signal to the multiplexer (40); After receiving the output signal (out) from the second processing unit 110 every clock pulse and outputting to the multiplexer 62 at the next stage, the output signal as the second feedback signal to the multiplexer 41 A pipeline register 61 fed back to; A multiplexer (62) for receiving and multiplexing signals from the pipeline registers (52, 61); A multiplier 63 for multiplying an output signal of the multiplexer 62 by a scaling factor ζ or 1 / ζ; And a multiplexer 64 for multiplexing the output signal of the multiplexer 62 and the output signal of the multiplier 63 according to a control signal 9_7sel.

In FIG. 7, X (n ₁ , n ₂ ) represents an input image, and n ₁ = 0,1, ... N-1, n ₂ = 0,1, ... N− for an N × N image. 1 Here, n ₁ means row and n ₂ means column. X (n ₁ , 2n ₂ +1) represents odd columns (1, 3, 5, 7, 9, ...) in the row direction, and X (n ₁ , 2n ₂ ) represents even columns (0, 2) in the row direction , 4, 6, ...), where (n ₁ = 0,1, ... N-1, n ₂ = 0,1, ... (N / 2) -1) to be. 9_7sel is a control signal according to whether the filter is to be used as a (9,7) filter or a (5,3) filter. In FIG. 7, when the horizontal filter is used as the (9,7) filter, 9_7sel is "1". 5,3) 9_7sel is "0" when used as a filter.

In addition, in FIG. 7, the signals H / L (n ₁ , n ₂ ) output from the multiplexer 64 are divided into two subbands (high frequency (H) and low frequency (L) by discrete wavelet transformation in the row direction. ), Where n ₁ = 0, 1, ... N-1, n ₂ = 0, 1, ... (N / 2) -1.

On the other hand, the first processing unit 100, the input terminal is connected to the output terminal of the pipeline register 43, the multiplier 44 for applying a filter coefficient (α or γ) to the input signal; An adder 48 for adding the output signal of the pipeline register 42 and the output signal of the multiplier 44; A delay register 50 composed of two registers for delaying the transfer signal q (i) (also referred to as a state variable) of the adder 48 by two clock cycles; An adder 49 is added to output the predetermined output signal out by adding the output signal of the multiplier 44 and the output signal of the delay register 50. Here, it may be said that the first processing unit 100 has a critical path of one multiplier and one adder.

The second processing unit (110) includes: a multiplier (53) for applying a filter coefficient (β or δ) to an input signal having an input terminal connected to an output terminal of the pipeline register (52); An adder (57) for adding the output signal of the pipeline register (51) and the output signal of the multiplier (53); A delay register 59 composed of two registers for delaying the transfer signal q (also referred to as a state variable) of the adder 57 by two clock cycles; And an adder 58 for adding the output signal of the multiplier 53 and the output signal of the delay register 59 to output a predetermined output signal out. Here, the second processing unit 110 can be said to have a critical path of one multiplier and one adder.

Thus, the above-described horizontal filter 24 is equipped with two processing units 100 and 110, specifically three multipliers 44, 53, 63, four adders 48, 49, 57, 58, It includes four registers 50, 59 for storing state variables, and six registers 42, 43, 51, 52, 60, 61 for the pipeline.

The horizontal filter 24 configured as described above operates according to the lifting calculation method of FIG. 8 and the calculation sequence of FIG. 9. That is, the first processing unit 100 performs the calculation of the lifting prediction step. When the horizontal filter 24 is used as the (5,3) filter in equation (2), only d ¹ (i) is calculated, and in the equation (2) Count up to d ² (i) (ie d ¹ (i) and d ² (i)). Then, the second processing unit 110 performs a calculation of the lifting update step. If horizontal filter 24 is used as filter (5,3) in equation (2), only s ¹ (i) is calculated, and horizontal filter 24 is used as filter (9,7) in equation (2) Count up to s ² (i) (ie s ¹ (i) and s ² (i)).

Fig. 8 shows the lifting operation of the biorthogonal (9,7) / (5,3) filter for input sequence 8 (n = 0, .. 7), and Fig. 9 shows the horizontal filter for size 8 of the image row. Indicates the order of operations. In the present invention, processing of the boundary region of the image is not considered and is assumed to be '0'. The boundary region processing of the image presented by JPEG2000 shows point symmetric extension and periodic symmetric extension, but the extension circuit for boundary region processing is possible outside the wavelet converter. It is not considered in the invention.

In cycle 5, when the input images x (0,4) and x (0,5) from the splitter 22 are input to the horizontal filter 24, the control signals of the multiplexer 40 and the multiplexer 41 are ' 0 'and the output of the multiplexer 40 becomes x (0,5) and the output of the multiplexer 41 becomes x (0,4).

In cycle 6, the output of the pipeline register 42 is x (0,5), and the output of the pipeline register 43 is x (0,4). At this time, the multiplier 44 in the first processing unit 100 (PE0) multiplies the output coefficient x (0,4) of the pipeline register 43 by the filter coefficient α to multiply α * x (0,4). Output The adder 48 adds the output signal x (0,5) of the pipeline register 42 to the output signal of the multiplier 44 and adds the state variable value α * x (0,4) + x (0,5). Calculate the result. In this case, the adder 49 calculates and stores the state variable values α * x (0,2) + x (0,3) and the output of the multiplier 44 before two cycles which are output results from the delay register 50. Calculate d ¹ (0,1) = α * x (0,4) + α * x (0,2) + x (0,3) by adding the signal α * x (0,4).

The calculated value of d ¹ (0,1) becomes the output signal of the pipeline register 52 at the next cycle (that is, cycle 7), and x (0,4), which is the output signal of the pipeline register 43, At the next cycle (i.e., cycle 7), it becomes the output signal of the pipeline register 51.

In the cycle 7, the multiplier 53 in the second processing unit 110 (PE1) multiplies the output coefficient d ¹ (0,1) of the pipeline register 52 by the filter coefficient β and β * d ¹ (0, Output 1). The adder 57 adds the output signal x (0,4) of the pipeline register 51 to the output signal of the multiplier 53 and adds the state variable value β * d ¹ (0,1) + x (0,4). Calculate the result. At this time, the adder 58 calculates and stores the state variable values β * d ¹ (0,0) + x (0,2) and the multiplier 53 before two cycles, which are output results from the delay register 59. S ¹ (0,1) = β * d ¹ (0,1) + β * d ¹ (0,0) + x (0,2) by adding the output signal β * d ¹ (0,1) do.

When the horizontal filter 24 operates as a (5,3) filter (control signal 9_7sel = '0' of the multiplexer 64), the output (d ¹ (0,1)) of the pipeline register 52 is The control signal of the multiplexer 62 becomes '0' and becomes an H (0,1) output value, and the output s ¹ (0,1) of the adder 58 becomes a pipeline register (i.e., cycle 8) at the next cycle. 61), and the control signal of the multiplexer 62 becomes '1' and becomes an L (0,1) output value.

When the horizontal filter 24 is used as the (9,7) filter, the value s ¹ (0,1), which is an output signal of the adder 58 at cycle 8, becomes an output signal of the pipeline register 61, and thus the multiplexer ( 41, and the value d ¹ (0, 1), which is an output signal of the pipeline 52, becomes an output signal of the pipeline register 60 and is fed back to the multiplexer 40. At this time, the control signal of the multiplexer 40 and the multiplexer 41 is '1', the output of the multiplexer 40 is d ¹ (0,1), the output of the multiplexer 41 is s ¹ (0, 1)

In cycle 9, the output of the pipeline register 42 is d ¹ (0, 1), and the output of the pipeline register 43 is s ¹ (0, 1). At this time, the multiplier 44 in the first processing unit 100 (PE0) multiplies the output coefficient s ¹ (0,1) of the pipeline register 43 by the filter coefficient γ to γ * s ¹ (0,1). ) The adder 48 adds the output signal d ¹ (0,1) of the pipeline register 42 to the output signal of the multiplier 44 and adds the state variable value γ * s ¹ (0,1) + d ¹ ( 0,1) Calculate the result. In this case, the adder 49 calculates and stores the state variable value γ * s ¹ (0,0) + d ¹ (0,0) and the multiplier 44 before two cycles which are output results from the delay register 50. Add γ * s ¹ (0,1) output signal of d ² (0,0) = γ * s ¹ (0,1) + γ * s ¹ (0,0) + d ¹ (0,0) Calculate

The calculated value of d ² (0,0) becomes the output signal of the pipeline register 52 at the next cycle (ie, cycle 10), and s ¹ (0,1) which is the output signal of the pipeline register 43. Becomes the output signal of the pipeline register 51 at the next cycle (ie cycle 10).

In the cycle 10, the multiplier 53 in the second processing unit 110 (PE1) multiplies the output coefficient d ² (0,0) of the pipeline register 52 by the filter coefficient δ to δ * d ² (0, Output 0). The adder 57 adds the output signal s ¹ (0,1) of the pipeline register 51 to the output signal of the multiplier 53, thereby adding the state variable value δ * d ² (0,0) + s ¹ (0). 1) Calculate the result. In this case, the adder 58 calculates and stores the state variable value s ¹ (0,0) calculated before two cycles, which is an output result from the delay register 59, and δ * d ² (0, which is an output signal of the multiplier 53). S ² (0,0) = δ * d ² (0,0) + s ¹ (0,0) is calculated.

At this time, the output d ² (0,0) of the pipeline register 52 becomes the H (0,0) output value because the control signal of the multiplexer 62 becomes '0', and the output s ² of the calculated adder 58 is calculated. (0,0) becomes the output of the pipeline register 61 at the next cycle (ie, cycle 11), and at this time, the control signal of the multiplexer 62 becomes '1' and becomes an L (0,0) output value.

As such, the horizontal filter 24 sends the high frequency result H or the low frequency result L to the vertical module 30, and the calculated state variables are stored in a register for the next calculation. That is, since the calculated state variables are used after two cycles, each state variable in each processing unit 100, 110 is stored in two registers 50, 59.

In the vertical module 30, the row direction operation is performed using two column data, while the column direction operation is performed using the low frequency and high frequency results of the two rows. That is, in the case of the first level of operation, the low-frequency and high-frequency results of the even-numbered rows of the image cannot be performed in the column direction only, and the low-frequency and high-frequency results of the odd rows must be useful before the operation in the column direction can be performed. have. As such, the even-numbered row periods in which the first level of operations cannot be performed may be used to perform operations of the second level or more (RPA). Unlike the horizontal module 20, the vertical module 30 simultaneously calculates and outputs a low frequency output and a high frequency output for each cycle, and uses the following computational scheduling.

1) When the horizontal module 20 sends L and H output results for odd rows of an image, the vertical module 30 performs the first level column direction.

2) When the horizontal module 20 exports L and H output results for even rows of an image, the vertical module 30 performs row and column operations in the second level or more.

2a) When the horizontal module 20 exports the output result for 2 ^(J-1) k + (2 ^(J-1) -2) rows of the image, the vertical module 30 performs the J th level row direction operation. To perform. (J> 1) (K = 0,1,2,…)

2b) When the horizontal module exports the output result for 2 ^J k + (2 ^(J-1) -2) rows of the image, the vertical module 30 performs the J th level columnwise operation. (J> 1) (K = 0,1,2,…)

Operation scheduling for the three-level wavelet transform operation of the vertical module 30 operating as described above is illustrated in FIG. 10, where each symbol is a row or column operation for one row of each level. Indicates.

When the horizontal module 20 calculates the output for the even-numbered rows of the image, the vertical module 30 performs the second level or more operations at the same timing as in FIG. 11.

The vertical module 30 includes: a signal buffer 32 for temporarily buffering signals necessary for column-level operation of the first level and row and column-direction operations of the second level or more; And four processing units connected in a mutual pipeline form, wherein the first processing unit performs the calculation of the first lifting prediction step on the signal from the signal buffer 32, and the second processing unit performs the first processing. The operation of the first lifting update step is performed on the signal from the unit, the third processing unit performs the second lifting prediction step on the signal from the second processing unit, and the fourth processing unit is the third processing unit. A vertical filter 34 is provided which performs the operation of the second lifting lifting update step on the signal from the processing unit.

The signal buffer 32 stores intermediate signal results and outputs these results to the vertical filter 34. The internal configuration of the signal buffer 32 is shown in FIG.

The signal buffer 32 of FIG. 12 includes a first buffer 70 for storing high frequency and low frequency output results from the horizontal module 20 for even rows of an input image; Two subbands ((LL) ^J-1 H (n ₁ , n ₂ ) and (LL) ^J- by discrete wavelet transform in the row direction of the second level or more (J> = 2) fed back and inputted. Second buffers 72, 74; 76, 78 for storing even and odd rows of ¹ L (n ₁ , n ₂ )) (J>1); Third buffers 80, 82 for separately storing the result of even and odd columns of one subband (LL) ^J (J> 0) in one row by discrete wavelet transform in the column direction fed back and inputted ); A register for temporarily storing high and low frequency output results from the horizontal module 20 for odd rows of _two subbands H / L (n ₁ , n ₂ ) by discrete wavelet transform in the row direction. (84); Signals for odd rows of (LL) ^J-1 L (n ₁ , n ₂ ) and (LL) ^J-1 H (n ₁ , n ₂ ) bands output from buffers 76 and 78 in the second buffer. And a multiplexer (86) for receiving and multiplexing the output signal of the register (84) and the odd-numbered columns of the (LL) ^J row output from the buffer (80) in the third buffer. And (LL) ^J-1 L (n ₁ , n ₂ ), (LL) ^J-1 H (outputted from the output signal from the first buffer 70 and the buffers 72 and 74 in the second buffer. n ₁ , n ₂ ) and a multiplexer 88 which receives and multiplexes the signal for the even row of the band and the (LL) ^{J one} even column of the signal output from the buffer 82 in the third buffer. Here, J represents the number of division levels of the wavelet transform.

The buffers 72 and 74 in the second buffer are divided into two subbands ((LL) ^J-1 L (n ₁ , n ₂ ), (LL) Stores even rows of ^J-1 H (n ₁ , n ₂ )) (J> 1), and the buffers 76 and 78 in the second buffer are fed back to the second level or more in the row direction. Odd rows of _two subbands ((LL) ^J-1 L (n ₁ , n ₂ ), (LL) ^J-1 H (n ₁ , n ₂ )) (J> 1) by discrete wavelet transform of Save it.

The buffer 80 in the third buffer stores the result of odd columns of one subband LL ^J (J> 0) by the discrete wavelet transform in the column direction fed back and inputted, The buffer 82 in the third buffer stores the result of even columns of one subband LL ^J (J> 0) by the discrete wavelet transform in the column direction fed back and input.

In Fig. 12, the register 84 is a propagation delay register and represents one register. Thus, there is a delay of one clock cycle.

In FIG. 12, the first buffer 70 has an N size because it stores the high frequency and low frequency output results, which are the result of the one-level row direction for one row, and has a second buffer (72, 74; 76, 78) and a second buffer. The three buffers 80 and 82 are used for wavelet calculations of two or more levels and have sizes N / 2 (= N / 4 + (N / 8) + ... (N / 2 ^J )) (J> 1). .

If the horizontal module 20 outputs the high frequency result value H and the low frequency result value L for the odd row of the image, the vertical filter 34 outputs the high frequency or low frequency result of the corresponding column of the previous even row. It reads from the first buffer 70 ((L / H) e row buffer) and outputs high frequency-low frequency (HL), high frequency-high frequency (HH), or low frequency-low frequency (LL) and low frequency-high frequency (LH) results. . The calculated low-low frequency results are stored in the third buffer 80, 82 (LL buffer) for the second level of calculation.

On the other hand, if the horizontal module 20 outputs the high frequency result value H and the low frequency result value L for even rows, the vertical filter 34 has a row direction of a second level or more in accordance with the above-described calculation scheduling. Performs column and column operations.

The vertical filter 34 has a pipeline structure as shown in FIG. 13.

The vertical filter 34 of FIG. 13 includes a signal L / H (2n ₁ + 1, n ₂ ) / LL (n ₁ , 2n ₂ +1) and a signal from the multiplexer 86 of the signal buffer 32. The signal L / H (2n ₁ , n ₂ ) / LL (n ₁ , 2n ₂ ) from the multiplexer 88 of the signal buffer 32 is input to calculate the first lifting prediction step. A first processing unit (90) which performs to calculate a predetermined high frequency result value (d ¹ (i) in Equation (2)); A second low-frequency result value (s ¹ (i) in Equation (2)) is calculated by receiving a signal from the first processing unit 90 and performing a calculation of the first lifting update step. Processing unit 92; A third that receives a signal from the second processing unit 92 and performs a second lifting prediction step to calculate a predetermined high frequency result value (d ² (i) in Equation (2)) Processing unit 94; A fourth low-frequency result value (s ² (i) in Equation (2)) is calculated by receiving a signal from the third processing unit 94 and performing a second lifting update step operation. Processing unit 96; A pipeline register (142) for providing a signal at the first output terminal of the first processing unit (90) to the first input terminal of the second processing unit (92) at every clock pulse; A pipeline register (145) for providing a signal of the second output terminal of the first processing unit (90) to the second input terminal of the second processing unit (92) at every clock pulse; A pipeline register (148) for providing a signal of the first output terminal of the second processing unit (92) to the first input terminal of the third processing unit (92) at every clock pulse; A pipeline register (149) for providing a signal at the second output terminal of the second processing unit (92) to the second input terminal of the third processing unit (94) at every clock pulse; A pipeline register 152 for providing a signal at the first output terminal of the second processing unit 94 to the first input terminal of the fourth processing unit 96 at every clock pulse; A pipeline register 155 which receives the second output terminal signal of the third processing unit 94 and provides it to the second input terminal of the fourth processing unit 96; A pipeline register 158 for outputting after receiving the first stage output signal of the fourth processing unit every clock pulse; A pipeline register 193 for outputting after receiving a signal at the second output terminal of the fourth processing unit 96 every clock pulse; A multiplier (191) for multiplying an output signal of the pipeline register (158) by a predetermined scaling factor (1 / ζ); The output signal of the pipeline register 148 and the output signal of the multiplier 191 are input and multiplexed according to the control signal 9_7sel to generate a high frequency and low frequency result value (HH / LH (n ₁ , n ₂ ) / (LL). A multiplexer 192 that outputs) H (n ₁ , n ₂ )); A multiplier (194) for multiplying an output signal of the pipeline register (193) by a predetermined scaling factor (ζ); And receiving the output signal of the pipeline register 149 and the output signal of the multiplier 194 and multiplexing according to a control signal 9_7sel to obtain high and low frequency result values (HH / LL (n ₁ , n ₂ ) / ( A multiplexer 195 for outputting LL) L (n ₁ , n ₂ )) is provided.

Then, the processing units in the vertical filter 34 are filter coefficients multiplied by their respective inputs (for the first processing unit 90: α, for the second processing unit 92: β, third processing unit 94). ) Is the same except for [gamma], for the fourth processing unit 96: [delta].

As shown in FIG. 14, the internal structure of the first processing unit 90 has a filter coefficient for the input signal PE_IN (even) (H / L (2n ₁ , n ₂ ) / LL (n ₁ , 2n ₂ )). a multiplier 120 for applying (α); An adder 126 for adding an input signal PE_IN (odd) (H / L (2n ₁ + 1, n ₂ ) / LL (n ₁ , 2n ₂ +1)) and an output signal of the multiplier 120; A delay buffer 127 configured to have a 2N size line buffer to delay the transfer of the output signal qv (also referred to as a vertical state variable) of the adder 126 by 2 ^J N clock cycles during the thermal direction calculation at each level; A delay register 128 composed of one register for delaying the transfer of the output signal q _H (also referred to as a horizontal state variable) of the adder 126 by one clock cycle in a row direction operation; A multiplexer 129 for receiving and multiplexing output signals from the delay buffer 127 and the delay register 128; The adder 130 adds an output signal of the multiplier 120 and an output signal of the multiplexer 129 to output a predetermined output signal out.

In FIG. 14, the delay buffer 127 may be referred to as a 2N size line memory for N * N images.

The first processing unit 90 of the vertical filter 34 described above performs the operation of the first lifting prediction step and calculates d ¹ (i) in equation (2). The second processing unit 92 performs the operation of the first update step and calculates s ¹ (i) in equation (2).

The third processing unit 94 performs the operation of the second lifting prediction step and calculates d ² (i) in equation (2), and the fourth processing unit 96 performs the second update step. Perform the operation of and calculate s ² (i) in equation (2). In the case of the (5,3) filter, only d ¹ (i) and s ¹ (i) are required, so 9_7sel becomes '0' and the result of d ¹ (i) and s ¹ (i) is H (i). And L (i) results, and for the (9,7) filter, 9_7sel is '1' because d ² (i) and s ² (i) results are required, so d ² (i) and s ² ( H (i) and L (i) results are output by multiplying the result of i) by a scaling factor.
The critical paths of the processing units 90, 92, 94, and 96 each include a multiplier 120 for applying a filter coefficient to an even-numbered input signal, an output signal of the multiplier 120, and an output signal of the multiplexer 129. Since the addition is a path from the adder 130 to the output signal, it has a critical path of one multiplier and one adder.

On the other hand, each processing unit 90, 92, 94, 96 in the vertical filter 34 requires one register for the state variables q _H in the row direction, and the state variables q _{V in the} column direction. This requires a 2N (= N + (N / 2) + ... (N / 2 ^J-1 )) sized buffer, because we need to store state variables for one row at every level. As such, the vertical filter 34 includes six multipliers, eight adders, and 8N size buffers, including scaling factors.

As described in detail above, according to the present invention, the use of an external memory for N * N images when the bi-orthogonal (9-7) / (5-3) lifting discrete wavelet transform of JPEG2000 is implemented with the VLSI structure of the present invention. It can be implemented using only 12N (signal buffer: 4N, vertical buffer: 8N) internal line memory, and in the case of bi-orthogonal (9-7), the structure using conventional RPA is processing unit 4 for row direction calculation. While four processing units for column and column operations are used, the structure of the present invention allows row and column operations to be performed in a filter that performs column operations of the first level or more, both in the row and column operations. It has two processing units for processing and four processing units for thermal calculation.

As a result, the conventional RPA-based architecture requires 12 multipliers and 16 adders, including a scaling factor, while the architecture of the present invention requires only 9 multipliers and 12 adders, which consumes less hardware. .

In addition, the processing unit for calculating each lifting step in the present invention has a critical path of one multiplier and one adder, so as to add one adder propagation delay to the conventional critical paths of one multiplier and two adders. Can be reduced.

On the other hand, the present invention is not limited only to the above-described embodiment, but can be modified and modified within the scope not departing from the gist of the present invention, the technical idea to which such modifications and variations are also applied to the claims Must see

Claims (7)

A horizontal module configured to perform filtering on the row direction of the first level of the lifting discrete wavelet transform on the input video signal; And Lifting Discrete Wavelet of JPEG2000, characterized in that it comprises a vertical module for filtering the signal from the horizontal module not only for the first level of the column direction but also for both the row and column direction of the second level or more. Inverter. The method of claim 1, The horizontal module may include: a splitter that receives image inputs for each cycle in series and outputs two parallel data once every two clock cycles; And a horizontal filter for performing a discrete wavelet transform operation using two parallel data provided from the splitter to output a low frequency result value or a high frequency result value. The horizontal filter has two processing units interconnected in the form of a pipeline, Each processing unit comprises a multiplier for multiplying even-numbered input signals by a filter coefficient for each lifting step operation, an adder for adding an odd-numbered input signal and an output signal of the multiplier for calculating a current state variable, and And a delay register for delaying the transfer of the state variable, which is the output signal of the adder, by two clock cycles, and an adder for adding a multiplier output signal and an output signal of the delay register to output a predetermined output signal. Wavelet inverter. The method of claim 2, Among the two processing units, the preceding processing unit performs the calculation of the lifting prediction step, and when the corresponding horizontal filter is used as the (5,3) filter, only d ¹ (i) is calculated in the following equation, and the corresponding horizontal filter is (9 (7) When used as a filter, d ¹ (i) and d ² (i) are calculated in the following equation, and the processing unit at the next stage performs the operation of the lifting update step and the corresponding horizontal filter is the (5,3) filter. when used only counts equation s ¹ (i) below, and characterized in that the horizontal filter (9,7) calculate the equation s ¹ (i) and s ² (i) of the case to be used as a filter JPEG2000 Discrete wavelet inverter. (expression) d ⁰ (i) = X (2i + 1), s ⁰ (i) = X (2i) d ¹ (i) = αs ⁰ (i + 1) + q ₀ (i-1), s ¹ (i) = βd ¹ (i) + q ₁ (i-1) q ₀ (i) = αs ⁰ (i + 1) + d ⁰ (i + 1), q ₁ (i) = βd ¹ (i) + s ⁰ (i + 1) d ² (i) = γs ¹ (i + 1) + q ₂ (i-1), s ² (i) = δd ² (i) + q ₃ (i-1) q ₂ (i) = γs ¹ (i + 1) + d ¹ (i + 1), q ₃ (i) = δd ² (i) + s ¹ (i + 1) H (i) = d (i) = d ¹ (i) L (i) = s (i) = s ¹ (i) for (5,3) filter = (1 / ζ) d ² (i) = ζs ² (i) for (9,7) filter X (n) represents an input sequence and n = 0,1,2, ... N for N input sequences, and i = 0,1,2, .. ..N / 2. The d (i) refers to the high frequency result by the prediction step, and the s (i) represents the low frequency results by the update step. Α, β, γ, and δ are filter coefficients, ζ and 1 / ζ represent scaling factors. The method of claim 1, The vertical module performs a first level columnwise operation when the horizontal module calculates a low frequency or high frequency output for odd rows of an image, and the horizontal module performs a low frequency or high frequency output for even rows of an image. A lifting discrete wavelet transform apparatus of JPEG2000, characterized in that performing a row and column direction calculation of a second level or more when calculating. The method of claim 4, wherein The vertical module includes a signal buffer for temporarily buffering a signal from the horizontal module; And a vertical filter having first to fourth processing units connected in a mutual pipeline form, The first processing unit performs an operation of the first lifting prediction step on the signal from the signal buffer to calculate d ¹ (i) in the following equation, and the second processing unit is obtained from the first processing unit. The first lifting update step is performed on the signal to calculate s ¹ (i) in the following equation, and the third processing unit performs the second lifting prediction step on the signal from the second processing unit. Calculate d ² (i) in the equation, and the fourth processing unit calculates s ² (i) in the following equation by performing a second lifting lifting update operation on the signal from the third processing unit. A lifting discrete wavelet converter of JPEG2000. (expression) d ⁰ (i) = X (2i + 1), s ⁰ (i) = X (2i) d ¹ (i) = αs ⁰ (i + 1) + q ₀ (i-1), s ¹ (i) = βd ¹ (i) + q ₁ (i-1) q ₀ (i) = αs ⁰ (i + 1) + d ⁰ (i + 1), q ₁ (i) = βd ¹ (i) + s ⁰ (i + 1) d ² (i) = γs ¹ (i + 1) + q ₂ (i-1), s ² (i) = δd ² (i) + q ₃ (i-1) q ₂ (i) = γs ¹ (i + 1) + d ¹ (i + 1), q ₃ (i) = δd ² (i) + s ¹ (i + 1) H (i) = d (i) = d ¹ (i) L (i) = s (i) = s ¹ (i) for (5,3) filter = (1 / ζ) d ² (i) = ζs ² (i) for (9,7) filter X (n) represents an input sequence and n = 0,1,2, ... N for N input sequences, and i = 0,1,2, .. ..N / 2. The d (i) refers to the high frequency result by the prediction step, and the s (i) represents the low frequency results by the update step. Α, β, γ, and δ are filter coefficients, ζ and 1 / ζ represent scaling factors. The method of claim 5, The signal buffer comprises: a first buffer for storing high frequency and low frequency output results from the horizontal module for even rows of an input image; Two subbands ((LL) ^J-1 L (n ₁ , n ₂ ) and (LL) ^J-1 H (n ₁ , n by discrete wavelet transform in the row direction of the second level or more fed back and inputted. A second buffer for storing even and odd rows of ₂ )); A third buffer for separately storing the results of the even and odd columns of one subband (LL) ^{J in} one row by the discrete wavelet transformation in the column direction fed back; A register for temporarily storing high frequency and low frequency output results from the horizontal module for odd rows of _two subbands L / H (n ₁ , n ₂ ) by discrete wavelet transformation in a row direction; Signals for odd rows of the (LL) ^J-1 L (n ₁ , n ₂ ), (LL) ^J-1 H (n ₁ , n ₂ ) bands output from the second buffer, the output signal of the register, and A multiplexer configured to receive and multiplex (LL) ^J odd-numbered columns of signals output from the third buffer; And even rows of the output signal from the first buffer and the (LL) ^J-1 L (n ₁ , n ₂ ) and (LL) ^J-1 H (n ₁ , n ₂ ) bands output from the second buffer. And a multiplexer configured to receive and multiplex a signal for (LL) ^{J and} an even column of one row output from the third buffer. J represents the number of division levels of the wavelet transform. The method of claim 5, Each of the first to fourth processing units includes a multiplier for applying filter coefficients to even-numbered input signals, an adder for adding odd-numbered input signals and output signals of the multiplier to calculate state variables, and an N × N image size. It is composed of a line buffer of 2N size and delay buffer which delays the output signal of the adder for 2N clock cycle during each level column operation, and it is composed of one register and transmits the output signal of the adder 1 cycle for row direction operation. A delay register for delaying, a multiplexer for receiving and multiplexing output signals from the delay buffer and the delay register, and an adder for adding a output signal of the multiplier and an output signal of the multiplexer to output a predetermined output signal. Lifting Discrete Wavelet Inverter of JPEG2000.

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