JP2004289188A - Process for fabricating photoelectric conversion element - Google Patents

Process for fabricating photoelectric conversion element Download PDF

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JP2004289188A
JP2004289188A JP2004210171A JP2004210171A JP2004289188A JP 2004289188 A JP2004289188 A JP 2004289188A JP 2004210171 A JP2004210171 A JP 2004210171A JP 2004210171 A JP2004210171 A JP 2004210171A JP 2004289188 A JP2004289188 A JP 2004289188A
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layer
photoelectric conversion
conversion element
film
thickness
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Katsushi Kishimoto
克史 岸本
Takanori Nakano
孝紀 中野
Hitoshi Sannomiya
仁 三宮
Katsuhiko Nomoto
克彦 野元
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Sharp Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/075Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
    • H01L31/076Multiple junction or tandem solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/075Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • H01L31/204Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System including AIVBIV alloys, e.g. SiGe, SiC
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a photoelectric conversion element exhibiting good interface characteristics to both an oxide based transparent conductive film and a photoelectric conversion layer in which a high conductivity is ensured while suppressing the quantity of light absorption by preventing the film quality of a p-layer from deteriorating due to the discomposition effect of hydrogen from a semiconductor layer of impurities while securing good interface characteristics. <P>SOLUTION: In the process for fabricating a photoelectric conversion element, a p-layer constituting the photoelectric conversion element having a pin junction is formed by depositing a first p-layer 7 having a film thickness of 5 nm or less and added with impurities uniformly, and then depositing a second p-layer 8 on the first p-layer 7 by gas decomposition containing no p-type impurity. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、光電変換素子の製造方法に関し、より詳細には、pin接合を有する光電変換素子の製造方法に関する。   The present invention relates to a method for manufacturing a photoelectric conversion element, and more particularly, to a method for manufacturing a photoelectric conversion element having a pin junction.

pin接合を有する薄膜太陽電池において、光入射側のドープ層は、変換効率(η)を向上させる上で重要な要因の一つとして歴史的にも様々な開発が行われてきた。
特に、光入射側のドープ層の一つであるp層は、アモルファスシリコン系の窓層としての機能を果たすものであるが、光電変換層ではないため、光吸収量を小さくすると同時に、高導電率及び良好なp/i界面特性をもたせるという相反する性能を満足させる必要があり、種々の研究がなされている。
In a thin-film solar cell having a pin junction, a doped layer on the light incident side has been variously developed historically as one of the important factors for improving the conversion efficiency (η).
In particular, the p layer, which is one of the doped layers on the light incident side, functions as an amorphous silicon-based window layer, but is not a photoelectric conversion layer. Therefore, various studies have been made to satisfy the conflicting performances of providing a high efficiency and good p / i interface characteristics.

例えば、p層として、ボロンをドープしたa−SiC膜を用いる方法が、特公平3−40515号公報(特許文献1)及び特公平3−63229号公報(特許文献2)に記載されている。これらの公報では、p層は、シラン又はシラン誘導体(例えば、SiH4)、炭化水素(例えば、CH4)、不活性ガス(例えば、Ar、He)等の混合ガスとともに、B26ガスをグロー放電分解して成膜する方法が記載されており、他にもプラズマ化学気相成長法等が一般に知られている。 For example, a method using a boron-doped a-SiC film as the p layer is described in Japanese Patent Publication No. 3-40515 (Patent Document 1) and Japanese Patent Publication No. 3-63229 (Patent Document 2). In these publications, the p-layer is composed of a B 2 H 6 gas together with a mixed gas such as silane or a silane derivative (eg, SiH 4 ), a hydrocarbon (eg, CH 4 ), or an inert gas (eg, Ar, He). Is described by glow discharge decomposition to form a film. In addition, a plasma chemical vapor deposition method and the like are generally known.

しかし、B26ガスを原料ガスに同時に混入すると、ボロンが、アモルファス中のSi等の結合手を終端している水素を引き抜く。これにより、層中にダングリングボンドと呼ばれる未結合手が多数形成されることとなる。このため、上記方法により成膜されたボロンをドープしたアモルファスシリコン系膜を窓層であるp層に使用した場合には、p層の光吸収量が増加する。 However, when the B 2 H 6 gas is mixed with the source gas at the same time, boron extracts hydrogen terminating the bond such as Si in the amorphous. As a result, a large number of dangling bonds called dangling bonds are formed in the layer. Therefore, when the boron-doped amorphous silicon-based film formed by the above method is used for the p-layer serving as the window layer, the light absorption of the p-layer increases.

そこで、この光吸収量の増加を抑えるために、膜内に数十パーセントまで炭素が導入されるが、この炭素量の増加は、膜質の悪化を招き、よって、導電率が低下し、素子全体の内部抵抗を増加させてしまうという問題がある。
このように、セル特性にシリーズ抵抗を生じさせないような所望の導電率を得ようとすれば、光吸収量が無視できないほど大きくなり、十分な光電流が確保できないという課題がある。
Therefore, in order to suppress the increase in the amount of light absorption, carbon is introduced into the film up to several tens of percent. However, the increase in the amount of carbon causes deterioration of the film quality, and therefore, the conductivity is reduced and the entire device is reduced. However, there is a problem that the internal resistance increases.
As described above, if an attempt is made to obtain a desired conductivity that does not cause series resistance in the cell characteristics, the amount of light absorption becomes so large that it cannot be ignored, and there is a problem that a sufficient photocurrent cannot be secured.

また、プラズマ化学気相成長法においては、プラズマ中のボロンは膜表面の未結合手をも増加させるため、p/i界面に再結合準位を大量に発生させ、変換効率に多大な悪影響を及ぼす。よって、例えば、p層としてボロンをドープしたSiC膜を用いた場合、光電変換層との接合が悪く、発生した光キャリアの再結合中心となり、十分な開放電圧(Voc)やフイルファクター(F.F.)が確保できなくなる。   In addition, in plasma enhanced chemical vapor deposition, boron in the plasma also increases the number of dangling bonds on the film surface, so that a large amount of recombination levels are generated at the p / i interface, which has a great adverse effect on the conversion efficiency. Exert. Therefore, for example, when a boron-doped SiC film is used as the p-layer, the bonding with the photoelectric conversion layer is poor, and it becomes a recombination center of generated photocarriers, and a sufficient open voltage (Voc) and a sufficient fill factor (F. F.) cannot be secured.

そこで、p/i界面に、膜中のC量を緩やかに変化させたアモルファス膜や真性SiC膜をバッファ層として挟み込むことにより、セル特性への影響を緩和する方法が一般的に用いられている。
しかし、これらバッファ層は、導電率が低く、素子の内部抵抗の増加の原因となり、結局F.F.の低下抑制は回避できない。
Therefore, a method is generally used in which an amorphous film or an intrinsic SiC film in which the amount of C in the film is gradually changed is sandwiched as a buffer layer at the p / i interface to reduce the influence on the cell characteristics. .
However, these buffer layers have low conductivity and cause an increase in the internal resistance of the device. F. It is not possible to avoid the suppression of the decrease.

これに対して、特開平7−22638号公報(特許文献3)には、p層の作製方法として、アモルファスボロン層を作製した後にアモルファスシリコン層を積層することにより、p型のアモルファスシリコン層を形成する方法が、Appl. Phys. 36 (1997) 467 (非特許文献1)には、アモルファスボロン層を作製した後にアモルファスカーボンを積層することにより、p層を形成する方法がそれぞれ提案されている。   On the other hand, Japanese Patent Application Laid-Open No. 7-22638 (Patent Document 3) discloses a method of forming a p-type amorphous silicon layer by stacking an amorphous silicon layer after forming an amorphous boron layer. Appl. Phys. 36 (1997) 467 (Non-Patent Document 1) proposes a method of forming an amorphous boron layer and then laminating amorphous carbon to form a p-layer. .

しかし、アモルファスボロン層では、光吸収量を十分小さくすることは依然として困難である。
また、通常、素子形成用基板は、ガラス基板上にSnO2やZnO膜等の酸化物系透明導電膜による凹凸構造をもつものが用いられるが、これら酸化物系透明導電膜上にpin接合を作製する場合においては、特開平7−22638号公報又はAppl. Phys. 36 (1997) 467 におけるアモルファスボロン層と酸化物系透明導電膜との界面抵抗が高くなり、良好な素子特性を得ることは依然として困難である。
However, it is still difficult to sufficiently reduce the amount of light absorbed by the amorphous boron layer.
In general, an element formation substrate having a concavo-convex structure made of an oxide-based transparent conductive film such as a SnO 2 or ZnO film on a glass substrate is used. A pin junction is formed on these oxide-based transparent conductive films. In the case of manufacturing, the interface resistance between the amorphous boron layer and the oxide-based transparent conductive film in JP-A-7-22638 or Appl. Phys. 36 (1997) 467 is high, and good device characteristics cannot be obtained. Still difficult.

このように、上記従来の方法では、p層において、光吸収量が小さく、かつ高導電率を備え、しかも酸化物系透明導電膜や光電変換層の双方に対して良好な界面特性をもつという相反する特性を満足させる技術が実現されていない。   As described above, according to the above-described conventional method, the p layer has a small amount of light absorption, high conductivity, and good interface characteristics with both the oxide-based transparent conductive film and the photoelectric conversion layer. A technology that satisfies conflicting characteristics has not been realized.

特公平3−40515号公報Japanese Patent Publication No. 3-40515 特公平3−63229号公報Japanese Patent Publication No. 3-63229 特開平7−22638号公報JP-A-7-22638 Appl. Phys. 36 (1997) 467Appl. Phys. 36 (1997) 467

本発明によれば、pin接合を有する光電変換素子を構成するp層を、5nm以下の膜厚を有する均一に不純物が添加された第1p層を成膜し、該第1p層上にp型不純物を含まないガス分解によって第2p層を成膜することにより形成することを特徴とする光電変換素子の製造方法が提供される。   According to the present invention, as a p-layer constituting a photoelectric conversion element having a pin junction, a first p-layer having a thickness of 5 nm or less and doped with impurities is formed, and a p-type layer is formed on the first p-layer. There is provided a method for manufacturing a photoelectric conversion element, wherein the second p-layer is formed by forming a second p-layer by gas decomposition containing no impurities.

本発明の光電変換素子の製造方法によれば、pin接合を有する光電変換素子を構成するp層を、5nm以下の膜厚を有する均一に不純物が添加された第1p層を成膜し、該第1p層上にp型不純物を含まないガス分解によって第2p層を成膜することにより形成するため、特別な製造装置及び製造方法を用いることなく、簡便に上記光電変換素子を製造することが可能となる。
また、本発明の製造方法によれば、pin接合を有する光電変換素子を構成するp層が、5nm以下の膜厚を有する均一に不純物が添加された第1p層とp型不純物を含まないガス分解によって形成された第2p層とが積層してなる光電変換素子を製造することができるため、p層において、光吸収量が小さく、かつp層内の不純物によるp層を構成する半導体層からの水素の引き抜き防止により高導電率を確保し、しかもp層の下層及び上層に配設される酸化物系透明導電膜や光電変換層の双方に対して良好な界面特性をもつ光変換素子を実現することができる。さらに、従来使用されていたp層の半導体材料を大幅に変更させることなく、i層中に十分な内部電界を形成させることができ、比較的大きな開放電圧を実現でき、さらに光吸収量の増加抑制により比較的大きな短絡電流を得ることができる。
According to the method for manufacturing a photoelectric conversion element of the present invention, a p-layer constituting a photoelectric conversion element having a pin junction is formed into a first p-layer having a thickness of 5 nm or less and uniformly doped with impurities. Since the second p-layer is formed on the first p-layer by gas decomposition containing no p-type impurity, the photoelectric conversion element can be easily manufactured without using any special manufacturing apparatus and manufacturing method. It becomes possible.
Further, according to the manufacturing method of the present invention, the p-layer constituting the photoelectric conversion element having the pin junction has the uniform p-type impurity-free first p-layer having a thickness of 5 nm or less and the gas containing no p-type impurity. Since a photoelectric conversion element formed by laminating the second p-layer formed by decomposition can be manufactured, the p-layer has a small light absorption amount and is formed from a semiconductor layer constituting the p-layer due to impurities in the p-layer. A photo-conversion element that secures high conductivity by preventing hydrogen from being extracted and has good interface characteristics with both the oxide-based transparent conductive film and the photoelectric conversion layer disposed below and above the p-layer. Can be realized. Furthermore, a sufficient internal electric field can be formed in the i-layer without significantly changing the semiconductor material of the p-layer which has been conventionally used, a relatively large open-circuit voltage can be realized, and the light absorption amount increases. A relatively large short-circuit current can be obtained by suppression.

本発明の製造方法にて製造された光電変換素子は、pin接合を有するものであり、主として透明電極層;5nm以下の膜厚を有する均一に不純物が添加された第1p層とp型不純物を含まないガス分解によって形成された第2p層とが積層してなるp層;i層;n層及び裏面電極層からなり得る。また、これら電極層及びpin接合は、基板上に形成されていることが好ましい。   The photoelectric conversion element manufactured by the manufacturing method of the present invention has a pin junction, and is mainly composed of a transparent electrode layer; a uniformly doped first p layer having a thickness of 5 nm or less and a p-type impurity. A p-layer formed by laminating a second p-layer formed by gas decomposition that does not include the p-layer; an i-layer; an n-layer; and a back electrode layer. Preferably, the electrode layer and the pin junction are formed on a substrate.

本発明において、光電変換素子に用いることができる基板としては、通常、基板として使用されるものであれば特に限定されるものではなく、ステンレス、アルミニウム、銅、亜鉛等の金属からなる基板、ガラス基板、ポリイミド、PET、PEN、PES、テフロン(登録商標)等の樹脂基板、金属基板に樹脂が塗布された基板、樹脂基板に金属層が形成された基板等、種々のものが挙げられる。なかでも透明基板であることが好ましい。なお、この基板は、基板の利用態様に応じて、さらに絶縁膜、金属や半導体等による他の導電膜あるいは配線層、バッファ層等又はこれらが組み合わされて形成された基板であってもよい。基板の厚さは特に限定されるものではないが、適当な強度や重量を有するように、例えば0.1〜30mm程度が挙げられる。また、基板表面には凹凸を有していてもよい。   In the present invention, the substrate that can be used for the photoelectric conversion element is not particularly limited as long as it is generally used as a substrate, and a substrate made of a metal such as stainless steel, aluminum, copper, or zinc, glass Various types of substrates, such as a substrate, a resin substrate such as polyimide, PET, PEN, PES, and Teflon (registered trademark), a substrate in which a resin is applied to a metal substrate, and a substrate in which a metal layer is formed on a resin substrate. Among them, a transparent substrate is preferable. The substrate may be an insulating film, another conductive film made of metal, semiconductor, or the like, a wiring layer, a buffer layer, or a combination thereof, depending on the usage of the substrate. The thickness of the substrate is not particularly limited, but may be, for example, about 0.1 to 30 mm so as to have appropriate strength and weight. Further, the substrate surface may have irregularities.

本発明において、光電変換素子に用いられる透明電極層としては、ZnO、ITO、SnO2 等の導電性酸化物等が挙げられる。これらの電極材料は、単層又は積層層として形成することができる。このような裏面電極の膜厚は、使用する材料等により適宜調整することができるが、例えば、200〜2000nm程度が挙げられる。また、このような透明電極層の表面には、凹凸が形成されていてもよい。凹凸は、例えば、可視光領域の光の波長程度、0.1〜1.2μm程度の高さ、0.1〜10μmのピッチを有するものが挙げられる。 In the present invention, examples of the transparent electrode layer used for the photoelectric conversion element include conductive oxides such as ZnO, ITO, and SnO 2 . These electrode materials can be formed as a single layer or a laminated layer. The thickness of such a back electrode can be appropriately adjusted depending on the material to be used and the like, and for example, about 200 to 2000 nm. In addition, irregularities may be formed on the surface of such a transparent electrode layer. Examples of the unevenness include those having a wavelength of light in a visible light region, a height of about 0.1 to 1.2 μm, and a pitch of 0.1 to 10 μm.

本発明において、光電変換素子のp層は、5nm以下の膜厚を有し、かつ均一に不純物が添加された第1p層とp型不純物を含まないガス分解によって形成された第2p層とが積層されてなり、このような構成により、その下層に形成された透明導電層と良好な界面特性を確保しながら、不純物の水素の引き抜き作用によるp層の膜質低下を抑制することができる。   In the present invention, the p-layer of the photoelectric conversion element has a thickness of 5 nm or less and has a first p-layer uniformly doped with impurities and a second p-layer formed by gas decomposition not containing p-type impurities. With such a configuration, it is possible to suppress deterioration in the quality of the p-layer due to the action of extracting hydrogen as an impurity while securing good interface characteristics with the transparent conductive layer formed thereunder.

上記p層は、第1p層及び第2p層とも、半導体層、特にアモルファス半導体層、例えば、a−Si:H、a−Ge:H、a−SiGe:H等により形成することができる。第1p層と第2p層とは、必ずしも同一半導体層により形成されていなくてもよいが、なかでも、第1p層及び第2p層のいずれも、a−Si:Hであることが好ましい。   The p layer can be formed of a semiconductor layer, particularly an amorphous semiconductor layer, for example, a-Si: H, a-Ge: H, a-SiGe: H or the like, for both the first p layer and the second p layer. The first p-layer and the second p-layer do not necessarily have to be formed of the same semiconductor layer, but it is particularly preferable that both the first p-layer and the second p-layer are a-Si: H.

第1p層において、膜厚が5nm以下とは、第1p層の光学的な吸収量が無視できる範囲の膜厚を意味しており、半導体の1原子層以上の膜が含まれる。また、この膜は全面において均一な膜厚を有していることが好ましいが、例えば、透明電極層の表面に島状に形成されていてもよい。さらに、均一に不純物が添加されているとは、第1p層全体にわたって、所定量の不純物が添加されていることを意味する。つまり、第1p層がシリコン系の層により形成されている場合、第1p層の1原子層中にSiは1022個/cm2存在し、その層中に不純物が1018個/cm2以上存在すれば、キャリア密度は十分である。これは、Si原子10000個に対して、キャリアが1個あればよいことを意味するため、このようなキャリア密度を維持できる程度のキャリア、例えばボロン等のアクセプタが存在するように、膜厚及び不純物濃度を調整することができる。 In the first p-layer, a thickness of 5 nm or less means a thickness in a range where the optical absorption of the first p-layer can be neglected, and includes a film of one or more atomic layers of a semiconductor. Further, this film preferably has a uniform film thickness over the entire surface, but for example, may be formed in an island shape on the surface of the transparent electrode layer. Further, that the impurity is uniformly added means that a predetermined amount of impurity is added over the entire first p-layer. That is, when the first p-layer is formed of a silicon-based layer, there are 10 22 / cm 2 of Si in one atomic layer of the first p-layer, and 10 18 / cm 2 or more of impurities in the layer. If present, the carrier density is sufficient. This means that only one carrier is required for every 10,000 Si atoms. Therefore, the film thickness and the thickness are adjusted so that carriers such as boron, for example, acceptors that can maintain such a carrier density are present. The impurity concentration can be adjusted.

上記のように第1p層が構成されていることにより、後述するi層に十分な内部電界を形成でき、比較的大きな開放電圧が確保でき、光吸収量の増加を抑制できるため比較的大きな短絡電流を得ることができる。
また、第1p層は、後述するように、その表面をプラズマ処理されていてもよい。このようにその表面をプラズマ処理することにより、良好なp/i界面特性をもたせることができる。
Since the first p-layer is configured as described above, a sufficient internal electric field can be formed in an i-layer described later, a relatively large open-circuit voltage can be secured, and an increase in light absorption can be suppressed, so that a relatively large short circuit An electric current can be obtained.
The first p-layer may have its surface plasma-treated as described later. By performing the plasma treatment on the surface in this way, good p / i interface characteristics can be provided.

第2p層において、p型不純物を含まないガス分解によって形成されたp層とは、この層を形成する際にはp型不純物を含まないガス分解によってi層を形成するが、その形成と同時あるいはその後に下層の第1p層からの不純物の拡散及び/又は成膜雰囲気からの不純物の混入により、p型となり得る層を意味する。よって、この第2p層内の第2導電型不純物は、第1p層の不純物濃度よりも小さい。
また、第2p層内の不純物濃度は、均一に拡散しているものでもよいが、第1p層から後述するi層にかけて、徐々に減少していることが好ましい。このように、第2p層内の不純物濃度が徐々に減少している場合には、i層にかけて光吸収係数を徐々に大きくすることができ、つまり、不純物による第2p層からの水素の引き抜き作用を抑制して光吸収量を徐々に小さくすることができ、かつ第2p層の膜質の低下を防止することができる。
また、第2p層は、1層で形成されてもよいが、成膜条件等を変化させた複数層で形成されていてもよい。換言すると、第2p層が、i層に近いほど光吸収係数が大きくなる複数層で構成されていてもよい。このように構成すれば、p/i界面の接合特性をより高める事ができ、F.F.とVocの低下を防止することができ、光電流のp/i界面での再結合確率の減少を実現することができる。
第2p層の膜厚は、特に限定されるものではないが、例えば、1〜200nm程度の膜厚が挙げられる。第2p層が複数層で形成されている場合には、各層の膜厚は、1〜30nm程度であることが好ましい。
In the second p layer, an i layer is formed by gas decomposition not containing a p-type impurity when forming this layer with a p layer formed by gas decomposition not containing a p-type impurity. Alternatively, it means a layer that can become p-type by diffusion of impurities from the lower first p-layer and / or mixing of impurities from the film formation atmosphere thereafter. Therefore, the impurity of the second conductivity type in the second p-layer is lower than the impurity concentration of the first p-layer.
The impurity concentration in the second p-layer may be evenly diffused, but is preferably gradually reduced from the first p-layer to the i-layer described later. As described above, when the impurity concentration in the second p-layer is gradually reduced, the light absorption coefficient can be gradually increased toward the i-layer, that is, the effect of the impurity to extract hydrogen from the second p-layer. And the amount of light absorption can be gradually reduced, and the film quality of the second p-layer can be prevented from deteriorating.
Further, the second p-layer may be formed as a single layer, or may be formed as a plurality of layers with different film-forming conditions or the like. In other words, the second p-layer may be composed of a plurality of layers in which the light absorption coefficient increases as the distance from the i-layer increases. With this configuration, it is possible to further enhance the bonding characteristics at the p / i interface. F. And Voc can be prevented from lowering, and the recombination probability of the photocurrent at the p / i interface can be reduced.
The thickness of the second p-layer is not particularly limited, but may be, for example, about 1 to 200 nm. When the second p-layer is formed of a plurality of layers, the thickness of each layer is preferably about 1 to 30 nm.

また、第2p層は、後述するように、その表面をプラズマ処理されていてもよいし、第2p層が複数層で形成されている場合には、各層の表面がプラズマ処理されていてもよい。なお、複数層のすべての表面がプラズマ処理されていてもよいし、その中の一部の層の表面がプラズマ処理されていてもよい。
本発明において、光電変換素子におけるi層及びn層は、通常、光電変換素子におけるpin接合に使用されるi層及びn層であれば、特に限定されるものではない。例えば、i層及びn層としては、いずれも上述したようなアモルファス層により形成され、i層はキャリアとなる不純物が導入されておらず、n層はドナーとなる不純物、例えばリン、砒素等が1018〜1019cm-3程度で導入された層が挙げられる。これらの膜厚は、光電変換素子により得ようとするエネルギー、p層、n層中等の不純物濃度等により適宜調整することができるが、例えば、それぞれ100〜600nm程度、30〜100nm程度が挙げられる。
Further, as described later, the surface of the second p-layer may be plasma-treated, or when the second p-layer is formed of a plurality of layers, the surface of each layer may be plasma-treated. . Note that all surfaces of the plurality of layers may be plasma-treated, or the surfaces of some of the layers may be plasma-treated.
In the present invention, the i-layer and the n-layer in the photoelectric conversion element are not particularly limited as long as they are the i-layer and the n-layer usually used for the pin junction in the photoelectric conversion element. For example, each of the i-layer and the n-layer is formed of the above-mentioned amorphous layer, the i-layer does not contain an impurity serving as a carrier, and the n-layer contains an impurity serving as a donor, for example, phosphorus or arsenic. A layer introduced at about 10 18 to 10 19 cm −3 is exemplified. These film thicknesses can be appropriately adjusted depending on the energy to be obtained by the photoelectric conversion element, the impurity concentration in the p-layer, the n-layer, and the like, and for example, about 100 to 600 nm and about 30 to 100 nm, respectively. .

また、裏面電極層は、通常電極として使用される導電材料であれば特に限定されることなく、例えば、金、白金、銀、銅、アルミニウム等の金属、上述した導電性酸化物等が挙げられる。これらの膜厚は、光電変換素子の使用態様に応じて適宜選択することができる。
なお、本発明において、光電変換素子は、基板上に、pin接合を1つだけ有していてもよいし、繰り返し複数個有していてもよい。また、pin接合を構成するn層、i層及びp層の全てが非晶質シリコンにより形成していなくてもよく、少なくともn層、i層が非晶質シリコンで形成されていればよい。さらに、透明電極層、p層、i層、n層、裏面電極層の間に、任意にバッファ層、中間層、導電層、絶縁層等をさらに備えていてもよい。
The back electrode layer is not particularly limited as long as it is a conductive material usually used as an electrode, and examples thereof include metals such as gold, platinum, silver, copper, and aluminum, and the above-described conductive oxides. . These film thicknesses can be appropriately selected according to the usage mode of the photoelectric conversion element.
In the present invention, the photoelectric conversion element may have only one pin junction on the substrate, or may have a plurality of repetitions. Further, all of the n-layer, i-layer and p-layer constituting the pin junction need not be formed of amorphous silicon, and it is sufficient that at least the n-layer and i-layer are formed of amorphous silicon. Further, a buffer layer, an intermediate layer, a conductive layer, an insulating layer, and the like may be further provided between the transparent electrode layer, the p layer, the i layer, the n layer, and the back electrode layer.

本発明の光電変換素子の製造方法においては、好ましくはその表面に透明電極層を備えた基板上に、まず、5nm以下の膜厚を有する均一に不純物が添加された第1p層を成膜する。
第1p層は、公知の方法、例えば、SiH4、GeH4、CH4、H2、Ar、He等の原料ガスを用いるCVD法、プラズマCVD法等により形成することができる。p層を構成するp型不純物(ボロン等)は、原料ガスに、例えば、B26ガスを混入して成膜と同時にドーピングしてもよいし、半導体層を形成した後、イオン注入又は熱拡散等の方法によりドーピングしてもよい。
In the method for manufacturing a photoelectric conversion element of the present invention, first, a first p-layer having a thickness of 5 nm or less and uniformly doped with impurities is formed on a substrate having a transparent electrode layer on the surface thereof. .
The first p-layer can be formed by a known method, for example, a CVD method using a source gas such as SiH 4 , GeH 4 , CH 4 , H 2 , Ar, He, a plasma CVD method, or the like. The p-type impurity (boron or the like) constituting the p-layer may be doped simultaneously with the film formation by mixing, for example, B 2 H 6 gas into the source gas, or may be ion-implanted or formed after forming the semiconductor layer. Doping may be performed by a method such as thermal diffusion.

また、第1p層は、上述したようにその表面にプラズマ処理を施してもよい。この際のプラズマは、例えば、H2 、He、Ar等が挙げられる。プラズマ処理の条件は、第1p層がa−Si層により形成されている場合には、例えば、表1のように設定することができる。 Further, the first p-layer may be subjected to a plasma treatment on its surface as described above. The plasma at this time is, for example, H 2 , He, Ar, or the like. When the first p-layer is formed of the a-Si layer, the conditions of the plasma processing can be set, for example, as shown in Table 1.

Figure 2004289188
Figure 2004289188

なお、第1p層がGeを主元素として形成されている場合には、投入電力を低条件で、Cを主元素として形成されている場合には、投入電力を高条件で行うことが適当である。
このようなプラズマ処理により、第1p層中の光吸収係数を増大させることができ、つまり第1p層中の光吸収量増加を抑制できるため、比較的高い短絡電流が得られることとなる。
When the first p layer is formed using Ge as a main element, it is appropriate to perform the input power under a low condition, and when formed using C as a main element, it is appropriate to perform the input power under a high condition. is there.
By such a plasma treatment, the light absorption coefficient in the first p-layer can be increased, that is, the increase in the amount of light absorption in the first p-layer can be suppressed, so that a relatively high short-circuit current can be obtained.

次に、第1p層上にp型不純物を含まないガス分解によって第2p層を成膜する。第2p層を成膜する方法は、原料ガスの中に不純物を含まない以外は、第1p層を形成する方法と同様の方法で形成することができる。
このような方法で成膜することにより、p型の不純物を積極的に含有させないが、下地である第1p層からp型不純物が拡散することにより、結果的に第2p層を形成することができる。また、第1及び第2p層が成膜装置、例えばプラズマCVD装置により成膜される場合であって、第2p層を第1p層と同じチャンバで成膜することにより、雰囲気中に存在する第1p層形成の際のp型不純物の混入により、結果的に第2p層を形成することができる。
Next, a second p-layer is formed on the first p-layer by gas decomposition containing no p-type impurity. The method for forming the second p-layer can be the same as the method for forming the first p-layer except that the source gas does not contain impurities.
By forming a film by such a method, the p-type impurity is not positively contained, but the p-type impurity is diffused from the first p-layer serving as the base, so that the second p-layer can be formed as a result. it can. In the case where the first and second p-layers are formed by a film forming apparatus, for example, a plasma CVD apparatus, the second p-layer is formed in the same chamber as the first p-layer so that the second p-layer exists in the atmosphere. By mixing p-type impurities when forming the 1p layer, the second p layer can be formed as a result.

さらに、この第2p層は、その表面及び/又は所定膜厚を成膜する毎に、得られた第2p層表面にプラズマ処理を施すことが、第2p層の光吸収量を低減することができて好ましい。この際の所定膜厚とは、例えば、1〜30nm程度が挙げられる。
また、所定膜厚毎にプラズマ処理を複数回施す場合には、プラズマ照射時間及び/又は処理時の投入電力を1回目よりも2回目、2回目よりも3回目と、徐々に小さくすることが好ましい。このようなプラズマ処理により、第2p層中の光吸収係数を、i層に近づくにつれて徐々に増大させることができ、つまり第1p層中の光吸収量増加を徐々に抑制できるため、短絡電流を向上できるとともに、Voc及びF.F.の低下を抑制することができる。
Further, the surface of the second p-layer and / or the surface of the obtained second p-layer may be subjected to plasma treatment every time a film having a predetermined thickness is formed, thereby reducing the amount of light absorbed by the second p-layer. It is possible and preferable. The predetermined thickness at this time is, for example, about 1 to 30 nm.
In the case where the plasma processing is performed a plurality of times for each predetermined film thickness, the plasma irradiation time and / or the power input during the processing may be gradually reduced to a second time from the first time and a third time from the second time. preferable. By such a plasma treatment, the light absorption coefficient in the second p-layer can be gradually increased as approaching the i-layer, that is, the increase in light absorption in the first p-layer can be suppressed gradually, so that the short-circuit current can be reduced. Voc and F.I. F. Can be suppressed.

なお、第2p層の形成は、第1p層を形成した成膜装置のチャンバと同一のチャンバで行ってもよい。この場合には、特別なドーピングプロファイルを設計することなく、光吸収係数を増大させることができ、つまり第1及び第2p層中の光吸収量増加を抑制できるため、ひいては、光電変換素子を簡便に製造することができ、製造コストの大幅な抑制を実現することができる。   Note that the formation of the second p-layer may be performed in the same chamber as the chamber of the film forming apparatus in which the first p-layer is formed. In this case, the light absorption coefficient can be increased without designing a special doping profile, that is, the increase in the amount of light absorption in the first and second p-layers can be suppressed. , And a significant reduction in manufacturing cost can be realized.

また、第2p層の形成は、必ずしも第1p層を形成した成膜装置のチャンバと同一のチャンバでなくてもよく、異なるチャンバで形成してもよい。この場合には、第2p層に過剰の不純物の拡散を及ぼすことがないため、第2p層内の内部電界制御を容易に行うことができる。その結果、i層内に過剰の不純物の拡散を及ぼすことがなく、i層の内部電界を容易に制御することができ、i層内の空間電荷の抑制をもたらすため、光電流の収集効率の増加(F.F.の低下抑制)を実現することができる。
以下に、本発明の光電変換素子の製造方法の実施例を説明する。
Further, the formation of the second p-layer does not necessarily have to be the same as the chamber of the film forming apparatus in which the first p-layer has been formed, and may be formed in a different chamber. In this case, since excessive diffusion of impurities is not applied to the second p-layer, the internal electric field in the second p-layer can be easily controlled. As a result, it is possible to easily control the internal electric field of the i-layer without causing excessive diffusion of impurities into the i-layer, and to suppress the space charge in the i-layer. An increase (suppression of a decrease in FF) can be realized.
Hereinafter, examples of the method for manufacturing a photoelectric conversion element of the present invention will be described.

[実施の形態1:p層の光吸収量の評価]
まず、プラズマ気相成長装置におけるチャンバ内の基板支持体上に、透明ガラス基板を載置し、この透明ガラス基板上にSiH4:B26:H2=1:0.1:20の原料ガスを200sccmの流量で供給した。この際、成膜温度を200℃、基板温度を200℃、投入電力を200Wとし、10分間成膜し、ボロンが高濃度でドープされた高ドープp型a−Si層を作製した。得られた高ドープp型a−Si層は、光吸収量が無視できる膜厚、ここでは2nm程度の膜厚に設定した。
[Embodiment 1: Evaluation of light absorption amount of p-layer]
First, a transparent glass substrate is placed on a substrate support in a chamber of a plasma vapor deposition apparatus, and SiH 4 : B 2 H 6 : H 2 = 1: 0.1: 20 on the transparent glass substrate. The source gas was supplied at a flow rate of 200 sccm. At this time, the film formation temperature was set to 200 ° C., the substrate temperature was set to 200 ° C., the input power was set to 200 W, and the film was formed for 10 minutes to produce a highly doped p-type a-Si layer doped with boron at a high concentration. The thickness of the obtained highly doped p-type a-Si layer was set to a thickness where the amount of light absorption was negligible, in this case, a thickness of about 2 nm.

続いて、同一チャンバで、SiH4:H2=100:200sccmの原料ガスを用いて、ボロンをドープしないa−Si層を10nm程度の膜厚で成膜した。この際、a−Si層は、このa−Si層の下地の高ドープp型a−Si層からボロンが拡散するか、あるいは雰囲気ガス中のボロンの混入により、p型となる。 この方法を繰り返して約10nmのa−Si層ごとに約2nmの高ドープp型a−Si層が積層された総膜厚300nmのp層を成膜した。 Subsequently, in the same chamber, an a-Si layer not doped with boron was formed to a thickness of about 10 nm using a source gas of SiH 4 : H 2 = 100: 200 sccm. At this time, the a-Si layer becomes p-type due to the diffusion of boron from the highly doped p-type a-Si layer underlying the a-Si layer or the incorporation of boron in the atmosphere gas. By repeating this method, a p-layer having a total thickness of 300 nm was formed by laminating a highly doped p-type a-Si layer of about 2 nm for every about 10 nm of a-Si layer.

また、比較のため、上記とは別に、透明ガラス基板上に、SiH4:B26:H2=100:5:200の混合ガスで成膜した300nmの膜厚の単一のp層を成膜した。
これら2種のp層を用いて、各層の光吸収量及び導電率を測定した。その結果を図1に示す。
For comparison, a single p-layer having a thickness of 300 nm was formed on a transparent glass substrate with a mixed gas of SiH 4 : B 2 H 6 : H 2 = 100: 5: 200. Was formed.
Using these two types of p layers, the amount of light absorption and the electrical conductivity of each layer were measured. The result is shown in FIG.

光吸収量は、図1から明らかなように、高ドープp層/p層の繰り返しp層においては、通常の単一のp層に比較して小さいことがわかる。これは、高ドープp層/p層の繰り返しp層では、p層成膜時にボロンの水素引き抜き効果がないためであると考えられる。
導電率は各層とも5×10-4S/cm程度でほぼ同じ値であった。
As is clear from FIG. 1, the light absorption amount is smaller in a highly doped p layer / p layer repeated p layer than in a normal single p layer. This is presumably because the repeated p-layer of the highly doped p-layer / p-layer does not have the effect of extracting hydrogen from boron when the p-layer is formed.
The conductivity of each layer was about 5 × 10 −4 S / cm, which was almost the same value.

また、上記においては、高ドープp層/p層の繰り返しp層におけるp層を12nm程度として、10nm程度ごとに2nmの高ドープp層を積層しているが、第1p層を30nm程度以下とした場合には、200℃での成膜で同様の導電率で光吸収量の低減効果が得られることがわかっている。   In the above description, the p-layer in the repetitive p-layer of the highly-doped p-layer / p-layer is about 12 nm, and the highly-doped p-layer of 2 nm is laminated every about 10 nm. In this case, it is known that the effect of reducing the amount of light absorption can be obtained at the same conductivity by forming the film at 200 ° C.

[実施の形態2:光電変換素子及びその製造方法]
この実施の形態の光電変換素子は、図2に示したように、透明ガラス基板1上に、透明電極層2、高ドープp型a−Si層7、p型a−Si層8、i層4、n層5及び裏面電極層6が順次形成されて構成されている。
[Embodiment 2: photoelectric conversion element and manufacturing method thereof]
As shown in FIG. 2, the photoelectric conversion element of this embodiment has a transparent electrode layer 2, a highly doped p-type a-Si layer 7, a p-type a-Si layer 8, an i-layer 4, an n layer 5 and a back electrode layer 6 are sequentially formed.

上記光電変換素子の製造方法を、以下に説明する。
まず、透明ガラス基板1上に、膜厚300nm程度の緩やかな凹凸形状を持つZnO膜を膜厚800nm程度で、スパッタリングにより成膜し、透明電極層2を形成する。
続いて、成膜装置におけるp層成膜チャンバ内の基板支持体上に、得られた透明ガラス基板1を載置し、この基板1上に、SiH4:B26:H2=1:0.1:20の混合ガスを200sccmの流量で供給した。この際、成膜温度を200℃、基板温度を200℃、投入電力を200Wとして成膜を行い、第1p層として、ボロンが高濃度でドープされた高ドープp型a−Si層7を膜厚2nm程度で作製した。
The method for manufacturing the photoelectric conversion element will be described below.
First, a transparent electrode layer 2 is formed on a transparent glass substrate 1 by sputtering a ZnO film having a gentle unevenness with a thickness of about 300 nm to a thickness of about 800 nm.
Subsequently, the obtained transparent glass substrate 1 is placed on a substrate support in a p-layer film forming chamber of the film forming apparatus, and SiH 4 : B 2 H 6 : H 2 = 1 : 0.1: 20 mixed gas was supplied at a flow rate of 200 sccm. At this time, film formation was performed at a film formation temperature of 200 ° C., a substrate temperature of 200 ° C., and an input power of 200 W. As a first p layer, a highly doped p-type a-Si layer 7 doped with boron at a high concentration was formed. It was produced with a thickness of about 2 nm.

続いて、同一チャンバでボロンをドープしないa−Si層8を10nm程度の膜厚で成膜した。この際、a−Si層8は、このa−Si層8の下地の高ドープp型a−Si層7からボロンが拡散するか、あるいは雰囲気ガス中のボロンの混入により、p型s−Si層(第2p層)となる。
次いで、a−Si層8上に、i層成膜チャンバにて、SiH4:H2=200:500、投入電力100Wとして膜厚200nm程度のi層4を成膜し、さらに、i層4上に、n層成膜チャンバにて、SiH4:H2:PH3 =10:500:3、投入電力100Wとして膜厚30nm程度のn層5を成膜した。
Subsequently, an a-Si layer 8 not doped with boron was formed to a thickness of about 10 nm in the same chamber. At this time, the p-type s-Si layer 8 is formed by diffusion of boron from the highly doped p-type a-Si layer 7 underlying the a-Si layer 8 or mixing of boron in the atmosphere gas. Layer (second p layer).
Next, an i-layer 4 having a thickness of about 200 nm is formed on the a-Si layer 8 in an i-layer deposition chamber with SiH 4 : H 2 = 200: 500 and an applied power of 100 W. An n-layer 5 having a thickness of about 30 nm was formed on the n-layer deposition chamber with SiH 4 : H 2 : PH 3 = 10: 500: 3 and a power of 100 W.

その後、スパッタ装置にて成膜温度200℃で、500nmのAg膜を成膜し、裏面電極を形成した。
このようにして図2に示すpin接合を有する光電変換素子を作製した。
得られた光電変換素子のI−V特性を評価した。
比較のため、図4に示したように、高ドープp型a−Si層7とp型a−Si層8との代わりに、SiH4:B26:H2=100:5:200の混合ガスで成膜した膜厚10nmの単一のp層を成膜した以外は、上記光電変換素子と同様の構成を有する光電変換素子を作製した。
Thereafter, an Ag film having a thickness of 500 nm was formed at a film forming temperature of 200 ° C. using a sputtering apparatus, and a back electrode was formed.
Thus, a photoelectric conversion element having a pin junction shown in FIG. 2 was manufactured.
The IV characteristics of the obtained photoelectric conversion element were evaluated.
For comparison, as shown in FIG. 4, instead of the highly doped p-type a-Si layer 7 and the p-type a-Si layer 8, SiH 4 : B 2 H 6 : H 2 = 100: 5: 200 A photoelectric conversion element having the same configuration as the above-described photoelectric conversion element was prepared except that a single p-layer having a thickness of 10 nm was formed using a mixed gas of the above.

これら光電変換素子のA.M.1.5下でのI−V特性を図3に示す。
図3から明らかなように、本実施の形態2における光電変換素子では、上記実施の形態1で示したように、p層の光吸収量が小さいために、短絡電流が15.0mA/cm2と比較的大きな値が得られた。また、Voc=0.85V、F.F.=0.65と、p層としてのキャリア密度も充分であることがわかる。
A. of these photoelectric conversion elements M. FIG. 3 shows the IV characteristics under 1.5.
As is clear from FIG. 3, in the photoelectric conversion element according to the second embodiment, as described in the first embodiment, the short-circuit current is 15.0 mA / cm 2 because the light absorption of the p-layer is small. And a relatively large value was obtained. In addition, Voc = 0.85 V; F. = 0.65, which indicates that the carrier density of the p-layer is also sufficient.

一方、p層が単一層で形成された光電変換素子においては、上記実施の形態1で示したように、p層の光吸収量が大きいため、本実施の形態2における光電変換素子に比較して、短絡電流は13.2mA/cm2と十分でないことがわかる。 On the other hand, in the photoelectric conversion element in which the p-layer is formed as a single layer, the amount of light absorption in the p-layer is large as described in the first embodiment, and therefore, compared to the photoelectric conversion element in the second embodiment. Therefore, it is understood that the short-circuit current is not enough at 13.2 mA / cm 2 .

[実施の形態3:p層の光吸収量の評価]
実施の形態1と同様の基板を用い、同様の方法で、約2nmの高ドープp型a−Si層上に約10nmのa−Si層を成膜し、さらに、a−Si層表面を、ヘリウムガスを用いて、表2に示す条件によりプラズマ処理した。これらの工程を繰り返して行い、総膜厚300nmのp層を形成した。
[Embodiment 3: Evaluation of light absorption amount of p layer]
Using the same substrate as in the first embodiment, a similar method is used to form an approximately 10 nm a-Si layer on an approximately 2 nm highly doped p-type a-Si layer. Plasma treatment was performed using helium gas under the conditions shown in Table 2. These steps were repeated to form a p-layer having a total thickness of 300 nm.

Figure 2004289188
Figure 2004289188

上記で得られたp層の光吸収量を測定した。その結果を図5に示す。
光吸収量は、図5から明らかなように、プラズマ処理を施すことにより、実施の形態1における高ドープp層/p層の繰り返しp層よりもさらに光吸収量が小さくなっていることがわかる。
また、上記においては、高ドープp層/p層の繰り返しp層におけるp層を10nm程度として、10nm程度ごとに高ドープp層を積層し、プラズマ処理を行っているが、p層を30nm程度以下とした場合には、同程度の光吸収量の低減効果が得られることがわかっている。
The light absorption of the p layer obtained above was measured. The result is shown in FIG.
As is clear from FIG. 5, the light absorption amount is smaller than that of the highly doped p-layer / p-layer repetition p-layer according to the first embodiment by performing the plasma treatment. .
Further, in the above, the p-layer in the repetitive p-layer of the highly doped p-layer / p-layer is set to about 10 nm, and the highly doped p-layer is laminated every about 10 nm, and the plasma treatment is performed. It has been found that the same effect of reducing the amount of light absorption can be obtained in the following cases.

[実施の形態4:光電変換素子及びその製造方法]
この実施の形態の光電変換素子は、図6に示したように、透明ガラス基板1上に、透明電極層2、高ドープp型a−Si層7、p型a−Si層8、i層4、n層5及び裏面電極層6が順次形成され、p型a−Si層8表面に、プラズマ処理が施された面9を有して構成されている。
[Embodiment 4: Photoelectric conversion element and manufacturing method thereof]
As shown in FIG. 6, a photoelectric conversion element according to this embodiment includes a transparent glass substrate 1, a transparent electrode layer 2, a highly doped p-type a-Si layer 7, a p-type a-Si layer 8, and an i-layer. 4, an n-layer 5 and a back electrode layer 6 are sequentially formed, and the surface of the p-type a-Si layer 8 has a surface 9 that has been subjected to plasma processing.

上記光電変換素子の製造方法を、以下に説明する。
まず、実施の形態2と同様の凹凸形状を持つZnO膜を表面に備えた透明ガラス基板1上に、実施の形態2と同様に、高ドープp型a−Si層、a−Si層8を形成する。
次いで、a−Si層8表面を、水素ガスを用いて、表3に示す条件によりプラズマ処理した。
The method for manufacturing the photoelectric conversion element will be described below.
First, similarly to the second embodiment, a highly doped p-type a-Si layer and an a-Si layer 8 are formed on a transparent glass substrate 1 provided with a ZnO film having the same concavo-convex shape as the second embodiment. Form.
Next, the surface of the a-Si layer 8 was subjected to plasma treatment using hydrogen gas under the conditions shown in Table 3.

Figure 2004289188
Figure 2004289188

続いて、実施の形態2と同様に、a−Si層8上に、i層4、n層5及び裏面電極6を形成し、図6に示す光電変換素子を作製した。
得られた光電変換素子のI−V特性を評価した。
この光電変換素子のA.M.1.5下でのI−V特性を、図7に示す。なお、図7においては、比較のために、実施の形態2で得られた光電変換素子のI−V特性を併せて示す。
Subsequently, as in Embodiment 2, the i-layer 4, the n-layer 5, and the back electrode 6 were formed on the a-Si layer 8, and the photoelectric conversion element shown in FIG. 6 was manufactured.
The IV characteristics of the obtained photoelectric conversion element were evaluated.
A. of this photoelectric conversion element M. FIG. 7 shows IV characteristics under 1.5. Note that FIG. 7 also shows, for comparison, the IV characteristics of the photoelectric conversion element obtained in Embodiment 2.

図7から明らかなように、本実施の形態4における光電変換素子では、上記実施の形態3で示したように、p層の光吸収量がさらに小さいために、短絡電流が16.0mA/cm2とより大きな値が得られた。また、Voc=0.9V、F.F.=0.68と、p層としてのキャリア密度も充分であることがわかる。 As is clear from FIG. 7, in the photoelectric conversion element according to the fourth embodiment, as described in the third embodiment, the short-circuit current is 16.0 mA / cm because the light absorption amount of the p-layer is smaller. A higher value of 2 was obtained. Further, Voc = 0.9 V, F.C. F. = 0.68, which indicates that the carrier density of the p-layer is also sufficient.

[実施の形態5:光電変換素子及びその製造方法]
この実施の形態の光電変換素子は、透明ガラス基板上に、透明電極層、高ドープp型a−Si層、p型a−Si層、i層、n層及び裏面電極層が順次形成され、高ドープp型a−Si層表面に、プラズマ処理が施された面を有して構成されている。
[Embodiment 5: Photoelectric conversion element and manufacturing method thereof]
In the photoelectric conversion element of this embodiment, a transparent electrode layer, a highly doped p-type a-Si layer, a p-type a-Si layer, an i-layer, an n-layer, and a back electrode layer are sequentially formed on a transparent glass substrate, The highly doped p-type a-Si layer has a surface subjected to plasma treatment on the surface.

上記光電変換素子の製造方法を、以下に説明する。
まず、実施の形態2と同様の凹凸形状を持つZnO膜を表面に備えた透明ガラス基板1上に、実施の形態2と同様に、高ドープp型a−Si層を形成した後、水素ガスを用いて、表3に示す条件によりプラズマ処理した。
次いで、高ドープp型a−Si層上に、実施の形態2と同様にa−Si層、i層、n層及び裏面電極を形成し、光電変換素子を作製した。
The method for manufacturing the photoelectric conversion element will be described below.
First, similarly to the second embodiment, a highly doped p-type a-Si layer is formed on a transparent glass substrate 1 having a ZnO film having a concavo-convex shape on the surface as in the second embodiment, and then a hydrogen gas is formed. And plasma treatment was performed under the conditions shown in Table 3.
Next, on the highly doped p-type a-Si layer, an a-Si layer, an i-layer, an n-layer, and a back electrode were formed in the same manner as in Embodiment 2, to produce a photoelectric conversion element.

得られた光電変換素子のI−V特性を評価したところ、本実施の形態5における光電変換素子では、短絡電流が16.5mA/cm2と大きな値が得られた。また、Voc=0.9V、F.F.=0.68と、p層としてのキャリア密度も充分であることがわかる。 When the IV characteristics of the obtained photoelectric conversion element were evaluated, the photoelectric conversion element according to Embodiment 5 exhibited a large short-circuit current of 16.5 mA / cm 2 . Further, Voc = 0.9 V, F.C. F. = 0.68, which indicates that the carrier density of the p-layer is also sufficient.

[実施の形態6:光電変換素子及びその製造方法]
この実施の形態の光電変換素子は、図8に示したように、透明ガラス基板1上に、透明電極層2、高ドープp型a−Si層7、p型グレーデッドプラズマ処理層10、i層4、n層5及び裏面電極層6が順次形成され、さらに高ドープp型a−Si層7表面にプラズマ処理が施された面を有し、グレーデッドプラズマ処理層10内及び表面にもプラズマ処理が施された面を有して構成されている。
[Embodiment 6: Photoelectric conversion element and manufacturing method thereof]
As shown in FIG. 8, a photoelectric conversion element according to this embodiment has a transparent electrode layer 2, a highly doped p-type a-Si layer 7, a p-type graded plasma processing layer 10, i on a transparent glass substrate 1. The layer 4, the n-layer 5, and the back electrode layer 6 are sequentially formed, and the surface of the highly doped p-type a-Si layer 7 has a plasma-treated surface. It has a surface that has been subjected to plasma processing.

上記光電変換素子の製造方法を、以下に説明する。
まず、実施の形態2と同様の凹凸形状を持つZnO膜を表面に備えた透明ガラス基板1上に、実施の形態2と同様に、高ドープp型a−Si層7を形成し、実施の形態5と同様に水素ガスを用いて高ドープp型a−Si層7表面をプラズマ処理した。
The method for manufacturing the photoelectric conversion element will be described below.
First, similarly to the second embodiment, a highly doped p-type a-Si layer 7 is formed on a transparent glass substrate 1 having a ZnO film having a concavo-convex shape similar to that of the second embodiment on the surface. As in Embodiment 5, the surface of the highly doped p-type a-Si layer 7 was subjected to plasma treatment using hydrogen gas.

次いで、同じ高ドープp型a−Si層7の成膜チャンバ内で、膜厚3nmのi層を成膜し、表2のH2プラズマ処理を50Wで1分行った後、さらに膜厚3nmのi層を成膜し、表3のH2プラズマ処理を20Wで1分行った。これにより、雰囲気からのボロンの混入が起こり、これら2層のi層は、p型グレーデッドプラズマ処理層10として形成された。 Next, an i-layer having a thickness of 3 nm was formed in the same highly doped p-type a-Si layer 7 in the film formation chamber, and the H 2 plasma treatment shown in Table 2 was performed at 50 W for 1 minute. Was formed, and the H 2 plasma treatment shown in Table 3 was performed at 20 W for 1 minute. As a result, boron was mixed in from the atmosphere, and these two i-layers were formed as the p-type graded plasma processing layer 10.

続いて、i層成膜チャンバで200nmのi層4を成膜した。
その後、n層成膜チャンバで30nmのn層5を成膜し、続いて裏面電極6を形成することにより図8に示す光電変換素子を作製した。
得られた光電変換素子のI−V特性を評価した。
この光電変換素子のA.M.1.5下でのI−V特性を、図9に示す。なお、図9においては、比較のために、実施の形態3で得られたa−Si層8表面を水素でプラズマ処理した光電変換素子のI−V特性を併せて示す。
Subsequently, an i-layer 4 having a thickness of 200 nm was formed in the i-layer film forming chamber.
Thereafter, an n-layer 5 having a thickness of 30 nm was formed in an n-layer formation chamber, and then a back electrode 6 was formed, thereby producing the photoelectric conversion element shown in FIG.
The IV characteristics of the obtained photoelectric conversion element were evaluated.
A. of this photoelectric conversion element M. FIG. 9 shows the IV characteristics under 1.5. FIG. 9 also shows, for comparison, the IV characteristics of the photoelectric conversion element obtained by plasma-treating the surface of the a-Si layer 8 obtained in Embodiment 3 with hydrogen.

図9から明らかなように、本実施の形態6における光電変換素子では、上記実施の形態5で示したように、短絡電流が16.5mA/cm2と大きな値が得られるとともに、Voc=0.92V、F.F.=0.73と、p層としてのキャリア密度が改善された。 As is clear from FIG. 9, in the photoelectric conversion element according to the sixth embodiment, as described in the fifth embodiment, a short-circuit current as large as 16.5 mA / cm 2 is obtained, and Voc = 0. .92 V, F.R. F. = 0.73, indicating that the carrier density of the p-layer was improved.

本発明の光電変換素子に用いるp層の光吸収量の評価を示すグラフである。4 is a graph showing an evaluation of a light absorption amount of a p-layer used in the photoelectric conversion element of the present invention. 本発明の光電変換素子の実施例を示す要部の概略断面図である。FIG. 2 is a schematic sectional view of a main part showing an example of the photoelectric conversion element of the present invention. 図2の光電変換素子のI−V特性を示すグラフである。3 is a graph showing IV characteristics of the photoelectric conversion element in FIG. 本発明の光電変換素子のI−V特性を比較するための従来のp層構造を備えた光電変換素子の要部の概略断面図である。It is a schematic sectional drawing of the important section of the photoelectric conversion element provided with the conventional p layer structure for comparing the IV characteristic of the photoelectric conversion element of this invention. 本発明の別の光電変換素子に用いるp層の光吸収量の評価を示すグラフである。It is a graph which shows evaluation of the amount of light absorption of the p layer used for another photoelectric conversion element of the present invention. 本発明の別の光電変換素子の実施例を示す要部の概略断面図である。It is a schematic sectional drawing of the important section showing the example of another photoelectric conversion element of the present invention. 図6の光電変換素子のI−V特性を示すグラフである。7 is a graph showing IV characteristics of the photoelectric conversion element in FIG. 本発明のさらに別の光電変換素子の実施例を示す要部の概略断面図である。It is an outline sectional view of an important section showing an example of still another photoelectric conversion element of the present invention. 図8の光電変換素子のI−V特性を示すグラフである。9 is a graph showing IV characteristics of the photoelectric conversion element in FIG.

符号の説明Explanation of reference numerals

1 ガラス基板
2 透明電極層
3 p型a−Si
4 i層
5 n層
6 裏面電極層
7 高ドープp型a−Si層(第1p層)
8 p型a−Si層(第2p層)
9 プラズマ処理界面
10 p型グレーデッドプラズマ処理層
Reference Signs List 1 glass substrate 2 transparent electrode layer 3 p-type a-Si
4 i layer 5 n layer 6 back electrode layer 7 highly doped p-type a-Si layer (first p layer)
8 p-type a-Si layer (second p layer)
9 Plasma treatment interface 10 P-type graded plasma treatment layer

Claims (6)

pin接合を有する光電変換素子を構成するp層を、5nm以下の膜厚を有する均一に不純物が添加された第1p層を成膜し、該第1p層上にp型不純物を含まないガス分解によって第2p層を成膜することにより形成することを特徴とする光電変換素子の製造方法。   As a p-layer constituting a photoelectric conversion element having a pin junction, a first p-layer having a thickness of 5 nm or less and uniformly doped with impurities is formed, and gas decomposition free of p-type impurities is formed on the first p-layer. A method for manufacturing a photoelectric conversion element, wherein the second p-layer is formed by forming a second p-layer. 第1p層を成膜した後、該第1p層表面にプラズマ処理を施す請求項1記載の光電変換素子の製造方法。   The method according to claim 1, wherein after forming the first p-layer, the surface of the first p-layer is subjected to plasma treatment. 第2p層の成膜中、前記第2p層を所定膜厚成膜する毎に得られた第2p層表面にプラズマ処理を施す請求項1又は2記載の光電変換素子の製造方法。   3. The method according to claim 1, wherein during the formation of the second p-layer, a plasma treatment is performed on the surface of the second p-layer obtained every time the second p-layer is formed to a predetermined thickness. プラズマ処理を、所定膜厚成膜する毎に、プラズマ照射時間及び/又は処理電力を小さくして施こす請求項3記載の光電変換素子の製造方法。   4. The method for manufacturing a photoelectric conversion element according to claim 3, wherein the plasma processing is performed with a reduced plasma irradiation time and / or processing power every time a predetermined film thickness is formed. 第1p層及び第2p層を、成膜装置の同一チャンバで形成する請求項1〜4のいずれか1つに記載の光電変換素子の製造方法。   The method according to any one of claims 1 to 4, wherein the first p-layer and the second p-layer are formed in the same chamber of a film forming apparatus. 第1p層及び第2p層とi層とを、成膜装置の異なるチャンバで形成する請求項1〜4のいずれか1つに記載の光電変換素子の製造方法。   The method for manufacturing a photoelectric conversion element according to any one of claims 1 to 4, wherein the first p layer, the second p layer, and the i layer are formed in different chambers of a film forming apparatus.
JP2004210171A 1998-06-12 2004-07-16 Process for fabricating photoelectric conversion element Pending JP2004289188A (en)

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