JP2004287493A - Operation synchronizing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize operational synchronization that makes it easy to realize operational synchronization or time synchronization between a plurality of processors, which are difficult to realize by means of a conventional multiprocessor system, without the prevention of communications between the processors via a fabric. <P>SOLUTION: The processors mounted on processor cards communicate with each other in the multiprocessor system. In this case, the processor card is provided with the processor which carries out main computation processing, a data communication conversion device and a port connected to an operation synchronizing signal transmission and reception device. The processor card is fixed to an operational synchronizing bus back panel and connected to an operation synchronizing bus. Only the operation synchronizing signal transmission and reception device which is set as a master executes the operational synchronization according to a master/slave setting signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multiprocessor system in which a plurality of processors operate in parallel, performs connection of electric signals for communication between processors, converts and connects electric characteristics of electric signals, or connects to optical fibers. A port that converts optical signals and electrical signals to each other, and these ports are connected to each other, and the electrical or optical signal is uniquely determined between the ports indicated by the signals themselves or the connection method between the ports. The present invention relates to a circuit for synchronizing the operation of each processor in a system including a fabric for transmitting and receiving signals between ports.
[0002]
[Prior art]
In a multiprocessor system, since each processor operates in parallel, special consideration is required for hardware or software debugging in system development and synchronization between operating processors.
In a configuration in which a processor is connected to a common bus as a conventional multiprocessor system, a mechanism for time synchronization is added to the common bus (for example, see Patent Document 1). Further, in a configuration in which the processor is connected to a network, a network for newly providing a trigger signal to the processor is added (for example, see Patent Document 2).
[0003]
[Patent Document 1]
JP-A-2000-348007 (page 6, FIG. 1)
[Patent Document 2]
JP-A-5-165792 (page 5, FIG. 1)
[0004]
[Problems to be solved by the invention]
In a conventional multiprocessor system, the instruction addresses and instruction contents of software executed by the processors at the system development stage, variables, and internal and It enables acquisition of operation trace information for recording states such as register information, and enables software operating on a plurality of processors in the system to operate in cooperation. In order to achieve this time synchronization, time synchronization information and debug information that is originally unnecessary are communicated via a common bus or fabric. For this reason, the time synchronization information must be interrupted in the gap between the processors communicating a large amount of data, and the strict time synchronization cannot be performed because the delay of the transmission processing and the reception processing is not constant for each processor. . Further, by performing time synchronization while ignoring the internal state of software executed by the processor and the dependency of data transmission / reception, for example, a processor that has completed transmission processing of a certain data and a processor that has completed the transmission processing of the data may be used. The operation trace information is collected with the processor. At this time, it is impossible to collect correct operation trace information, for example, the transmission of the data is completed on one side, and the data is not received on the other side. In addition, the time synchronization information communication hinders the occurrence of failures during software development, impairing the reproducibility of the failures, and increasing the time synchronization information communication time increases the communication time of the entire system, degrading the processing performance of the system There is a problem of letting them do.
[0005]
The present invention has been made to solve the above-described problem, and has as its object to realize operation synchronization without interrupting communication between processors.
[0006]
[Means for Solving the Problems]
An operation synchronization circuit according to the present invention includes: a card internal bus; a data communication converter connected to the card internal bus, for performing conversion for transmitting an electric signal on the card internal bus to a fabric; A port for connecting the converter to the fabric; and an operation synchronization signal transceiver for connecting an operation synchronization bus for operation synchronization with the card internal bus.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
Hereinafter, Embodiment 1 according to the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of the operation synchronization circuit in the multiprocessor system according to the first embodiment. The multiprocessor system shown in the figure is a system including two or more processors of the same or different types, and is installed in the multiprocessor system. The multiprocessor system is based on the IEEE802.3 standard and the Fiber Channel (ANSI X3. 230: 1994), InfiniBand (InfiniBand Trade Association), RACEway (ANSI / VITA 5-1994), RapidIO (RapioIO Trade Association), Hyper Transport (Hyper Transport Consortium), STARFABRIC (StarFabric Trade Association), PCI Express (Peripheral Com This is a combination of connections for one-to-one communication between devices using an electrical or optical signal conforming to the Pentant Interconnect Special Interest Group), an upward compatible standard of the above standard, or another standard. This is a system in which processors mounted on two or more processor cards communicate with each other via a fabric 6, which is a connection network capable of exchanging data. The two or more processor cards that constitute the multiprocessor system are respectively connected to the fabric 6 and the inside of the fabric as shown in the processor card (1) 2, the processor card (2) 11, and the processor card (n) 13. Signals are converted into electrical signals on the processor card and connected by a port 5. In the processor card (1) 2, the processor card (2) 11, and the processor card (n) 13, processors (1) 1, processor (2) 10, and processor (n) 12, which perform main arithmetic processing, operate in parallel. Each processor card has a card internal bus 3 for electrically connecting the processor and other electronic circuits. The card internal bus 3 converts an electric signal for connecting to the port 5 and an electric signal on the card internal bus 3 to each other, while maintaining the data content, with respect to their respective transmission methods and electric characteristics. And a data communication converter 4 which can detect and correct transmission of erroneous data which is expected to occur on the fabric 6. The data transmitted and received by the processor (1) 1, the processor (2) 10, and the processor (n) 12 are transmitted to each other via the card internal bus 3, the data communication converter 4, the port 5, and the fabric 6. You. Regarding the internal connection method of the fabric 6, there is a point-to-point connection such as a crossbar switch, or a method of directly connecting the ports of the processor cards in a ring shape, but the details of the structure are omitted.
[0008]
An operation synchronization signal transceiver 20a connected to the card internal bus 3 is connected to the processor card (1) 2. The operation synchronization signal transceiver 20a is a device for controlling and observing signals constituting the operation synchronization bus 21 by connecting to the card internal bus 3. The operation synchronization signal transceiver 20a can drive the synchronization signal 23 and the data signal 24 constituting the operation synchronization bus 21 shown in FIG. Similarly, operation synchronization signal transceivers 20b and 20c are connected to the processor card (2) 11 and the processor card (n) 13, respectively. These processor cards are operation synchronization buses on which the operation synchronization bus 21 is electrically mounted. -It is mechanically fixed to the back panel 27 and is electrically connected to the operation synchronization bus 21. In this bus connection configuration, since the operation synchronization signal transceiver has the same electrical characteristics, it can be interconnected with the common operation synchronization bus 21. Therefore, the processor (1) 1 and the other processor (2) 10, the processor (n) ) 12 can be connected even if they are of different types, or the card internal bus 3 is a different type of bus for each processor card. In the operation synchronization signal transceiver connected to the operation synchronization bus 21, only one operation synchronization signal transceiver 20a operates as a master, and all the operation synchronization signal transceivers 20b and 20c other than the master operate as slaves. . The operation synchronization signal transceiver 20a set as the master can drive the synchronization signal 23 and the data signal 24 among the signals on the operation synchronization bus 21, and can read the status signal 25. On the other hand, the operation synchronization signal transceivers 20b and 20c set as slaves can read the synchronization signal 23 and the data signal 24, and can drive the status signal 25. The operation setting of the master or the slave may be an operation synchronization signal transceiver dedicated to the master and an operation synchronization signal transceiver dedicated to the slave designed exclusively for each, or an operation synchronization signal designed commonly for the master and the slave. For the transceiver, the master / slave setting signal 22 may be set for each processor card to determine the internal operation. In this case, the master / slave setting signal 22 supplies an electric signal for instructing master setting to only one processor card (1) 2, and the other processor cards (2) 11 and processor card (n). 13) is supplied with an electric signal for instructing slave setting. Even if the processor cards have the same configuration, only one processor card (1) 2 operates as the master-set operation synchronization signal transceiver 20a, and the other processor cards (2) 11, 11 (n) 13 The operation synchronization bus / back panel 27 supplies the master / slave setting signal 22 according to the position where the card is fixed so as to operate as the slave-set operation synchronization signal transceivers 20b and 20c. I do. With this configuration, the trouble of setting the master setting and the slave setting for each card can be omitted, and all the operation synchronization signal transceivers connected to the operation synchronization bus 21 are set as slaves, or two or more operation synchronization signal transceivers are set at the same time. Master setting can be prevented. In another configuration, the processor may instruct the operation synchronization signal transceiver via the card internal bus 3 to perform master setting or slave setting without using the master / slave setting signal 22 by software.
[0009]
The operation synchronization bus 21 will be described in detail with reference to FIG. Unlike a VME (Versa Module Europe) standard bus or a CompactPCI (Compact-Peripheral Component Interconnect) standard bus, one synchronous signal 23 and one or more data signals 24 for notifying the operating state and time are provided. It comprises one or more status signals 25 for sharing the internal state of each operation synchronization signal transceiver. In addition, a timer / register circuit 26 is included in the operation synchronization signal transceivers 20a, 20b, 20c. The timer / register circuit 26 is a circuit that can be controlled by the processor via the card internal bus 3. When the processor requests the start of the timer operation, a circuit prepared for performing time measurement operates, and the timer register circuit 26 internally calculates the time each time a predetermined time elapses and holds the time. It has a function to do. The processor can read the time calculated and held by the timer register circuit 26 at any time, and can obtain the time elapsed since the request for starting the timer operation. Further, the operation synchronization signal transceiver 20a set as the master can output to the data signal 24 the time calculated by the timer / register circuit 26 at regular intervals based on an instruction from the processor. Also, the slave-set operation synchronization signal transceivers 20b and 20c can read the time output by the master-set operation synchronization signal transceiver 20a via the data signal 24 and store the time in the timer / register circuit 26. it can. This time can be read by the processor (2) 10 and the processor (n) 12 via the card internal bus 3. Alternatively, the operation synchronization code specified by the processor is written into the timer register circuit 26 of the operation synchronization signal transceiver 20a set as the master, and when the processor requests transmission of the code, the operation synchronization code is output to the data signal 24. I do. The operation synchronization signal transceivers 20b and 20c set as slaves read the operation synchronization code from the data signal 24 and hold the same in the timer register circuit 26. This operation synchronization code can be read by the processor (2) 10 and the processor (n) 12 via the card internal bus 3.
[0010]
Among the processor cards, the processor card (1) 2, which is uniquely set as the master by the master setting instruction of the master / slave setting signal 22, has the authority to manage the operation synchronous bus 21 in this multiprocessor system. In each processor card set as the slave, the processor (2) 10 and the processor (n) 12 write the status to the timer register circuit 26 in order to notify a state where the operation can be started when the preparation for the system operation is completed. . In response, the slave-set operation synchronization signal transceivers 20 b and 20 c output a status signal 25 to the operation synchronization bus 21. The status signal 25 is received by the operation synchronization signal transceiver 20a of the processor card (1) 2 set as the master, and is held in the timer / register circuit 26.
[0011]
The processor (1) 1 can read this status signal 25 from the timer / register circuit 26 via the card internal bus 3 at any time. By this reading, the operation state of the processor cards (2) 11, (n) 13 equipped with the operation synchronization signal transceivers 20b, 20c set as slaves can be grasped. The processor (1) 1 monitors the status of the status signal 25 obtained from the timer register circuit 26 to prepare for the system operation of all the processor cards even if the activation times of the respective processor cards are different. You can wait until you can. With this mechanism, a processor that has not been ready for startup is connected, and a processor that has completed startup quickly starts communication via the fabric 6 unnecessarily, and communication with the processor before startup has been completed cannot be established. Can be prevented from occurring.
[0012]
The processor (1) 1 can start the system operation at an arbitrary point in time after the start preparation of the processor (1) is completed and the start preparation of the other processor obtained by the above mechanism is completed. At the start of the system operation, the processor (1) 1 sends the previously registered code or the code indicating time zero to the timer register circuit 26 of the operation synchronization signal transceiver 20a set as a master to notify the operation start as the synchronization start time. Set. The operation synchronization signal transceiver 20a set as the master outputs this code to the data signal 24, and drives the synchronization signal 23 in a pulsed manner. The slave-set operation synchronization signal transceivers 20b and 20c connected to the operation synchronization bus 21 receive the edge of the synchronization signal 23 which transitions from logic L to logic H or from logic H to logic L depending on the configuration. Synchronization is completely achieved within the range of the difference in the total time of the signal transmission delay time of the synchronization signal and the physical response delay time of the element component transmitting and receiving this signal in each processor card. Therefore, the synchronization accuracy does not depend on the pulse width of the synchronization signal 23 or the transmission delay of the data signal 24.
[0013]
After the start of the operation synchronization, the processor starts high-speed data transmission / reception via the data communication converter 4, port 5, and fabric 6 of each processor card. When the processor (1) 1 does not need to manage the operation synchronization of the multiprocessor system, the processor (1) 1 controls the timer register circuit 26 included in the operation synchronization signal transceiver 20a to execute the timer operation. By instructing, the operation synchronization signal transceivers 20b and 20c set as slaves on the other processor card (2) 11 and the processor card (n) 13 irrespective of the software operation of the processor (1) 1. Time data is output to the data signal 24 at time intervals, and the synchronization signal 23 is pulse-driven. With the above operation, time synchronization can be performed with respect to the other processors (2) 10 and (n) 12. Further, since the processor (1) 1 can also refer to the time information by referring to the timer / register circuit 26, time synchronization can be performed. Further, an interrupt input for instructing an interrupt process of a program operation of each processor is connected to the operation synchronizing signal transceivers 20a, 20b, 20c via the interrupt signal line 33, and the interrupt signal is notified simultaneously with the generation of the pulse of the synchronizing signal 23. By doing so, the occurrence of time synchronization may be notified regardless of the software processing content.
[0014]
When the processor (1) 1 performs the synchronization management of the multiprocessor system, it writes an appropriate operation synchronization code into the timer register circuit 26 included in the operation synchronization signal transceiver 20a set as a master. By this write operation, the operation synchronization signal transceiver 20a outputs the code specified in the data signal 24 and drives the synchronization signal 23 in a pulsed manner.
The operation synchronizing signal transceivers 20b and 20c set as slaves take in the sign of the data signal 24 every time the synchronizing signal 23 is received, and hold the same in the timer register circuit 26. By reading the timer / register circuit 26 from the card internal bus 3 as needed, the processor can acquire the code for the operation synchronization from the processor (1) 1 and perform the operation synchronization. In another configuration, each time the synchronization signal 23 is received, the operation synchronization signal transceivers 20b and 20c set as slaves connect the interruption signal line 33 to the interruption input of the processor, and execute the software processing of the processor. Instead, the processor may be notified of the reception of the operation synchronization signal.
[0015]
The timing of each signal on the operation synchronization bus 21 will be described with reference to FIG. The synchronizing signal 23 is a valid signal at the edge of the waveform on the pulse, and is synchronized at the time of transition from logic L to logic H as shown in FIG. 3, for example. In another configuration, synchronization may be established at the time of transition from logic H to logic L. This signal is output by the operation synchronizing signal transceiver 20a set as a master by the master / slave setting signal 22. The data signal 24 is composed of one or more signal lines, and is composed of a sufficient number of signal lines capable of expressing codes required for system operation synchronization. The sign of this signal is determined at the time when the signal of the synchronization signal 23 changes from logic L to logic H, or from logic H to logic L depending on the configuration, and is output by the operation synchronization signal transceiver 20a set as a master. The operation synchronization signal transceivers 20b and 20c set as slaves read. The status signal 25 is output from the slave-set operation synchronization signal transceivers 20b and 20c, and when each processor becomes operable, sets from logic L to logic H or from logic H to logic L depending on the configuration. In order to simultaneously read the status signals of a plurality of processors, the number of lines may correspond to the number of processors, or one signal may be shared by two or more processors.
[0016]
Embodiment 2 FIG.
FIG. 4 shows a configuration of an operation synchronization circuit in a multiprocessor system according to the second embodiment. The multiprocessor system shown in the figure is supported by a robust structure of a common bus back panel 32 such as a widely commercially available bus of the VME standard, a bus of the PCI standard, and a bus of the CompactPCI standard. In this configuration, the operation synchronization bus 21 is arranged in an empty signal line.
[0017]
The processor card (1) 2, the processor card (2) 11, and the processor card (n) 13 are inserted into the common bus back panel 32. The common bus 31 is a bus to which address lines, data lines, and control signals such as VME standard, PCI standard, and CompactPCI standard buses are connected based on a common standard. Via the common bus converter 30 for mutually converting the electrical characteristics and data exchange procedure with the electrical signals of the other and performing data transfer.
Here, the operation synchronization bus 21 can be configured with one signal line for each of the synchronization signal 23, the data signal 24, and the status signal 25 in the minimum configuration, and the empty signal line of the common bus 31 can be easily used. it can. Further, in comparison with the common bus 31 which takes a complicated procedure due to the characteristics of the electric signal, the operation synchronization can be performed by the edge of the pulse signal of the synchronization signal 23. Also depends only on the propagation delay of the electrical signal on that signal line. For this reason, the time transmitted to each operation synchronizing signal transceiver has sufficient precision compared with the operation of the processor.
Further, the master / slave setting signal 22 is set to only one master setting signal and another slave setting signal in accordance with the position where the card is inserted into the common bus back panel 32. With this configuration, the trouble of setting the master setting and the slave setting for each card can be omitted, and all the operation synchronization signal transceivers connected to the operation synchronization bus 21 are set as slaves, or two or more operation synchronization signal transceivers are set at the same time. Master setting can be prevented. In another configuration, the processor may instruct the operation synchronization signal transceiver via the card internal bus 3 to perform master setting or slave setting without using the master / slave setting signal 22 by software.
[0018]
Embodiment 3 FIG.
FIG. 5 shows the configuration of the operation synchronization circuit in the multiprocessor system according to the third embodiment. The multiprocessor system shown in the figure has a configuration in which operation synchronization can be performed between processor cards connected to a common fabric 6 connected to a plurality of different common bus back panels 32.
[0019]
A connector 28, which is a connection device for connecting the synchronization signal 23, the data signal 24, and the status signal 25 constituting the operation synchronization bus 21, is connected between different common bus / back panels 32, and the synchronization signal 23, the data signal 24, the back panel is connected by a cable 29 which is a wiring for electrically connecting the status signal 25. Normally, it is difficult to apply such a configuration to, for example, the common bus 31 from the viewpoint of electrical characteristics. However, since the operation synchronous bus 21 is slower than the operation of the common bus 31, Since the characteristics are extremely simple, extension by the cable 29 is easy. Further, even when the common buses 31 are of different types of standards, the operation synchronization bus 21 can be made common, so that the operation synchronization bus 21 can be easily synchronized.
[0020]
Embodiment 4 FIG.
FIG. 6 shows the configuration of the operation synchronization circuit in the multiprocessor system according to the fourth embodiment. The multiprocessor system illustrated in the figure is a card that does not have a direct connection to the fabric 6, and reads and writes data from and to a memory via a common bus, and controls signal input from external devices and external devices. Is connected to the common bus 31.
[0021]
The card internal bus 3 on the input / output card 15 converts and holds the electrical characteristics of the input signal from the external device, outputs a signal that matches the electrical characteristics required by the external device, or outputs the input signal. An input / output controller 14 that performs analog-to-digital conversion and vice versa to generate an output signal by performing digital-to-analog conversion is connected to perform input / output control with an external device (not shown). The card internal bus 3 may be the same bus as the processor card (1) 2 or other card internal buses 3, a dedicated bus dedicated to the input / output card 15, or a simple set of control lines and data lines. . When processing an input signal from an external device in a multiprocessor system, it is important to know when the input signal is. The input / output controller 14 reads the time information and the operation synchronization information transmitted from the processor card (1) 2 via the operation synchronization bus 21 via the card internal bus 3 so that the input signal and the acquisition time are obtained. Alternatively, it can be associated with the internal state of the processor (1) 1. Thus, by transmitting and receiving the information in which the input signal is associated with the time via the common bus 31, it is possible for the processor (1) 1 to execute necessary arithmetic processing, and the system configuration can be flexibly configured. There is.
[0022]
By changing the configuration of the master / slave setting signal 22 set by the common bus back panel 32, the operation synchronization signal transceiver 20b on the input / output card 15 is operated as the master setting, and the processor card (1) 2 may be configured to operate the operation synchronization signal transceiver 20a as a slave setting. In this case, the input / output controller 14 instructs the timer operation to the timer / register circuit 26 included in the operation synchronization signal transmitter / receiver 20b set as the master, and converts the input signal from the external device at regular intervals. In addition, time synchronization can be performed.
[0023]
【The invention's effect】
Since the present invention is configured as described above, operation synchronization can be realized without interrupting interprocessor communication.
[Brief description of the drawings]
FIG. 1 is a diagram for describing an operation synchronization circuit in a multiprocessor system according to a first embodiment of the present invention;
FIG. 2 is a diagram for describing details of an operation synchronization bus according to the first embodiment of the present invention;
FIG. 3 is a diagram for explaining signal timing of an operation synchronization bus according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating an operation synchronization circuit in a multiprocessor system according to a second embodiment of the present invention;
FIG. 5 is a diagram illustrating an operation synchronization circuit in a multiprocessor system according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating an operation synchronization circuit in a multiprocessor system according to a fourth embodiment of the present invention.
[Explanation of symbols]
1 processor (1)
2 Processor card (1)
3 Card internal bus
4 Data communication converter
5 ports
6 Fabric
10 processor (2)
11 Processor card (2)
12 Processor (n)
13 Processor card (n)
14 I / O controller
15 I / O card
20a Master setting operation synchronization signal transceiver
20b Slave setting operation synchronization signal transceiver
20c Slave setting operation synchronization signal transceiver
21 Operation Synchronous Bus
22 Master / slave setting signal
23 Sync signal
24 data signals
25 Status signal
26 Timer / register circuit
27 Operation Synchronous Bus / Back Panel
28 Connector
29 cable
30 common bus converter
31 common bus
32 Common Bus Back Panel
33 interrupt signal line

Claims (3)

Card internal bus,
A data communication converter connected to the card internal bus and performing conversion for transmitting an electric signal on the card internal bus onto a fabric;
A port connecting the data communication converter and a fabric,
An operation synchronization signal transceiver that connects the card internal bus and an operation synchronization bus for performing operation synchronization,
An operation synchronization circuit comprising: A common bus,
A common bus converter that is connected to the card internal bus and converts the electric signal of the card internal bus into data of the common bus;
The operation synchronization circuit according to claim 1, further comprising: 3. The operation synchronization circuit according to claim 2, wherein the common bus is plural.

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