JP2004287113A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To compensate unevenness between flicker levels of upper, lower, left and right parts and a central part of a screen of a liquid crystal display. <P>SOLUTION: In The liquid crystal display which is provided with a liquid crystal module 1 consisting of a liquid crystal element panel 2, a horizontal shift register 3, a vertical shift register 4, a common electrode 5 and the like, a control signal producing circuit 6, an S/H drive circuit 7 and a common voltage adjusting circuit 8 and wherein polarities of a video signal to common voltage is reversed in every horizontal and vertical periods, a common voltage compensation circuit is provided, compensating the common voltage so that the common voltage has a waveform consisting of a curve projecting upward or downward by which the difference between video signal voltage and the common voltage is the minimum at the center part of the screen in every horizontal and vertical periods to uniformly compensate the flicker levels of the central part and both end parts of the display screen. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an active matrix type liquid crystal display device, and more particularly, to a liquid crystal display device capable of uniformly correcting a flicker level between a central portion and a peripheral portion of a display screen.
[0002]
[Prior art]
Conventionally, some proposals have been made as measures against flicker of an active matrix type liquid crystal display device (for example, see Patent Documents 1 to 3).
Generally, a drive circuit of an active matrix type liquid crystal display device is configured as shown in FIG. That is, the liquid crystal module 1 is composed of the panel 2, the horizontal shift register 3, the vertical shift register 4, and the common electrode 5, and these are driven by the control signal generation circuit 6, the S / H drive circuit 7, and the common voltage adjustment circuit 8. The control signal generation circuit 6 generates a signal HST (horizontal start pulse) and a signal HCK (horizontal clock pulse) and sends them to the horizontal shift register 3, and at the same time, a signal VST (vertical start pulse) and a signal VCK (vertical clock pulse). Is generated and sent to the vertical shift register 4, and a signal FRP is generated and sent to the S / H drive circuit 7. The S / H drive circuit 7 samples the input video signal at predetermined intervals and sends it to the horizontal shift register 3, and inverts the polarity of the signal at the timing of the signal FRP. The horizontal shift register 3 starts operating when the signal HST is input, and sequentially applies the video signal voltage to the panel 2 at the timing of the signal HCK. The vertical shift register 4 starts operating when the signal VST is input, and sequentially applies a predetermined gate voltage to the panel 2 at the timing of the signal VCK. The common voltage adjusting circuit 8 sends a common signal to the common electrode 5 and applies a common voltage of the common signal to the panel 2.
[0003]
FIG. 7 shows a video signal output from the S / H drive circuit 7 and a common signal output from the common voltage adjustment circuit 8 in FIG. 6, and the video signal is common every one horizontal period (1H) at the timing of the signal FRP. The polarity is inverted for the signal. Here, the common signal is adjusted to an intermediate voltage between the video signal before inversion and the video signal after inversion so that the flicker level becomes uniform.
Similarly, FIG. 8 shows a video signal output from the S / H drive circuit 7 and a common signal output from the common voltage adjustment circuit 8 in FIG. 6, and the video signal is one vertical period (1 V) at the timing of the signal FRP. Each time the polarity is inverted with respect to the common signal. Here, the common signal is adjusted to an intermediate voltage between the video signal before inversion and the video signal after inversion so that the flicker level becomes uniform.
[0004]
[Patent Document 1]
JP-A-10-62741 (pages 4-7, FIGS. 1-8)
[Patent Document 2]
JP-A-2000-322031 (page 6-9, FIG. 1)
[Patent Document 3]
JP-A-2000-193938 (pages 4-5, FIGS. 5-9)
[0005]
[Problems to be solved by the invention]
By the way, in a liquid crystal projector or the like, when there is an in-plane distribution in the intensity and the divergence angle of the light source, the minute leak amount of the pixel differs. The optimum common voltage in the plane slightly shifts due to the minute leak amount. The electrodes forming the storage capacitor of the pixel are wired from the left and right, and this wiring has some noise during driving. Therefore, the optimum common voltage is shifted between the left and right ends that are not easily affected by noise and the central portion that is easily affected by noise. The same applies to the upper and lower ends and the center. As described above, the common voltage is shifted in the screen due to the optical factor of the light source and the process factor of the liquid crystal panel. However, if the voltage applied to the common electrode is DC, the flicker level becomes non-uniform. The conventional technique described above does not provide a sufficient measure against the problem that the flicker level becomes uneven.
Therefore, an object of the present invention is to propose a liquid crystal display device which can correct the non-uniformity of the flicker level generated between the upper, lower, left, and right ends of the screen and the center.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, a liquid crystal display device according to the present invention includes a liquid crystal module including a liquid crystal element, a horizontal shift register, a vertical shift register, a common electrode, a control signal generation circuit, an S / H drive circuit, A common voltage adjusting circuit for inverting the polarity of the video signal with respect to the common voltage every horizontal cycle and vertical cycle. The differential voltage is corrected to a common voltage having a waveform having an upwardly or downwardly convex curve that is minimum at the center of the screen. This makes it possible to uniformly correct the flicker level between the center and both ends of the display screen.
[0007]
Here, the common voltage correction circuit corrects the common voltage at the center of the screen with respect to the common voltage at both ends of the screen to a voltage at which the flicker level becomes uniform.
Further, a peak value adjusting circuit for adjusting the peak value of the common voltage at the center of the screen is provided in the common voltage correcting circuit, and the peak value of the common voltage is adjusted.
Further, the waveform of the common voltage can be a parabolic waveform.
Furthermore, the common voltage correction circuit is constituted by a horizontal parabola wave generation circuit, a vertical parabola wave generation circuit, and a horizontal and vertical parabola wave amplitude adjustment circuit, and adjusts the amplitude of the parabola wave for each of the horizontal period and the vertical period. It is also possible.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a drive circuit of an active matrix type liquid crystal display device according to the present invention. As shown in the figure, the liquid crystal module 1 is composed of a panel 2, which is a liquid crystal element, a horizontal shift register 3, a vertical shift register 4, a common electrode 5, etc., and these components are controlled by a control signal generation circuit 6, an S / H drive circuit 7, Driven by the common voltage adjustment circuit 8.
[0009]
The control signal generation circuit 6 generates a signal HST (horizontal start pulse) and a signal HCK (horizontal clock pulse) and sends them to the horizontal shift register 3, and at the same time, a signal VST (vertical start pulse) and a signal VCK (vertical clock pulse). And sends it to the vertical shift register 4, further generates a signal FRP and sends it to the S / H drive circuit 7, and further generates a signal HD and a signal VD to generate a horizontal parabola wave generation circuit 11 and a vertical parabola respectively. The signal is sent to the wave generation circuit 12.
[0010]
The S / H drive circuit 7 samples the input video signal at a predetermined interval and sends it to the horizontal shift register 3, and inverts the polarity of the signal at the timing of the signal FRP every horizontal cycle and vertical cycle. The horizontal shift register 3 starts operating when the signal HST is input, and sequentially applies the video signal voltage to the panel 2 at the timing of the signal HCK. The vertical shift register 4 starts operating when the signal VST is input, and sequentially applies a predetermined gate voltage to the panel 2 at the timing of the signal VCK.
[0011]
The horizontal parabolic wave generation circuit 11 generates a common voltage signal having a waveform consisting of a parabolic curve in which the differential pressure between the video signal voltage and the common voltage is minimized at the timing of the input signal HD every horizontal cycle at the center of the screen. The amplitude of the waveform of the common voltage signal is adjusted by the parabolic wave amplitude adjustment circuit 13 and output. The vertical parabolic wave generation circuit 12 generates a common voltage signal having a waveform consisting of a parabolic curve in which the differential pressure between the video signal voltage and the common voltage is minimized at the timing of the input signal VD for each vertical cycle at the center of the screen. The amplitude of the waveform of the common voltage signal is adjusted by the parabolic wave amplitude adjusting circuit 14 and output.
[0012]
In the parabolic wave amplitude adjusting circuits 13 and 14, which are peak value adjusting circuits, the amplitude of the peak value at the center of the wavelength of the common voltage signal having a parabolic waveform is changed so that the flicker level becomes uniform between the center and both ends of the screen. Adjusted. The two common signals output from the horizontal parabolic wave generating circuit 11 and the vertical parabolic wave generating circuit 12 are sent to the common voltage adjusting circuit 8 after being mixed. The common voltage adjusting circuit 8 inverts the waveform of the common signal every horizontal cycle and vertical cycle at the timing of the signal FRP, sends the inverted signal to the common electrode 5, and sequentially applies the common voltage of the common signal to the panel 2.
[0013]
2 shows a video signal output from the S / H drive circuit 7 in FIG. 1 and a common signal output from the common voltage adjustment circuit 8, and FIG. 3 shows a waveform of a voltage of one common period (1H) of the common signal. FIG. The polarity of the video signal is inverted with respect to the common signal every one horizontal period (1H) at the timing of the signal FRP. Here, the common signal is adjusted to an intermediate voltage between the video signal before inversion and the video signal after inversion so that the flicker level is minimized. Is corrected to be minimum. The peak value at the center of the wavelength is a value at which the flicker level becomes uniform between the center of the screen and the left and right ends.
[0014]
FIG. 4 also shows a video signal output from the S / H drive circuit 7 of FIG. 1 and a common signal output from the common voltage adjustment circuit 8, and FIG. 5 shows a waveform of a voltage of one vertical period (1V) of the common signal. FIG. The polarity of the video signal is inverted with respect to the common signal every horizontal period (1H) and every vertical period (1V) at the timing of the signal FRP. Here, the common signal is adjusted to an intermediate voltage between the video signal before inversion and the video signal after inversion so that the flicker level is minimized. Is corrected to be minimum. The peak value at the center of the wavelength is a value at which the flicker level becomes uniform between the center of the screen and the upper and lower ends.
[0015]
As described above, in the embodiment of the present invention, the horizontal parabolic wave generating circuit 11, the vertical parabolic wave generating circuit 12, and the parabolic wave amplitude adjusting circuits 13 and 14 are provided in the driving circuit section of the conventional active matrix type liquid crystal display device. As a result, it is possible to eliminate the non-uniformity of the flicker level that occurs between the central portion of the screen and the left, right, upper, and lower peripheral portions.
In the above-described embodiment, the waveform of the common signal is a parabola, but other curves may be used as long as the waveform is similar. In the present invention, the parabola wave is superimposed on the common signal, but it can be superimposed on the video signal.
[0016]
【The invention's effect】
As described above, according to the present invention, the drive circuit of the active matrix type liquid crystal display device is provided with the common voltage correction circuit, and the differential pressure between the video signal voltage and the common voltage is set at the center of the screen every horizontal cycle and vertical cycle. By correcting to a common voltage having a waveform having an upward or downward convex curve which is minimized, the flicker level is uniformly corrected between the center and both ends of the display screen.
In addition, when the present invention is applied to a liquid crystal projector, it is possible to uniformly correct the non-uniformity of the flicker level on the screen caused by the deterioration of the optical characteristics of the liquid crystal projector and the characteristics of the liquid crystal panel element, thereby achieving a balance. Fine flicker can be fine-tuned.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a drive circuit of an active matrix type liquid crystal display device according to the present invention.
FIG. 2 is a waveform diagram showing a video signal and a common signal output in FIG.
FIG. 3 is a waveform diagram showing a waveform of a voltage of a common signal during one horizontal period (1H).
FIG. 4 is a waveform diagram showing a video signal and a common signal output in FIG.
FIG. 5 is a waveform diagram showing a waveform of a voltage of one common period (1 V) of the common signal.
FIG. 6 is a block diagram illustrating a configuration of a driving circuit of a conventional liquid crystal display device.
FIG. 7 is a waveform diagram showing a conventional video signal and a common signal.
FIG. 8 is a waveform diagram showing a conventional video signal and a common signal.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Liquid crystal module 2 Panel 3 Horizontal shift register 4 Vertical shift register 5 Common electrode 6 Control signal generation circuit 7 S / H drive circuit 8 Common voltage adjustment circuit 11 Horizontal parabolic wave generation circuit 12 Vertical parabolic wave generation circuit 13, 14 Parabolic wave amplitude Adjustment circuit

Claims (5)

A liquid crystal module including a liquid crystal element, a horizontal shift register, a vertical shift register, a common electrode, and the like, a control signal generation circuit, an S / H drive circuit, and a common voltage adjustment circuit are provided. In a liquid crystal display device inverting the polarity of a video signal with respect to
A common voltage correction circuit for correcting the differential voltage between the video signal voltage and the common voltage at the horizontal center and the vertical cycle to a common voltage having a waveform having an upwardly or downwardly convex curve that is minimum at the center of the screen. Characteristic liquid crystal display device. 2. The liquid crystal display device according to claim 1, wherein the common voltage correction circuit corrects the common voltage at the center of the screen with respect to the common voltage at both ends of the screen to a voltage at which the flicker level becomes uniform. 3. The liquid crystal display device according to claim 1, wherein the common voltage correction circuit includes a peak value adjustment circuit that adjusts a peak value of a common voltage at a central portion of a screen. 4. The liquid crystal display device according to claim 1, wherein the waveform of the common voltage is a parabolic waveform. 5. The liquid crystal display device according to claim 4, wherein said common voltage correction circuit comprises a horizontal parabolic wave generating circuit, a vertical parabolic wave generating circuit, and horizontal and vertical parabolic wave amplitude adjusting circuits.

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